2018-05-03 03:18:29 +08:00
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Freescale i.MX7ULP LPSPI driver
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//
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// Copyright 2016 Freescale Semiconductor, Inc.
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2016-11-22 21:52:17 +08:00
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/types.h>
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#define DRIVER_NAME "fsl_lpspi"
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/* i.MX7ULP LPSPI registers */
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#define IMX7ULP_VERID 0x0
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#define IMX7ULP_PARAM 0x4
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#define IMX7ULP_CR 0x10
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#define IMX7ULP_SR 0x14
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#define IMX7ULP_IER 0x18
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#define IMX7ULP_DER 0x1c
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#define IMX7ULP_CFGR0 0x20
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#define IMX7ULP_CFGR1 0x24
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#define IMX7ULP_DMR0 0x30
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#define IMX7ULP_DMR1 0x34
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#define IMX7ULP_CCR 0x40
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#define IMX7ULP_FCR 0x58
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#define IMX7ULP_FSR 0x5c
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#define IMX7ULP_TCR 0x60
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#define IMX7ULP_TDR 0x64
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#define IMX7ULP_RSR 0x70
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#define IMX7ULP_RDR 0x74
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/* General control register field define */
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#define CR_RRF BIT(9)
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#define CR_RTF BIT(8)
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#define CR_RST BIT(1)
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#define CR_MEN BIT(0)
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#define SR_TCF BIT(10)
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#define SR_RDF BIT(1)
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#define SR_TDF BIT(0)
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#define IER_TCIE BIT(10)
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#define IER_RDIE BIT(1)
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#define IER_TDIE BIT(0)
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#define CFGR1_PCSCFG BIT(27)
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#define CFGR1_PCSPOL BIT(8)
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#define CFGR1_NOSTALL BIT(3)
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#define CFGR1_MASTER BIT(0)
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#define RSR_RXEMPTY BIT(1)
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#define TCR_CPOL BIT(31)
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#define TCR_CPHA BIT(30)
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#define TCR_CONT BIT(21)
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#define TCR_CONTC BIT(20)
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#define TCR_RXMSK BIT(19)
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#define TCR_TXMSK BIT(18)
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static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
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struct lpspi_config {
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u8 bpw;
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u8 chip_select;
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u8 prescale;
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u16 mode;
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u32 speed_hz;
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};
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struct fsl_lpspi_data {
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struct device *dev;
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void __iomem *base;
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struct clk *clk;
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void *rx_buf;
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const void *tx_buf;
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void (*tx)(struct fsl_lpspi_data *);
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void (*rx)(struct fsl_lpspi_data *);
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u32 remain;
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u8 txfifosize;
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u8 rxfifosize;
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struct lpspi_config config;
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struct completion xfer_done;
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};
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static const struct of_device_id fsl_lpspi_dt_ids[] = {
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{ .compatible = "fsl,imx7ulp-spi", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
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#define LPSPI_BUF_RX(type) \
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static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
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{ \
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unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
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\
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if (fsl_lpspi->rx_buf) { \
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*(type *)fsl_lpspi->rx_buf = val; \
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fsl_lpspi->rx_buf += sizeof(type); \
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} \
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}
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#define LPSPI_BUF_TX(type) \
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static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
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{ \
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type val = 0; \
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\
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if (fsl_lpspi->tx_buf) { \
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val = *(type *)fsl_lpspi->tx_buf; \
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fsl_lpspi->tx_buf += sizeof(type); \
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} \
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\
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fsl_lpspi->remain -= sizeof(type); \
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writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
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}
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LPSPI_BUF_RX(u8)
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LPSPI_BUF_TX(u8)
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LPSPI_BUF_RX(u16)
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LPSPI_BUF_TX(u16)
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LPSPI_BUF_RX(u32)
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LPSPI_BUF_TX(u32)
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static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
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unsigned int enable)
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{
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writel(enable, fsl_lpspi->base + IMX7ULP_IER);
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}
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2016-11-24 19:04:44 +08:00
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static int lpspi_prepare_xfer_hardware(struct spi_master *master)
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2016-11-22 21:52:17 +08:00
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{
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struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
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return clk_prepare_enable(fsl_lpspi->clk);
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}
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2016-11-24 19:04:44 +08:00
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static int lpspi_unprepare_xfer_hardware(struct spi_master *master)
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2016-11-22 21:52:17 +08:00
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{
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struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
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clk_disable_unprepare(fsl_lpspi->clk);
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return 0;
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}
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static int fsl_lpspi_txfifo_empty(struct fsl_lpspi_data *fsl_lpspi)
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{
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u32 txcnt;
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unsigned long orig_jiffies = jiffies;
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do {
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txcnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
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if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
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dev_dbg(fsl_lpspi->dev, "txfifo empty timeout\n");
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return -ETIMEDOUT;
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}
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2016-11-24 19:04:42 +08:00
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cond_resched();
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2016-11-22 21:52:17 +08:00
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} while (txcnt);
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return 0;
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}
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static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
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{
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u8 txfifo_cnt;
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txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
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while (txfifo_cnt < fsl_lpspi->txfifosize) {
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if (!fsl_lpspi->remain)
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break;
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fsl_lpspi->tx(fsl_lpspi);
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txfifo_cnt++;
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}
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if (!fsl_lpspi->remain && (txfifo_cnt < fsl_lpspi->txfifosize))
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writel(0, fsl_lpspi->base + IMX7ULP_TDR);
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else
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fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
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}
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static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
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{
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while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
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fsl_lpspi->rx(fsl_lpspi);
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}
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static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi,
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bool is_first_xfer)
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{
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u32 temp = 0;
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temp |= fsl_lpspi->config.bpw - 1;
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temp |= fsl_lpspi->config.prescale << 27;
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2016-11-24 19:04:43 +08:00
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temp |= (fsl_lpspi->config.mode & 0x3) << 30;
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2016-11-22 21:52:17 +08:00
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temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
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/*
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* Set TCR_CONT will keep SS asserted after current transfer.
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* For the first transfer, clear TCR_CONTC to assert SS.
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* For subsequent transfer, set TCR_CONTC to keep SS asserted.
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*/
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temp |= TCR_CONT;
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if (is_first_xfer)
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temp &= ~TCR_CONTC;
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else
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temp |= TCR_CONTC;
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writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
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dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
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}
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static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
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{
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u32 temp;
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2016-11-28 11:03:00 +08:00
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temp = fsl_lpspi->txfifosize >> 1 | (fsl_lpspi->rxfifosize >> 1) << 16;
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2016-11-22 21:52:17 +08:00
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writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
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dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
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}
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static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
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{
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struct lpspi_config config = fsl_lpspi->config;
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unsigned int perclk_rate, scldiv;
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u8 prescale;
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perclk_rate = clk_get_rate(fsl_lpspi->clk);
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for (prescale = 0; prescale < 8; prescale++) {
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scldiv = perclk_rate /
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(clkdivs[prescale] * config.speed_hz) - 2;
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if (scldiv < 256) {
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fsl_lpspi->config.prescale = prescale;
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break;
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}
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}
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if (prescale == 8 && scldiv >= 256)
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return -EINVAL;
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writel(scldiv, fsl_lpspi->base + IMX7ULP_CCR);
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dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale =%d, scldiv=%d\n",
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perclk_rate, config.speed_hz, prescale, scldiv);
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return 0;
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}
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static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
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{
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u32 temp;
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int ret;
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temp = CR_RST;
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writel(temp, fsl_lpspi->base + IMX7ULP_CR);
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writel(0, fsl_lpspi->base + IMX7ULP_CR);
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ret = fsl_lpspi_set_bitrate(fsl_lpspi);
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if (ret)
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return ret;
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fsl_lpspi_set_watermark(fsl_lpspi);
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2018-10-02 19:06:36 +08:00
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temp = CFGR1_PCSCFG | CFGR1_MASTER;
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2016-11-22 21:52:17 +08:00
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if (fsl_lpspi->config.mode & SPI_CS_HIGH)
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temp |= CFGR1_PCSPOL;
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writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
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temp = readl(fsl_lpspi->base + IMX7ULP_CR);
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temp |= CR_RRF | CR_RTF | CR_MEN;
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writel(temp, fsl_lpspi->base + IMX7ULP_CR);
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return 0;
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}
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static void fsl_lpspi_setup_transfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(spi->master);
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fsl_lpspi->config.mode = spi->mode;
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fsl_lpspi->config.bpw = t ? t->bits_per_word : spi->bits_per_word;
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fsl_lpspi->config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
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fsl_lpspi->config.chip_select = spi->chip_select;
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if (!fsl_lpspi->config.speed_hz)
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fsl_lpspi->config.speed_hz = spi->max_speed_hz;
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if (!fsl_lpspi->config.bpw)
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fsl_lpspi->config.bpw = spi->bits_per_word;
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/* Initialize the functions for transfer */
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if (fsl_lpspi->config.bpw <= 8) {
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fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
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fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
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} else if (fsl_lpspi->config.bpw <= 16) {
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fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
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fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
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} else {
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fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
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fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
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}
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fsl_lpspi_config(fsl_lpspi);
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}
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static int fsl_lpspi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
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int ret;
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fsl_lpspi->tx_buf = t->tx_buf;
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fsl_lpspi->rx_buf = t->rx_buf;
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fsl_lpspi->remain = t->len;
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reinit_completion(&fsl_lpspi->xfer_done);
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fsl_lpspi_write_tx_fifo(fsl_lpspi);
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2016-11-28 11:02:59 +08:00
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ret = wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ);
|
|
|
|
if (!ret) {
|
|
|
|
dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
2016-11-22 21:52:17 +08:00
|
|
|
|
|
|
|
ret = fsl_lpspi_txfifo_empty(fsl_lpspi);
|
2016-12-02 11:50:01 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2016-11-22 21:52:17 +08:00
|
|
|
fsl_lpspi_read_rx_fifo(fsl_lpspi);
|
|
|
|
|
2016-12-02 11:50:01 +08:00
|
|
|
return 0;
|
2016-11-22 21:52:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_lpspi_transfer_one_msg(struct spi_master *master,
|
|
|
|
struct spi_message *msg)
|
|
|
|
{
|
|
|
|
struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
|
|
|
|
struct spi_device *spi = msg->spi;
|
|
|
|
struct spi_transfer *xfer;
|
|
|
|
bool is_first_xfer = true;
|
|
|
|
u32 temp;
|
2016-12-14 19:20:55 +08:00
|
|
|
int ret = 0;
|
2016-11-22 21:52:17 +08:00
|
|
|
|
|
|
|
msg->status = 0;
|
|
|
|
msg->actual_length = 0;
|
|
|
|
|
|
|
|
list_for_each_entry(xfer, &msg->transfers, transfer_list) {
|
|
|
|
fsl_lpspi_setup_transfer(spi, xfer);
|
|
|
|
fsl_lpspi_set_cmd(fsl_lpspi, is_first_xfer);
|
|
|
|
|
|
|
|
is_first_xfer = false;
|
|
|
|
|
|
|
|
ret = fsl_lpspi_transfer_one(master, spi, xfer);
|
|
|
|
if (ret < 0)
|
|
|
|
goto complete;
|
|
|
|
|
|
|
|
msg->actual_length += xfer->len;
|
|
|
|
}
|
|
|
|
|
|
|
|
complete:
|
|
|
|
/* de-assert SS, then finalize current message */
|
|
|
|
temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
|
|
|
|
temp &= ~TCR_CONTC;
|
|
|
|
writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
|
|
|
|
|
|
|
|
msg->status = ret;
|
|
|
|
spi_finalize_current_message(master);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct fsl_lpspi_data *fsl_lpspi = dev_id;
|
|
|
|
u32 temp;
|
|
|
|
|
|
|
|
fsl_lpspi_intctrl(fsl_lpspi, 0);
|
|
|
|
temp = readl(fsl_lpspi->base + IMX7ULP_SR);
|
|
|
|
|
|
|
|
fsl_lpspi_read_rx_fifo(fsl_lpspi);
|
|
|
|
|
|
|
|
if (temp & SR_TDF) {
|
|
|
|
fsl_lpspi_write_tx_fifo(fsl_lpspi);
|
|
|
|
|
|
|
|
if (!fsl_lpspi->remain)
|
|
|
|
complete(&fsl_lpspi->xfer_done);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_lpspi_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct fsl_lpspi_data *fsl_lpspi;
|
|
|
|
struct spi_master *master;
|
|
|
|
struct resource *res;
|
|
|
|
int ret, irq;
|
2016-11-28 11:03:00 +08:00
|
|
|
u32 temp;
|
2016-11-22 21:52:17 +08:00
|
|
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_lpspi_data));
|
|
|
|
if (!master)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
|
|
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
|
|
|
|
master->bus_num = pdev->id;
|
|
|
|
|
|
|
|
fsl_lpspi = spi_master_get_devdata(master);
|
|
|
|
fsl_lpspi->dev = &pdev->dev;
|
|
|
|
|
|
|
|
master->transfer_one_message = fsl_lpspi_transfer_one_msg;
|
2016-11-24 19:04:44 +08:00
|
|
|
master->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
|
|
|
|
master->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
|
2016-11-22 21:52:17 +08:00
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
|
master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
|
|
master->bus_num = pdev->id;
|
|
|
|
|
|
|
|
init_completion(&fsl_lpspi->xfer_done);
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(fsl_lpspi->base)) {
|
|
|
|
ret = PTR_ERR(fsl_lpspi->base);
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
|
|
ret = irq;
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
|
|
|
|
dev_name(&pdev->dev), fsl_lpspi);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
fsl_lpspi->clk = devm_clk_get(&pdev->dev, "ipg");
|
|
|
|
if (IS_ERR(fsl_lpspi->clk)) {
|
|
|
|
ret = PTR_ERR(fsl_lpspi->clk);
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
2016-11-28 11:03:00 +08:00
|
|
|
ret = clk_prepare_enable(fsl_lpspi->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "can't enable lpspi clock, ret=%d\n", ret);
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
|
|
|
|
fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
|
|
|
|
fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
|
|
|
|
|
|
|
|
clk_disable_unprepare(fsl_lpspi->clk);
|
|
|
|
|
2016-11-22 21:52:17 +08:00
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "spi_register_master error.\n");
|
|
|
|
goto out_master_put;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_master_put:
|
|
|
|
spi_master_put(master);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_lpspi_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
|
|
struct fsl_lpspi_data *fsl_lpspi = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
clk_disable_unprepare(fsl_lpspi->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver fsl_lpspi_driver = {
|
|
|
|
.driver = {
|
2017-01-04 17:38:16 +08:00
|
|
|
.name = DRIVER_NAME,
|
|
|
|
.of_match_table = fsl_lpspi_dt_ids,
|
|
|
|
},
|
2016-11-22 21:52:17 +08:00
|
|
|
.probe = fsl_lpspi_probe,
|
|
|
|
.remove = fsl_lpspi_remove,
|
|
|
|
};
|
|
|
|
module_platform_driver(fsl_lpspi_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("LPSPI Master Controller driver");
|
|
|
|
MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
|
2016-12-02 11:50:00 +08:00
|
|
|
MODULE_LICENSE("GPL");
|