2007-07-17 19:04:13 +08:00
|
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/*
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* OMAP2 McSPI controller driver
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*
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* Copyright (C) 2005, 2006 Nokia Corporation
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* Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
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2011-02-02 20:22:14 +08:00
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* Juha Yrj<EFBFBD>l<EFBFBD> <juha.yrjola@nokia.com>
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2007-07-17 19:04:13 +08:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
|
2012-04-23 20:51:48 +08:00
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#include <linux/dmaengine.h>
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2015-11-19 23:18:28 +08:00
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#include <linux/pinctrl/consumer.h>
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2007-07-17 19:04:13 +08:00
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
|
2011-02-02 20:22:15 +08:00
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#include <linux/pm_runtime.h>
|
2012-02-16 01:37:34 +08:00
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#include <linux/of.h>
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#include <linux/of_device.h>
|
2013-06-17 21:31:06 +08:00
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#include <linux/gcd.h>
|
2018-10-15 14:38:27 +08:00
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#include <linux/iopoll.h>
|
2007-07-17 19:04:13 +08:00
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#include <linux/spi/spi.h>
|
2015-05-09 02:31:01 +08:00
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#include <linux/gpio.h>
|
2007-07-17 19:04:13 +08:00
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|
2012-08-24 21:21:06 +08:00
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#include <linux/platform_data/spi-omap2-mcspi.h>
|
2007-07-17 19:04:13 +08:00
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#define OMAP2_MCSPI_MAX_FREQ 48000000
|
2014-02-02 23:24:25 +08:00
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#define OMAP2_MCSPI_MAX_DIVIDER 4096
|
2013-06-17 21:31:06 +08:00
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#define OMAP2_MCSPI_MAX_FIFODEPTH 64
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#define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
|
2012-03-26 19:34:22 +08:00
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#define SPI_AUTOSUSPEND_TIMEOUT 2000
|
2007-07-17 19:04:13 +08:00
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#define OMAP2_MCSPI_REVISION 0x00
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#define OMAP2_MCSPI_SYSSTATUS 0x14
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#define OMAP2_MCSPI_IRQSTATUS 0x18
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#define OMAP2_MCSPI_IRQENABLE 0x1c
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#define OMAP2_MCSPI_WAKEUPENABLE 0x20
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#define OMAP2_MCSPI_SYST 0x24
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#define OMAP2_MCSPI_MODULCTRL 0x28
|
2013-06-17 21:31:06 +08:00
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#define OMAP2_MCSPI_XFERLEVEL 0x7c
|
2007-07-17 19:04:13 +08:00
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/* per-channel banks, 0x14 bytes each, first is: */
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#define OMAP2_MCSPI_CHCONF0 0x2c
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#define OMAP2_MCSPI_CHSTAT0 0x30
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#define OMAP2_MCSPI_CHCTRL0 0x34
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#define OMAP2_MCSPI_TX0 0x38
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#define OMAP2_MCSPI_RX0 0x3c
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/* per-register bitmasks: */
|
2013-06-17 21:31:06 +08:00
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#define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
|
2007-07-17 19:04:13 +08:00
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|
2009-09-23 07:45:58 +08:00
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#define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
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#define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
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#define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
|
2007-07-17 19:04:13 +08:00
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2009-09-23 07:45:58 +08:00
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#define OMAP2_MCSPI_CHCONF_PHA BIT(0)
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#define OMAP2_MCSPI_CHCONF_POL BIT(1)
|
2007-07-17 19:04:13 +08:00
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#define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
|
2009-09-23 07:45:58 +08:00
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#define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
|
2007-07-17 19:04:13 +08:00
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#define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
|
2009-09-23 07:45:58 +08:00
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#define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
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#define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
|
2007-07-17 19:04:13 +08:00
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#define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
|
2009-09-23 07:45:58 +08:00
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#define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
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#define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
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#define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
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#define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
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#define OMAP2_MCSPI_CHCONF_IS BIT(18)
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#define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
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#define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
|
2013-06-17 21:31:06 +08:00
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#define OMAP2_MCSPI_CHCONF_FFET BIT(27)
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#define OMAP2_MCSPI_CHCONF_FFER BIT(28)
|
2014-02-02 23:24:25 +08:00
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#define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
|
2007-07-17 19:04:13 +08:00
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|
2009-09-23 07:45:58 +08:00
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#define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
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#define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
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#define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
|
2013-06-17 21:31:06 +08:00
|
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#define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
|
2007-07-17 19:04:13 +08:00
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|
2009-09-23 07:45:58 +08:00
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#define OMAP2_MCSPI_CHCTRL_EN BIT(0)
|
2014-02-02 23:24:25 +08:00
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#define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
|
2007-07-17 19:04:13 +08:00
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|
2009-09-23 07:45:58 +08:00
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#define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
|
2007-07-17 19:04:13 +08:00
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/* We have 2 DMA channels per CS, one for RX and one for TX */
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struct omap2_mcspi_dma {
|
2012-04-23 20:51:48 +08:00
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struct dma_chan *dma_tx;
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struct dma_chan *dma_rx;
|
2007-07-17 19:04:13 +08:00
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struct completion dma_tx_completion;
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struct completion dma_rx_completion;
|
2013-06-23 01:37:38 +08:00
|
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char dma_rx_ch_name[14];
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char dma_tx_ch_name[14];
|
2007-07-17 19:04:13 +08:00
|
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};
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/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
|
|
|
|
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* cache operations; better heuristics consider wordsize and bitrate.
|
|
|
|
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*/
|
2010-04-12 17:07:54 +08:00
|
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|
#define DMA_MIN_BYTES 160
|
2007-07-17 19:04:13 +08:00
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|
2012-03-26 18:02:33 +08:00
|
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|
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/*
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|
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|
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* Used for context save and restore, structure members to be updated whenever
|
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|
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* corresponding registers are modified.
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*/
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struct omap2_mcspi_regs {
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u32 modulctrl;
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u32 wakeupenable;
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struct list_head cs;
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};
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|
2007-07-17 19:04:13 +08:00
|
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|
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struct omap2_mcspi {
|
2018-10-15 14:38:29 +08:00
|
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struct completion txdone;
|
2007-07-17 19:04:13 +08:00
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struct spi_master *master;
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/* Virtual base address of the controller */
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void __iomem *base;
|
2008-09-02 04:51:50 +08:00
|
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|
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unsigned long phys;
|
2007-07-17 19:04:13 +08:00
|
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/* SPI1 has 4 channels, while SPI2 has 2 */
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struct omap2_mcspi_dma *dma_channels;
|
2012-03-26 18:02:33 +08:00
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struct device *dev;
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struct omap2_mcspi_regs ctx;
|
2013-06-17 21:31:06 +08:00
|
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int fifo_depth;
|
2018-10-15 14:38:29 +08:00
|
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bool slave_aborted;
|
2012-10-08 00:19:44 +08:00
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unsigned int pin_dir:1;
|
2007-07-17 19:04:13 +08:00
|
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};
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struct omap2_mcspi_cs {
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void __iomem *base;
|
2008-09-02 04:51:50 +08:00
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unsigned long phys;
|
2007-07-17 19:04:13 +08:00
|
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int word_len;
|
2014-07-02 11:28:32 +08:00
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u16 mode;
|
2009-09-23 07:46:17 +08:00
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struct list_head node;
|
2009-09-23 07:46:16 +08:00
|
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/* Context save and restore shadow register */
|
2014-02-02 23:24:25 +08:00
|
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u32 chconf0, chctrl0;
|
2009-09-23 07:46:16 +08:00
|
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};
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|
2007-07-17 19:04:13 +08:00
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static inline void mcspi_write_reg(struct spi_master *master,
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int idx, u32 val)
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{
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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|
2013-11-16 08:01:16 +08:00
|
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writel_relaxed(val, mcspi->base + idx);
|
2007-07-17 19:04:13 +08:00
|
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}
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static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
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{
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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|
2013-11-16 08:01:16 +08:00
|
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return readl_relaxed(mcspi->base + idx);
|
2007-07-17 19:04:13 +08:00
|
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}
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static inline void mcspi_write_cs_reg(const struct spi_device *spi,
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int idx, u32 val)
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|
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{
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|
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struct omap2_mcspi_cs *cs = spi->controller_state;
|
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|
2013-11-16 08:01:16 +08:00
|
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writel_relaxed(val, cs->base + idx);
|
2007-07-17 19:04:13 +08:00
|
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|
|
}
|
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static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
|
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|
|
{
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|
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struct omap2_mcspi_cs *cs = spi->controller_state;
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|
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|
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|
2013-11-16 08:01:16 +08:00
|
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return readl_relaxed(cs->base + idx);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
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|
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|
2009-09-23 07:46:16 +08:00
|
|
|
|
static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
|
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{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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return cs->chconf0;
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}
|
|
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static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
|
|
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|
{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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cs->chconf0 = val;
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mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
|
2010-03-15 17:06:28 +08:00
|
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|
mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
|
2009-09-23 07:46:16 +08:00
|
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|
|
}
|
|
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|
2013-06-15 00:12:07 +08:00
|
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|
static inline int mcspi_bytes_per_word(int word_len)
|
|
|
|
|
{
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|
|
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|
if (word_len <= 8)
|
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|
return 1;
|
|
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|
else if (word_len <= 16)
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|
return 2;
|
|
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|
|
else /* word_len <= 32 */
|
|
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|
|
return 4;
|
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|
|
|
}
|
|
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|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
|
|
|
|
|
int is_read, int enable)
|
|
|
|
|
{
|
|
|
|
|
u32 l, rw;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
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|
|
l = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
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|
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|
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|
|
if (is_read) /* 1 is read, 0 write */
|
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|
|
rw = OMAP2_MCSPI_CHCONF_DMAR;
|
|
|
|
|
else
|
|
|
|
|
rw = OMAP2_MCSPI_CHCONF_DMAW;
|
|
|
|
|
|
2012-08-22 14:05:13 +08:00
|
|
|
|
if (enable)
|
|
|
|
|
l |= rw;
|
|
|
|
|
else
|
|
|
|
|
l &= ~rw;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
mcspi_write_chconf0(spi, l);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
|
|
|
|
|
{
|
2014-02-02 23:24:25 +08:00
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
u32 l;
|
|
|
|
|
|
2014-02-02 23:24:25 +08:00
|
|
|
|
l = cs->chctrl0;
|
|
|
|
|
if (enable)
|
|
|
|
|
l |= OMAP2_MCSPI_CHCTRL_EN;
|
|
|
|
|
else
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCTRL_EN;
|
|
|
|
|
cs->chctrl0 = l;
|
|
|
|
|
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
|
2010-04-13 18:41:51 +08:00
|
|
|
|
/* Flash post-writes */
|
|
|
|
|
mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2015-05-13 01:38:57 +08:00
|
|
|
|
static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
2015-07-23 02:46:09 +08:00
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
u32 l;
|
|
|
|
|
|
2015-05-24 10:13:43 +08:00
|
|
|
|
/* The controller handles the inverted chip selects
|
|
|
|
|
* using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
|
|
|
|
|
* the inversion from the core spi_set_cs function.
|
|
|
|
|
*/
|
|
|
|
|
if (spi->mode & SPI_CS_HIGH)
|
|
|
|
|
enable = !enable;
|
|
|
|
|
|
2015-05-13 01:38:57 +08:00
|
|
|
|
if (spi->controller_state) {
|
2015-07-23 02:46:09 +08:00
|
|
|
|
int err = pm_runtime_get_sync(mcspi->dev);
|
|
|
|
|
if (err < 0) {
|
2018-04-27 23:50:07 +08:00
|
|
|
|
pm_runtime_put_noidle(mcspi->dev);
|
2015-07-23 02:46:09 +08:00
|
|
|
|
dev_err(mcspi->dev, "failed to get sync: %d\n", err);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2015-05-13 01:38:57 +08:00
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2012-08-22 14:05:13 +08:00
|
|
|
|
|
2015-05-13 01:38:57 +08:00
|
|
|
|
if (enable)
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_FORCE;
|
|
|
|
|
else
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_FORCE;
|
|
|
|
|
|
|
|
|
|
mcspi_write_chconf0(spi, l);
|
2015-07-23 02:46:09 +08:00
|
|
|
|
|
|
|
|
|
pm_runtime_mark_last_busy(mcspi->dev);
|
|
|
|
|
pm_runtime_put_autosuspend(mcspi->dev);
|
2015-05-13 01:38:57 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
static void omap2_mcspi_set_mode(struct spi_master *master)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
2012-03-26 18:02:33 +08:00
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
u32 l;
|
|
|
|
|
|
2012-03-26 18:02:33 +08:00
|
|
|
|
/*
|
2018-10-15 14:38:29 +08:00
|
|
|
|
* Choose master or slave mode
|
2007-07-17 19:04:13 +08:00
|
|
|
|
*/
|
|
|
|
|
l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
|
2018-10-15 14:38:29 +08:00
|
|
|
|
l &= ~(OMAP2_MCSPI_MODULCTRL_STEST);
|
|
|
|
|
if (spi_controller_is_slave(master)) {
|
|
|
|
|
l |= (OMAP2_MCSPI_MODULCTRL_MS);
|
|
|
|
|
} else {
|
|
|
|
|
l &= ~(OMAP2_MCSPI_MODULCTRL_MS);
|
|
|
|
|
l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
|
2009-09-23 07:46:16 +08:00
|
|
|
|
|
2012-03-26 18:02:33 +08:00
|
|
|
|
ctx->modulctrl = l;
|
2009-09-23 07:46:16 +08:00
|
|
|
|
}
|
|
|
|
|
|
2013-06-17 21:31:06 +08:00
|
|
|
|
static void omap2_mcspi_set_fifo(const struct spi_device *spi,
|
|
|
|
|
struct spi_transfer *t, int enable)
|
|
|
|
|
{
|
|
|
|
|
struct spi_master *master = spi->master;
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
unsigned int wcnt;
|
2018-10-15 14:38:28 +08:00
|
|
|
|
int max_fifo_depth, bytes_per_word;
|
2013-06-17 21:31:06 +08:00
|
|
|
|
u32 chconf, xferlevel;
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
|
|
|
|
|
|
|
chconf = mcspi_cached_chconf0(spi);
|
|
|
|
|
if (enable) {
|
|
|
|
|
bytes_per_word = mcspi_bytes_per_word(cs->word_len);
|
|
|
|
|
if (t->len % bytes_per_word != 0)
|
|
|
|
|
goto disable_fifo;
|
|
|
|
|
|
2013-10-09 20:05:08 +08:00
|
|
|
|
if (t->rx_buf != NULL && t->tx_buf != NULL)
|
|
|
|
|
max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
|
|
|
|
|
else
|
|
|
|
|
max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
|
|
|
|
|
|
2013-06-17 21:31:06 +08:00
|
|
|
|
wcnt = t->len / bytes_per_word;
|
|
|
|
|
if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
|
|
|
|
|
goto disable_fifo;
|
|
|
|
|
|
|
|
|
|
xferlevel = wcnt << 16;
|
|
|
|
|
if (t->rx_buf != NULL) {
|
|
|
|
|
chconf |= OMAP2_MCSPI_CHCONF_FFER;
|
2018-10-15 14:38:28 +08:00
|
|
|
|
xferlevel |= (bytes_per_word - 1) << 8;
|
2013-10-09 20:05:08 +08:00
|
|
|
|
}
|
2018-10-15 14:38:28 +08:00
|
|
|
|
|
2013-10-09 20:05:08 +08:00
|
|
|
|
if (t->tx_buf != NULL) {
|
2013-06-17 21:31:06 +08:00
|
|
|
|
chconf |= OMAP2_MCSPI_CHCONF_FFET;
|
2018-10-15 14:38:28 +08:00
|
|
|
|
xferlevel |= bytes_per_word - 1;
|
2013-06-17 21:31:06 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
|
|
|
|
|
mcspi_write_chconf0(spi, chconf);
|
2018-10-15 14:38:28 +08:00
|
|
|
|
mcspi->fifo_depth = max_fifo_depth;
|
2013-06-17 21:31:06 +08:00
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
disable_fifo:
|
|
|
|
|
if (t->rx_buf != NULL)
|
|
|
|
|
chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
|
2014-08-10 05:06:58 +08:00
|
|
|
|
|
|
|
|
|
if (t->tx_buf != NULL)
|
2013-06-17 21:31:06 +08:00
|
|
|
|
chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
|
|
|
|
|
|
|
|
|
|
mcspi_write_chconf0(spi, chconf);
|
|
|
|
|
mcspi->fifo_depth = 0;
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-19 22:07:31 +08:00
|
|
|
|
static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
|
|
|
|
|
{
|
2018-10-15 14:38:27 +08:00
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
return readl_poll_timeout(reg, val, val & bit, 1, MSEC_PER_SEC);
|
2010-10-19 22:07:31 +08:00
|
|
|
|
}
|
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi,
|
|
|
|
|
struct completion *x)
|
|
|
|
|
{
|
|
|
|
|
if (spi_controller_is_slave(mcspi->master)) {
|
|
|
|
|
if (wait_for_completion_interruptible(x) ||
|
|
|
|
|
mcspi->slave_aborted)
|
|
|
|
|
return -EINTR;
|
|
|
|
|
} else {
|
|
|
|
|
wait_for_completion(x);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-23 20:51:48 +08:00
|
|
|
|
static void omap2_mcspi_rx_callback(void *data)
|
|
|
|
|
{
|
|
|
|
|
struct spi_device *spi = data;
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
|
|
|
|
/* We must disable the DMA RX request */
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 1, 0);
|
2012-12-12 16:45:59 +08:00
|
|
|
|
|
|
|
|
|
complete(&mcspi_dma->dma_rx_completion);
|
2012-04-23 20:51:48 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_tx_callback(void *data)
|
|
|
|
|
{
|
|
|
|
|
struct spi_device *spi = data;
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
|
|
|
|
/* We must disable the DMA TX request */
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 0, 0);
|
2012-12-12 16:45:59 +08:00
|
|
|
|
|
|
|
|
|
complete(&mcspi_dma->dma_tx_completion);
|
2012-04-23 20:51:48 +08:00
|
|
|
|
}
|
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
static void omap2_mcspi_tx_dma(struct spi_device *spi,
|
|
|
|
|
struct spi_transfer *xfer,
|
|
|
|
|
struct dma_slave_config cfg)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
if (mcspi_dma->dma_tx) {
|
2012-04-23 20:51:48 +08:00
|
|
|
|
struct dma_async_tx_descriptor *tx;
|
|
|
|
|
|
|
|
|
|
dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
|
|
|
|
|
|
2016-07-08 01:17:50 +08:00
|
|
|
|
tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
|
|
|
|
|
xfer->tx_sg.nents,
|
|
|
|
|
DMA_MEM_TO_DEV,
|
|
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
2012-04-23 20:51:48 +08:00
|
|
|
|
if (tx) {
|
|
|
|
|
tx->callback = omap2_mcspi_tx_callback;
|
|
|
|
|
tx->callback_param = spi;
|
|
|
|
|
dmaengine_submit(tx);
|
|
|
|
|
} else {
|
|
|
|
|
/* FIXME: fall back to PIO? */
|
|
|
|
|
}
|
|
|
|
|
}
|
2012-09-11 14:43:20 +08:00
|
|
|
|
dma_async_issue_pending(mcspi_dma->dma_tx);
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 0, 1);
|
|
|
|
|
|
|
|
|
|
}
|
2012-04-23 20:51:48 +08:00
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
static unsigned
|
|
|
|
|
omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
|
|
|
|
|
struct dma_slave_config cfg,
|
|
|
|
|
unsigned es)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
2016-07-08 01:17:50 +08:00
|
|
|
|
unsigned int count, transfer_reduction = 0;
|
|
|
|
|
struct scatterlist *sg_out[2];
|
|
|
|
|
int nb_sizes = 0, out_mapped_nents[2], ret, x;
|
|
|
|
|
size_t sizes[2];
|
2012-09-11 14:43:20 +08:00
|
|
|
|
u32 l;
|
|
|
|
|
int elements = 0;
|
|
|
|
|
int word_len, element_count;
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
2017-03-22 08:18:26 +08:00
|
|
|
|
void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
|
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
count = xfer->len;
|
2013-06-17 21:31:06 +08:00
|
|
|
|
|
2016-06-27 22:54:08 +08:00
|
|
|
|
/*
|
|
|
|
|
* In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
|
|
|
|
|
* it mentions reducing DMA transfer length by one element in master
|
|
|
|
|
* normal mode.
|
|
|
|
|
*/
|
2013-06-17 21:31:06 +08:00
|
|
|
|
if (mcspi->fifo_depth == 0)
|
2016-07-08 01:17:50 +08:00
|
|
|
|
transfer_reduction = es;
|
2013-06-17 21:31:06 +08:00
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
word_len = cs->word_len;
|
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2012-04-23 20:51:48 +08:00
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
if (word_len <= 8)
|
|
|
|
|
element_count = count;
|
|
|
|
|
else if (word_len <= 16)
|
|
|
|
|
element_count = count >> 1;
|
|
|
|
|
else /* word_len <= 32 */
|
|
|
|
|
element_count = count >> 2;
|
|
|
|
|
|
|
|
|
|
if (mcspi_dma->dma_rx) {
|
2012-04-23 20:51:48 +08:00
|
|
|
|
struct dma_async_tx_descriptor *tx;
|
|
|
|
|
|
|
|
|
|
dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
|
|
|
|
|
|
2016-06-27 22:54:08 +08:00
|
|
|
|
/*
|
|
|
|
|
* Reduce DMA transfer length by one more if McSPI is
|
|
|
|
|
* configured in turbo mode.
|
|
|
|
|
*/
|
2013-06-17 21:31:06 +08:00
|
|
|
|
if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
|
2016-07-08 01:17:50 +08:00
|
|
|
|
transfer_reduction += es;
|
|
|
|
|
|
|
|
|
|
if (transfer_reduction) {
|
|
|
|
|
/* Split sgl into two. The second sgl won't be used. */
|
|
|
|
|
sizes[0] = count - transfer_reduction;
|
|
|
|
|
sizes[1] = transfer_reduction;
|
|
|
|
|
nb_sizes = 2;
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* Don't bother splitting the sgl. This essentially
|
|
|
|
|
* clones the original sgl.
|
|
|
|
|
*/
|
|
|
|
|
sizes[0] = count;
|
|
|
|
|
nb_sizes = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
|
|
|
|
|
0, nb_sizes,
|
|
|
|
|
sizes,
|
|
|
|
|
sg_out, out_mapped_nents,
|
|
|
|
|
GFP_KERNEL);
|
2012-04-23 20:51:48 +08:00
|
|
|
|
|
2016-07-08 01:17:50 +08:00
|
|
|
|
if (ret < 0) {
|
|
|
|
|
dev_err(&spi->dev, "sg_split failed\n");
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2012-04-23 20:51:48 +08:00
|
|
|
|
|
2016-07-08 01:17:50 +08:00
|
|
|
|
tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
|
|
|
|
|
sg_out[0],
|
|
|
|
|
out_mapped_nents[0],
|
|
|
|
|
DMA_DEV_TO_MEM,
|
|
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
2012-04-23 20:51:48 +08:00
|
|
|
|
if (tx) {
|
|
|
|
|
tx->callback = omap2_mcspi_rx_callback;
|
|
|
|
|
tx->callback_param = spi;
|
|
|
|
|
dmaengine_submit(tx);
|
|
|
|
|
} else {
|
2012-09-11 14:43:20 +08:00
|
|
|
|
/* FIXME: fall back to PIO? */
|
2010-10-19 22:07:31 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
dma_async_issue_pending(mcspi_dma->dma_rx);
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 1, 1);
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
|
|
|
|
|
if (ret || mcspi->slave_aborted) {
|
|
|
|
|
dmaengine_terminate_sync(mcspi_dma->dma_rx);
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 1, 0);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2016-07-08 01:17:50 +08:00
|
|
|
|
|
|
|
|
|
for (x = 0; x < nb_sizes; x++)
|
|
|
|
|
kfree(sg_out[x]);
|
2013-06-17 21:31:06 +08:00
|
|
|
|
|
|
|
|
|
if (mcspi->fifo_depth > 0)
|
|
|
|
|
return count;
|
|
|
|
|
|
2016-06-27 22:54:08 +08:00
|
|
|
|
/*
|
|
|
|
|
* Due to the DMA transfer length reduction the missing bytes must
|
|
|
|
|
* be read manually to receive all of the expected data.
|
|
|
|
|
*/
|
2012-09-11 14:43:20 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2012-04-23 20:51:48 +08:00
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
elements = element_count - 1;
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
if (l & OMAP2_MCSPI_CHCONF_TURBO) {
|
|
|
|
|
elements--;
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
2017-03-22 08:18:26 +08:00
|
|
|
|
if (!mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS)) {
|
2009-07-30 06:02:12 +08:00
|
|
|
|
u32 w;
|
|
|
|
|
|
|
|
|
|
w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
|
|
|
|
|
if (word_len <= 8)
|
2012-09-11 14:43:20 +08:00
|
|
|
|
((u8 *)xfer->rx_buf)[elements++] = w;
|
2009-07-30 06:02:12 +08:00
|
|
|
|
else if (word_len <= 16)
|
2012-09-11 14:43:20 +08:00
|
|
|
|
((u16 *)xfer->rx_buf)[elements++] = w;
|
2009-07-30 06:02:12 +08:00
|
|
|
|
else /* word_len <= 32 */
|
2012-09-11 14:43:20 +08:00
|
|
|
|
((u32 *)xfer->rx_buf)[elements++] = w;
|
2009-07-30 06:02:12 +08:00
|
|
|
|
} else {
|
2013-06-15 00:12:07 +08:00
|
|
|
|
int bytes_per_word = mcspi_bytes_per_word(word_len);
|
2013-10-11 18:53:59 +08:00
|
|
|
|
dev_err(&spi->dev, "DMA RX penultimate word empty\n");
|
2013-06-15 00:12:07 +08:00
|
|
|
|
count -= (bytes_per_word << 1);
|
2012-09-11 14:43:20 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
|
|
|
|
return count;
|
2009-07-30 06:02:12 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
2017-03-22 08:18:26 +08:00
|
|
|
|
if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
|
2012-09-11 14:43:20 +08:00
|
|
|
|
u32 w;
|
|
|
|
|
|
|
|
|
|
w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
|
|
|
|
|
if (word_len <= 8)
|
|
|
|
|
((u8 *)xfer->rx_buf)[elements] = w;
|
|
|
|
|
else if (word_len <= 16)
|
|
|
|
|
((u16 *)xfer->rx_buf)[elements] = w;
|
|
|
|
|
else /* word_len <= 32 */
|
|
|
|
|
((u32 *)xfer->rx_buf)[elements] = w;
|
|
|
|
|
} else {
|
2013-10-11 18:53:59 +08:00
|
|
|
|
dev_err(&spi->dev, "DMA RX last word empty\n");
|
2013-06-15 00:12:07 +08:00
|
|
|
|
count -= mcspi_bytes_per_word(word_len);
|
2012-09-11 14:43:20 +08:00
|
|
|
|
}
|
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
|
omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
|
unsigned int count;
|
|
|
|
|
u8 *rx;
|
|
|
|
|
const u8 *tx;
|
|
|
|
|
struct dma_slave_config cfg;
|
|
|
|
|
enum dma_slave_buswidth width;
|
|
|
|
|
unsigned es;
|
2012-11-06 17:00:19 +08:00
|
|
|
|
void __iomem *chstat_reg;
|
2013-06-17 21:31:06 +08:00
|
|
|
|
void __iomem *irqstat_reg;
|
|
|
|
|
int wait_res;
|
2012-09-11 14:43:20 +08:00
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
|
|
|
|
if (cs->word_len <= 8) {
|
|
|
|
|
width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
|
|
|
|
es = 1;
|
|
|
|
|
} else if (cs->word_len <= 16) {
|
|
|
|
|
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
|
|
|
es = 2;
|
|
|
|
|
} else {
|
|
|
|
|
width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
|
es = 4;
|
|
|
|
|
}
|
|
|
|
|
|
2013-06-17 21:31:06 +08:00
|
|
|
|
count = xfer->len;
|
|
|
|
|
|
2012-09-11 14:43:20 +08:00
|
|
|
|
memset(&cfg, 0, sizeof(cfg));
|
|
|
|
|
cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
|
|
|
|
|
cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
|
|
|
|
|
cfg.src_addr_width = width;
|
|
|
|
|
cfg.dst_addr_width = width;
|
2018-10-15 14:38:28 +08:00
|
|
|
|
cfg.src_maxburst = es;
|
|
|
|
|
cfg.dst_maxburst = es;
|
2012-09-11 14:43:20 +08:00
|
|
|
|
|
|
|
|
|
rx = xfer->rx_buf;
|
|
|
|
|
tx = xfer->tx_buf;
|
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
mcspi->slave_aborted = false;
|
|
|
|
|
reinit_completion(&mcspi_dma->dma_tx_completion);
|
|
|
|
|
reinit_completion(&mcspi_dma->dma_rx_completion);
|
|
|
|
|
reinit_completion(&mcspi->txdone);
|
|
|
|
|
if (tx) {
|
|
|
|
|
/* Enable EOW IRQ to know end of tx in slave mode */
|
|
|
|
|
if (spi_controller_is_slave(spi->master))
|
|
|
|
|
mcspi_write_reg(spi->master,
|
|
|
|
|
OMAP2_MCSPI_IRQENABLE,
|
|
|
|
|
OMAP2_MCSPI_IRQSTATUS_EOW);
|
2012-09-11 14:43:20 +08:00
|
|
|
|
omap2_mcspi_tx_dma(spi, xfer, cfg);
|
2018-10-15 14:38:29 +08:00
|
|
|
|
}
|
2012-09-11 14:43:20 +08:00
|
|
|
|
|
|
|
|
|
if (rx != NULL)
|
2012-11-06 17:00:19 +08:00
|
|
|
|
count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
|
|
|
|
|
|
|
|
|
|
if (tx != NULL) {
|
2018-10-15 14:38:29 +08:00
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
|
|
|
|
|
if (ret || mcspi->slave_aborted) {
|
|
|
|
|
dmaengine_terminate_sync(mcspi_dma->dma_tx);
|
|
|
|
|
omap2_mcspi_set_dma_req(spi, 0, 0);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (spi_controller_is_slave(mcspi->master)) {
|
|
|
|
|
ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
|
|
|
|
|
if (ret || mcspi->slave_aborted)
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2012-11-06 17:00:19 +08:00
|
|
|
|
|
2013-06-17 21:31:06 +08:00
|
|
|
|
if (mcspi->fifo_depth > 0) {
|
|
|
|
|
irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
|
|
|
|
|
|
|
|
|
|
if (mcspi_wait_for_reg_bit(irqstat_reg,
|
|
|
|
|
OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
|
|
|
|
|
dev_err(&spi->dev, "EOW timed out\n");
|
|
|
|
|
|
|
|
|
|
mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
|
|
|
|
|
OMAP2_MCSPI_IRQSTATUS_EOW);
|
|
|
|
|
}
|
|
|
|
|
|
2012-11-06 17:00:19 +08:00
|
|
|
|
/* for TX_ONLY mode, be sure all words have shifted out */
|
|
|
|
|
if (rx == NULL) {
|
2013-06-17 21:31:06 +08:00
|
|
|
|
chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
|
|
|
|
|
if (mcspi->fifo_depth > 0) {
|
|
|
|
|
wait_res = mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXFFE);
|
|
|
|
|
if (wait_res < 0)
|
|
|
|
|
dev_err(&spi->dev, "TXFFE timed out\n");
|
|
|
|
|
} else {
|
|
|
|
|
wait_res = mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS);
|
|
|
|
|
if (wait_res < 0)
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
}
|
|
|
|
|
if (wait_res >= 0 &&
|
|
|
|
|
(mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_EOT) < 0))
|
2012-11-06 17:00:19 +08:00
|
|
|
|
dev_err(&spi->dev, "EOT timed out\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned
|
|
|
|
|
omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
unsigned int count, c;
|
|
|
|
|
u32 l;
|
|
|
|
|
void __iomem *base = cs->base;
|
|
|
|
|
void __iomem *tx_reg;
|
|
|
|
|
void __iomem *rx_reg;
|
|
|
|
|
void __iomem *chstat_reg;
|
|
|
|
|
int word_len;
|
|
|
|
|
|
|
|
|
|
count = xfer->len;
|
|
|
|
|
c = count;
|
|
|
|
|
word_len = cs->word_len;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
/* We store the pre-calculated register addresses on stack to speed
|
|
|
|
|
* up the transfer loop. */
|
|
|
|
|
tx_reg = base + OMAP2_MCSPI_TX0;
|
|
|
|
|
rx_reg = base + OMAP2_MCSPI_RX0;
|
|
|
|
|
chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
|
|
|
|
|
|
2011-02-25 23:55:11 +08:00
|
|
|
|
if (c < (word_len>>3))
|
|
|
|
|
return 0;
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (word_len <= 8) {
|
|
|
|
|
u8 *rx;
|
|
|
|
|
const u8 *tx;
|
|
|
|
|
|
|
|
|
|
rx = xfer->rx_buf;
|
|
|
|
|
tx = xfer->tx_buf;
|
|
|
|
|
|
|
|
|
|
do {
|
2008-01-25 06:00:40 +08:00
|
|
|
|
c -= 1;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "write-%d %02x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *tx);
|
2013-11-16 08:01:16 +08:00
|
|
|
|
writel_relaxed(*tx++, tx_reg);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
if (rx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
|
|
|
|
if (c == 1 && tx == NULL &&
|
|
|
|
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2013-11-16 08:01:16 +08:00
|
|
|
|
*rx++ = readl_relaxed(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %02x\n",
|
2010-04-13 18:41:51 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
|
"RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
c = 0;
|
|
|
|
|
} else if (c == 0 && tx == NULL) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2013-11-16 08:01:16 +08:00
|
|
|
|
*rx++ = readl_relaxed(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %02x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
}
|
2011-03-21 22:27:30 +08:00
|
|
|
|
} while (c);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
} else if (word_len <= 16) {
|
|
|
|
|
u16 *rx;
|
|
|
|
|
const u16 *tx;
|
|
|
|
|
|
|
|
|
|
rx = xfer->rx_buf;
|
|
|
|
|
tx = xfer->tx_buf;
|
|
|
|
|
do {
|
2008-01-25 06:00:40 +08:00
|
|
|
|
c -= 2;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "write-%d %04x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *tx);
|
2013-11-16 08:01:16 +08:00
|
|
|
|
writel_relaxed(*tx++, tx_reg);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
if (rx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
|
|
|
|
if (c == 2 && tx == NULL &&
|
|
|
|
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2013-11-16 08:01:16 +08:00
|
|
|
|
*rx++ = readl_relaxed(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %04x\n",
|
2010-04-13 18:41:51 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
|
"RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
c = 0;
|
|
|
|
|
} else if (c == 0 && tx == NULL) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2013-11-16 08:01:16 +08:00
|
|
|
|
*rx++ = readl_relaxed(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %04x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
}
|
2011-03-21 22:27:30 +08:00
|
|
|
|
} while (c >= 2);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
} else if (word_len <= 32) {
|
|
|
|
|
u32 *rx;
|
|
|
|
|
const u32 *tx;
|
|
|
|
|
|
|
|
|
|
rx = xfer->rx_buf;
|
|
|
|
|
tx = xfer->tx_buf;
|
|
|
|
|
do {
|
2008-01-25 06:00:40 +08:00
|
|
|
|
c -= 4;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (tx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "write-%d %08x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *tx);
|
2013-11-16 08:01:16 +08:00
|
|
|
|
writel_relaxed(*tx++, tx_reg);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
if (rx != NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
|
|
|
|
if (c == 4 && tx == NULL &&
|
|
|
|
|
(l & OMAP2_MCSPI_CHCONF_TURBO)) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2013-11-16 08:01:16 +08:00
|
|
|
|
*rx++ = readl_relaxed(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %08x\n",
|
2010-04-13 18:41:51 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_RXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev,
|
|
|
|
|
"RXS timed out\n");
|
|
|
|
|
goto out;
|
|
|
|
|
}
|
|
|
|
|
c = 0;
|
|
|
|
|
} else if (c == 0 && tx == NULL) {
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2013-11-16 08:01:16 +08:00
|
|
|
|
*rx++ = readl_relaxed(rx_reg);
|
2010-09-29 16:31:29 +08:00
|
|
|
|
dev_vdbg(&spi->dev, "read-%d %08x\n",
|
2007-07-17 19:04:13 +08:00
|
|
|
|
word_len, *(rx - 1));
|
|
|
|
|
}
|
2011-03-21 22:27:30 +08:00
|
|
|
|
} while (c >= 4);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* for TX_ONLY mode, be sure all words have shifted out */
|
|
|
|
|
if (xfer->rx_buf == NULL) {
|
|
|
|
|
if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_TXS) < 0) {
|
|
|
|
|
dev_err(&spi->dev, "TXS timed out\n");
|
|
|
|
|
} else if (mcspi_wait_for_reg_bit(chstat_reg,
|
|
|
|
|
OMAP2_MCSPI_CHSTAT_EOT) < 0)
|
|
|
|
|
dev_err(&spi->dev, "EOT timed out\n");
|
2010-10-19 18:03:27 +08:00
|
|
|
|
|
|
|
|
|
/* disable chan to purge rx datas received in TX_ONLY transfer,
|
|
|
|
|
* otherwise these rx datas will affect the direct following
|
|
|
|
|
* RX_ONLY transfer.
|
|
|
|
|
*/
|
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
out:
|
2010-04-13 18:41:51 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
return count - c;
|
|
|
|
|
}
|
|
|
|
|
|
2011-02-25 03:31:33 +08:00
|
|
|
|
static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
|
|
|
|
|
{
|
|
|
|
|
u32 div;
|
|
|
|
|
|
|
|
|
|
for (div = 0; div < 15; div++)
|
|
|
|
|
if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
|
|
|
|
|
return div;
|
|
|
|
|
|
|
|
|
|
return 15;
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
/* called only when no transfer is active to this device */
|
|
|
|
|
static int omap2_mcspi_setup_transfer(struct spi_device *spi,
|
|
|
|
|
struct spi_transfer *t)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
2014-02-02 23:24:25 +08:00
|
|
|
|
u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
u8 word_len = spi->bits_per_word;
|
2010-03-11 05:23:13 +08:00
|
|
|
|
u32 speed_hz = spi->max_speed_hz;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
|
|
|
|
|
if (t != NULL && t->bits_per_word)
|
|
|
|
|
word_len = t->bits_per_word;
|
|
|
|
|
|
|
|
|
|
cs->word_len = word_len;
|
|
|
|
|
|
2010-03-11 05:23:13 +08:00
|
|
|
|
if (t && t->speed_hz)
|
|
|
|
|
speed_hz = t->speed_hz;
|
|
|
|
|
|
2011-02-25 03:31:33 +08:00
|
|
|
|
speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
|
2014-02-02 23:24:25 +08:00
|
|
|
|
if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
|
|
|
|
|
clkd = omap2_mcspi_calc_divisor(speed_hz);
|
|
|
|
|
speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
|
|
|
|
|
clkg = 0;
|
|
|
|
|
} else {
|
|
|
|
|
div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
|
|
|
|
|
speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
|
|
|
|
|
clkd = (div - 1) & 0xf;
|
|
|
|
|
extclk = (div - 1) >> 4;
|
|
|
|
|
clkg = OMAP2_MCSPI_CHCONF_CLKG;
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
l = mcspi_cached_chconf0(spi);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
|
|
|
|
|
* REVISIT: this controller could support SPI_3WIRE mode.
|
|
|
|
|
*/
|
2012-11-14 11:14:26 +08:00
|
|
|
|
if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
|
2012-10-08 00:19:44 +08:00
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_IS;
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_DPE1;
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_DPE0;
|
|
|
|
|
} else {
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_IS;
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_DPE1;
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_DPE0;
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
/* wordlength */
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
|
|
|
|
|
l |= (word_len - 1) << 7;
|
|
|
|
|
|
|
|
|
|
/* set chipselect polarity; manage with FORCE */
|
|
|
|
|
if (!(spi->mode & SPI_CS_HIGH))
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
|
|
|
|
|
else
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_EPOL;
|
|
|
|
|
|
|
|
|
|
/* set clock divisor */
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
|
2014-02-02 23:24:25 +08:00
|
|
|
|
l |= clkd << 2;
|
|
|
|
|
|
|
|
|
|
/* set clock granularity */
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_CLKG;
|
|
|
|
|
l |= clkg;
|
|
|
|
|
if (clkg) {
|
|
|
|
|
cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
|
|
|
|
|
cs->chctrl0 |= extclk << 8;
|
|
|
|
|
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
/* set SPI mode 0..3 */
|
|
|
|
|
if (spi->mode & SPI_CPOL)
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_POL;
|
|
|
|
|
else
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_POL;
|
|
|
|
|
if (spi->mode & SPI_CPHA)
|
|
|
|
|
l |= OMAP2_MCSPI_CHCONF_PHA;
|
|
|
|
|
else
|
|
|
|
|
l &= ~OMAP2_MCSPI_CHCONF_PHA;
|
|
|
|
|
|
2009-09-23 07:46:16 +08:00
|
|
|
|
mcspi_write_chconf0(spi, l);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2014-07-02 11:28:32 +08:00
|
|
|
|
cs->mode = spi->mode;
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
|
2014-02-02 23:24:25 +08:00
|
|
|
|
speed_hz,
|
2007-07-17 19:04:13 +08:00
|
|
|
|
(spi->mode & SPI_CPHA) ? "trailing" : "leading",
|
|
|
|
|
(spi->mode & SPI_CPOL) ? "inverted" : "normal");
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-04-13 08:25:07 +08:00
|
|
|
|
/*
|
|
|
|
|
* Note that we currently allow DMA only if we get a channel
|
|
|
|
|
* for both rx and tx. Otherwise we'll do PIO for both rx and tx.
|
|
|
|
|
*/
|
2007-07-17 19:04:13 +08:00
|
|
|
|
static int omap2_mcspi_request_dma(struct spi_device *spi)
|
|
|
|
|
{
|
|
|
|
|
struct spi_master *master = spi->master;
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
2016-04-29 21:11:56 +08:00
|
|
|
|
int ret = 0;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
|
|
mcspi_dma = mcspi->dma_channels + spi->chip_select;
|
|
|
|
|
|
2012-04-23 20:51:48 +08:00
|
|
|
|
init_completion(&mcspi_dma->dma_rx_completion);
|
|
|
|
|
init_completion(&mcspi_dma->dma_tx_completion);
|
|
|
|
|
|
2016-04-29 21:11:56 +08:00
|
|
|
|
mcspi_dma->dma_rx = dma_request_chan(&master->dev,
|
|
|
|
|
mcspi_dma->dma_rx_ch_name);
|
|
|
|
|
if (IS_ERR(mcspi_dma->dma_rx)) {
|
|
|
|
|
ret = PTR_ERR(mcspi_dma->dma_rx);
|
|
|
|
|
mcspi_dma->dma_rx = NULL;
|
2013-04-13 08:25:07 +08:00
|
|
|
|
goto no_dma;
|
2016-04-29 21:11:56 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2016-04-29 21:11:56 +08:00
|
|
|
|
mcspi_dma->dma_tx = dma_request_chan(&master->dev,
|
|
|
|
|
mcspi_dma->dma_tx_ch_name);
|
|
|
|
|
if (IS_ERR(mcspi_dma->dma_tx)) {
|
|
|
|
|
ret = PTR_ERR(mcspi_dma->dma_tx);
|
|
|
|
|
mcspi_dma->dma_tx = NULL;
|
2012-04-23 20:51:48 +08:00
|
|
|
|
dma_release_channel(mcspi_dma->dma_rx);
|
|
|
|
|
mcspi_dma->dma_rx = NULL;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2013-04-13 08:25:07 +08:00
|
|
|
|
no_dma:
|
2016-04-29 21:11:56 +08:00
|
|
|
|
return ret;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int omap2_mcspi_setup(struct spi_device *spi)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
2012-03-26 18:02:33 +08:00
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
|
|
|
|
struct omap2_mcspi_cs *cs = spi->controller_state;
|
|
|
|
|
|
|
|
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
|
|
|
|
if (!cs) {
|
2012-06-18 18:27:04 +08:00
|
|
|
|
cs = kzalloc(sizeof *cs, GFP_KERNEL);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (!cs)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
cs->base = mcspi->base + spi->chip_select * 0x14;
|
2008-09-02 04:51:50 +08:00
|
|
|
|
cs->phys = mcspi->phys + spi->chip_select * 0x14;
|
2014-07-02 11:28:32 +08:00
|
|
|
|
cs->mode = 0;
|
2009-09-23 07:46:16 +08:00
|
|
|
|
cs->chconf0 = 0;
|
2014-02-02 23:24:25 +08:00
|
|
|
|
cs->chctrl0 = 0;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
spi->controller_state = cs;
|
2009-09-23 07:46:17 +08:00
|
|
|
|
/* Link this to context save list */
|
2012-03-26 18:02:33 +08:00
|
|
|
|
list_add_tail(&cs->node, &ctx->cs);
|
2015-11-30 23:02:39 +08:00
|
|
|
|
|
|
|
|
|
if (gpio_is_valid(spi->cs_gpio)) {
|
|
|
|
|
ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(&spi->dev, "failed to request gpio\n");
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
gpio_direction_output(spi->cs_gpio,
|
|
|
|
|
!(spi->mode & SPI_CS_HIGH));
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2012-04-23 20:56:25 +08:00
|
|
|
|
if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
|
2007-07-17 19:04:13 +08:00
|
|
|
|
ret = omap2_mcspi_request_dma(spi);
|
2016-04-29 21:11:56 +08:00
|
|
|
|
if (ret)
|
|
|
|
|
dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
|
|
|
|
|
ret);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2012-08-22 14:05:12 +08:00
|
|
|
|
ret = pm_runtime_get_sync(mcspi->dev);
|
2018-04-27 23:50:07 +08:00
|
|
|
|
if (ret < 0) {
|
|
|
|
|
pm_runtime_put_noidle(mcspi->dev);
|
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
return ret;
|
2018-04-27 23:50:07 +08:00
|
|
|
|
}
|
2009-09-23 07:46:16 +08:00
|
|
|
|
|
2007-10-16 16:27:45 +08:00
|
|
|
|
ret = omap2_mcspi_setup_transfer(spi, NULL);
|
2012-08-22 14:05:12 +08:00
|
|
|
|
pm_runtime_mark_last_busy(mcspi->dev);
|
|
|
|
|
pm_runtime_put_autosuspend(mcspi->dev);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap2_mcspi_cleanup(struct spi_device *spi)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
2009-09-23 07:46:17 +08:00
|
|
|
|
struct omap2_mcspi_cs *cs;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
|
2010-03-11 05:22:45 +08:00
|
|
|
|
if (spi->controller_state) {
|
|
|
|
|
/* Unlink controller state from context save list */
|
|
|
|
|
cs = spi->controller_state;
|
|
|
|
|
list_del(&cs->node);
|
2009-09-23 07:46:17 +08:00
|
|
|
|
|
2012-06-18 18:27:04 +08:00
|
|
|
|
kfree(cs);
|
2010-03-11 05:22:45 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2010-05-24 22:20:27 +08:00
|
|
|
|
if (spi->chip_select < spi->master->num_chipselect) {
|
|
|
|
|
mcspi_dma = &mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
2012-04-23 20:51:48 +08:00
|
|
|
|
if (mcspi_dma->dma_rx) {
|
|
|
|
|
dma_release_channel(mcspi_dma->dma_rx);
|
|
|
|
|
mcspi_dma->dma_rx = NULL;
|
2010-05-24 22:20:27 +08:00
|
|
|
|
}
|
2012-04-23 20:51:48 +08:00
|
|
|
|
if (mcspi_dma->dma_tx) {
|
|
|
|
|
dma_release_channel(mcspi_dma->dma_tx);
|
|
|
|
|
mcspi_dma->dma_tx = NULL;
|
2010-05-24 22:20:27 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
2015-05-09 02:31:01 +08:00
|
|
|
|
|
|
|
|
|
if (gpio_is_valid(spi->cs_gpio))
|
|
|
|
|
gpio_free(spi->cs_gpio);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
static irqreturn_t omap2_mcspi_irq_handler(int irq, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi = data;
|
|
|
|
|
u32 irqstat;
|
|
|
|
|
|
|
|
|
|
irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS);
|
|
|
|
|
if (!irqstat)
|
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
|
|
/* Disable IRQ and wakeup slave xfer task */
|
|
|
|
|
mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0);
|
|
|
|
|
if (irqstat & OMAP2_MCSPI_IRQSTATUS_EOW)
|
|
|
|
|
complete(&mcspi->txdone);
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int omap2_mcspi_slave_abort(struct spi_master *master)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
|
|
|
|
|
|
|
|
|
|
mcspi->slave_aborted = true;
|
|
|
|
|
complete(&mcspi_dma->dma_rx_completion);
|
|
|
|
|
complete(&mcspi_dma->dma_tx_completion);
|
|
|
|
|
complete(&mcspi->txdone);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-08 01:17:50 +08:00
|
|
|
|
static int omap2_mcspi_transfer_one(struct spi_master *master,
|
|
|
|
|
struct spi_device *spi,
|
|
|
|
|
struct spi_transfer *t)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
/* We only enable one channel at a time -- the one whose message is
|
2012-05-10 20:57:45 +08:00
|
|
|
|
* -- although this controller would gladly
|
2007-07-17 19:04:13 +08:00
|
|
|
|
* arbitrate among multiple channels. This corresponds to "single
|
|
|
|
|
* channel" master mode. As a side effect, we need to manage the
|
|
|
|
|
* chipselect with the FORCE bit ... CS != channel enable.
|
|
|
|
|
*/
|
|
|
|
|
|
2016-07-08 01:17:50 +08:00
|
|
|
|
struct omap2_mcspi *mcspi;
|
2013-04-13 08:25:07 +08:00
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma;
|
2012-05-10 20:57:45 +08:00
|
|
|
|
struct omap2_mcspi_cs *cs;
|
|
|
|
|
struct omap2_mcspi_device_config *cd;
|
|
|
|
|
int par_override = 0;
|
|
|
|
|
int status = 0;
|
|
|
|
|
u32 chconf;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2016-07-08 01:17:50 +08:00
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
2013-04-13 08:25:07 +08:00
|
|
|
|
mcspi_dma = mcspi->dma_channels + spi->chip_select;
|
2012-05-10 20:57:45 +08:00
|
|
|
|
cs = spi->controller_state;
|
|
|
|
|
cd = spi->controller_data;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2014-07-02 11:28:32 +08:00
|
|
|
|
/*
|
|
|
|
|
* The slave driver could have changed spi->mode in which case
|
|
|
|
|
* it will be different from cs->mode (the current hardware setup).
|
|
|
|
|
* If so, set par_override (even though its not a parity issue) so
|
|
|
|
|
* omap2_mcspi_setup_transfer will be called to configure the hardware
|
|
|
|
|
* with the correct mode on the first iteration of the loop below.
|
|
|
|
|
*/
|
|
|
|
|
if (spi->mode != cs->mode)
|
|
|
|
|
par_override = 1;
|
|
|
|
|
|
2013-06-17 21:31:06 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
2015-05-24 10:13:44 +08:00
|
|
|
|
if (gpio_is_valid(spi->cs_gpio))
|
|
|
|
|
omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
|
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
if (par_override ||
|
|
|
|
|
(t->speed_hz != spi->max_speed_hz) ||
|
|
|
|
|
(t->bits_per_word != spi->bits_per_word)) {
|
|
|
|
|
par_override = 1;
|
|
|
|
|
status = omap2_mcspi_setup_transfer(spi, t);
|
|
|
|
|
if (status < 0)
|
|
|
|
|
goto out;
|
|
|
|
|
if (t->speed_hz == spi->max_speed_hz &&
|
|
|
|
|
t->bits_per_word == spi->bits_per_word)
|
|
|
|
|
par_override = 0;
|
|
|
|
|
}
|
|
|
|
|
if (cd && cd->cs_per_word) {
|
|
|
|
|
chconf = mcspi->ctx.modulctrl;
|
|
|
|
|
chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
|
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
|
|
|
|
|
mcspi->ctx.modulctrl =
|
|
|
|
|
mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
|
|
|
|
|
}
|
2010-04-13 18:41:51 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
chconf = mcspi_cached_chconf0(spi);
|
|
|
|
|
chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
|
|
|
|
|
chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
|
|
|
|
|
|
|
|
|
|
if (t->tx_buf == NULL)
|
|
|
|
|
chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
|
|
|
|
|
else if (t->rx_buf == NULL)
|
|
|
|
|
chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
|
|
|
|
|
|
|
|
|
|
if (cd && cd->turbo_mode && t->tx_buf == NULL) {
|
|
|
|
|
/* Turbo mode is for more than one word */
|
|
|
|
|
if (t->len > ((cs->word_len + 7) >> 3))
|
|
|
|
|
chconf |= OMAP2_MCSPI_CHCONF_TURBO;
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
mcspi_write_chconf0(spi, chconf);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
if (t->len) {
|
|
|
|
|
unsigned count;
|
2012-05-10 20:57:45 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
|
2016-07-08 01:17:50 +08:00
|
|
|
|
master->cur_msg_mapped &&
|
|
|
|
|
master->can_dma(master, spi, t))
|
2015-05-08 07:36:53 +08:00
|
|
|
|
omap2_mcspi_set_fifo(spi, t, 1);
|
2013-06-17 21:31:06 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 1);
|
2013-06-17 21:31:06 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
/* RX_ONLY mode needs dummy data in TX reg */
|
|
|
|
|
if (t->tx_buf == NULL)
|
|
|
|
|
writel_relaxed(0, cs->base
|
|
|
|
|
+ OMAP2_MCSPI_TX0);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
|
2016-07-08 01:17:50 +08:00
|
|
|
|
master->cur_msg_mapped &&
|
|
|
|
|
master->can_dma(master, spi, t))
|
2015-05-08 07:36:53 +08:00
|
|
|
|
count = omap2_mcspi_txrx_dma(spi, t);
|
|
|
|
|
else
|
|
|
|
|
count = omap2_mcspi_txrx_pio(spi, t);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
if (count != t->len) {
|
|
|
|
|
status = -EIO;
|
|
|
|
|
goto out;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
2015-05-08 07:36:53 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2013-06-17 21:31:06 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
if (mcspi->fifo_depth > 0)
|
|
|
|
|
omap2_mcspi_set_fifo(spi, t, 0);
|
|
|
|
|
|
|
|
|
|
out:
|
2012-05-10 20:57:45 +08:00
|
|
|
|
/* Restore defaults if they were overriden */
|
|
|
|
|
if (par_override) {
|
|
|
|
|
par_override = 0;
|
|
|
|
|
status = omap2_mcspi_setup_transfer(spi, NULL);
|
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2013-01-24 20:40:41 +08:00
|
|
|
|
if (cd && cd->cs_per_word) {
|
|
|
|
|
chconf = mcspi->ctx.modulctrl;
|
|
|
|
|
chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
|
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
|
|
|
|
|
mcspi->ctx.modulctrl =
|
|
|
|
|
mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
|
|
|
|
|
}
|
|
|
|
|
|
2012-05-10 20:57:45 +08:00
|
|
|
|
omap2_mcspi_set_enable(spi, 0);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2015-05-24 10:13:44 +08:00
|
|
|
|
if (gpio_is_valid(spi->cs_gpio))
|
|
|
|
|
omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
|
|
|
|
|
|
2013-06-17 21:31:06 +08:00
|
|
|
|
if (mcspi->fifo_depth > 0 && t)
|
|
|
|
|
omap2_mcspi_set_fifo(spi, t, 0);
|
2011-02-02 20:22:15 +08:00
|
|
|
|
|
2015-05-08 07:36:53 +08:00
|
|
|
|
return status;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2015-10-09 21:47:41 +08:00
|
|
|
|
static int omap2_mcspi_prepare_message(struct spi_master *master,
|
|
|
|
|
struct spi_message *msg)
|
|
|
|
|
{
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
|
|
|
|
|
struct omap2_mcspi_cs *cs;
|
|
|
|
|
|
|
|
|
|
/* Only a single channel can have the FORCE bit enabled
|
|
|
|
|
* in its chconf0 register.
|
|
|
|
|
* Scan all channels and disable them except the current one.
|
|
|
|
|
* A FORCE can remain from a last transfer having cs_change enabled
|
|
|
|
|
*/
|
|
|
|
|
list_for_each_entry(cs, &ctx->cs, node) {
|
|
|
|
|
if (msg->spi->controller_state == cs)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
|
|
|
|
|
cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
|
|
|
|
|
writel_relaxed(cs->chconf0,
|
|
|
|
|
cs->base + OMAP2_MCSPI_CHCONF0);
|
|
|
|
|
readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-08 01:17:50 +08:00
|
|
|
|
static bool omap2_mcspi_can_dma(struct spi_master *master,
|
|
|
|
|
struct spi_device *spi,
|
|
|
|
|
struct spi_transfer *xfer)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
2018-10-15 14:38:29 +08:00
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
|
|
|
|
|
struct omap2_mcspi_dma *mcspi_dma =
|
|
|
|
|
&mcspi->dma_channels[spi->chip_select];
|
|
|
|
|
|
|
|
|
|
if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
if (spi_controller_is_slave(master))
|
|
|
|
|
return true;
|
|
|
|
|
|
2016-07-08 01:17:50 +08:00
|
|
|
|
return (xfer->len >= DMA_MIN_BYTES);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
|
|
|
|
struct spi_master *master = mcspi->master;
|
2012-03-26 18:02:33 +08:00
|
|
|
|
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
|
|
|
|
|
int ret = 0;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2012-08-22 14:05:12 +08:00
|
|
|
|
ret = pm_runtime_get_sync(mcspi->dev);
|
2018-04-27 23:50:07 +08:00
|
|
|
|
if (ret < 0) {
|
|
|
|
|
pm_runtime_put_noidle(mcspi->dev);
|
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
return ret;
|
2018-04-27 23:50:07 +08:00
|
|
|
|
}
|
2009-07-30 06:02:11 +08:00
|
|
|
|
|
2012-03-30 00:41:07 +08:00
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
|
2013-01-24 20:28:58 +08:00
|
|
|
|
OMAP2_MCSPI_WAKEUPENABLE_WKEN);
|
2012-03-30 00:41:07 +08:00
|
|
|
|
ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
omap2_mcspi_set_mode(master);
|
2012-08-22 14:05:12 +08:00
|
|
|
|
pm_runtime_mark_last_busy(mcspi->dev);
|
|
|
|
|
pm_runtime_put_autosuspend(mcspi->dev);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-25 22:08:43 +08:00
|
|
|
|
/*
|
|
|
|
|
* When SPI wake up from off-mode, CS is in activate state. If it was in
|
|
|
|
|
* inactive state when driver was suspend, then force it to inactive state at
|
|
|
|
|
* wake up.
|
|
|
|
|
*/
|
2011-02-02 20:22:15 +08:00
|
|
|
|
static int omap_mcspi_runtime_resume(struct device *dev)
|
|
|
|
|
{
|
2018-04-25 22:08:43 +08:00
|
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
struct omap2_mcspi_regs *ctx = &mcspi->ctx;
|
|
|
|
|
struct omap2_mcspi_cs *cs;
|
2011-02-02 20:22:15 +08:00
|
|
|
|
|
2018-04-25 22:08:43 +08:00
|
|
|
|
/* McSPI: context restore */
|
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
|
|
|
|
|
mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
|
|
|
|
|
|
|
|
|
|
list_for_each_entry(cs, &ctx->cs, node) {
|
|
|
|
|
/*
|
|
|
|
|
* We need to toggle CS state for OMAP take this
|
|
|
|
|
* change in account.
|
|
|
|
|
*/
|
|
|
|
|
if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
|
|
|
|
|
cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
|
|
|
|
|
writel_relaxed(cs->chconf0,
|
|
|
|
|
cs->base + OMAP2_MCSPI_CHCONF0);
|
|
|
|
|
cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
|
|
|
|
|
writel_relaxed(cs->chconf0,
|
|
|
|
|
cs->base + OMAP2_MCSPI_CHCONF0);
|
|
|
|
|
} else {
|
|
|
|
|
writel_relaxed(cs->chconf0,
|
|
|
|
|
cs->base + OMAP2_MCSPI_CHCONF0);
|
|
|
|
|
}
|
|
|
|
|
}
|
2011-02-02 20:22:15 +08:00
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-02-16 01:37:34 +08:00
|
|
|
|
static struct omap2_mcspi_platform_config omap2_pdata = {
|
|
|
|
|
.regs_offset = 0,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct omap2_mcspi_platform_config omap4_pdata = {
|
|
|
|
|
.regs_offset = OMAP4_MCSPI_REG_OFFSET,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct of_device_id omap_mcspi_of_match[] = {
|
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,omap2-mcspi",
|
|
|
|
|
.data = &omap2_pdata,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,omap4-mcspi",
|
|
|
|
|
.data = &omap4_pdata,
|
|
|
|
|
},
|
|
|
|
|
{ },
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
|
2008-02-06 17:38:16 +08:00
|
|
|
|
|
2012-12-08 00:57:14 +08:00
|
|
|
|
static int omap2_mcspi_probe(struct platform_device *pdev)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
|
|
|
|
struct spi_master *master;
|
2012-05-22 03:57:39 +08:00
|
|
|
|
const struct omap2_mcspi_platform_config *pdata;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
struct omap2_mcspi *mcspi;
|
|
|
|
|
struct resource *r;
|
|
|
|
|
int status = 0, i;
|
2012-02-16 01:37:34 +08:00
|
|
|
|
u32 regs_offset = 0;
|
|
|
|
|
struct device_node *node = pdev->dev.of_node;
|
|
|
|
|
const struct of_device_id *match;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
if (of_property_read_bool(node, "spi-slave"))
|
|
|
|
|
master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi));
|
|
|
|
|
else
|
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*mcspi));
|
|
|
|
|
if (!master)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2009-06-18 07:26:04 +08:00
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
2013-05-22 10:36:35 +08:00
|
|
|
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
master->setup = omap2_mcspi_setup;
|
2013-07-28 22:34:37 +08:00
|
|
|
|
master->auto_runtime_pm = true;
|
2015-10-09 21:47:41 +08:00
|
|
|
|
master->prepare_message = omap2_mcspi_prepare_message;
|
2016-07-08 01:17:50 +08:00
|
|
|
|
master->can_dma = omap2_mcspi_can_dma;
|
2015-05-08 07:36:53 +08:00
|
|
|
|
master->transfer_one = omap2_mcspi_transfer_one;
|
2015-05-13 01:38:57 +08:00
|
|
|
|
master->set_cs = omap2_mcspi_set_cs;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
master->cleanup = omap2_mcspi_cleanup;
|
2018-10-15 14:38:29 +08:00
|
|
|
|
master->slave_abort = omap2_mcspi_slave_abort;
|
2012-02-16 01:37:34 +08:00
|
|
|
|
master->dev.of_node = node;
|
2014-02-18 22:02:47 +08:00
|
|
|
|
master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
|
|
|
|
|
master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
|
2012-02-16 01:37:34 +08:00
|
|
|
|
|
2013-05-23 18:20:40 +08:00
|
|
|
|
platform_set_drvdata(pdev, master);
|
2012-10-08 00:19:44 +08:00
|
|
|
|
|
|
|
|
|
mcspi = spi_master_get_devdata(master);
|
|
|
|
|
mcspi->master = master;
|
|
|
|
|
|
2012-02-16 01:37:34 +08:00
|
|
|
|
match = of_match_device(omap_mcspi_of_match, &pdev->dev);
|
|
|
|
|
if (match) {
|
|
|
|
|
u32 num_cs = 1; /* default number of chipselect */
|
|
|
|
|
pdata = match->data;
|
|
|
|
|
|
|
|
|
|
of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
|
|
|
|
|
master->num_chipselect = num_cs;
|
2012-11-14 11:14:26 +08:00
|
|
|
|
if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
|
|
|
|
|
mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
|
2012-02-16 01:37:34 +08:00
|
|
|
|
} else {
|
2013-07-30 15:58:59 +08:00
|
|
|
|
pdata = dev_get_platdata(&pdev->dev);
|
2012-02-16 01:37:34 +08:00
|
|
|
|
master->num_chipselect = pdata->num_cs;
|
2012-10-08 00:19:44 +08:00
|
|
|
|
mcspi->pin_dir = pdata->pin_dir;
|
2012-02-16 01:37:34 +08:00
|
|
|
|
}
|
|
|
|
|
regs_offset = pdata->regs_offset;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2013-01-21 18:09:18 +08:00
|
|
|
|
mcspi->base = devm_ioremap_resource(&pdev->dev, r);
|
|
|
|
|
if (IS_ERR(mcspi->base)) {
|
|
|
|
|
status = PTR_ERR(mcspi->base);
|
2012-03-17 15:14:01 +08:00
|
|
|
|
goto free_master;
|
2008-09-04 21:07:22 +08:00
|
|
|
|
}
|
2016-09-30 22:23:11 +08:00
|
|
|
|
mcspi->phys = r->start + regs_offset;
|
|
|
|
|
mcspi->base += regs_offset;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2011-02-02 20:22:15 +08:00
|
|
|
|
mcspi->dev = &pdev->dev;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2012-03-26 18:02:33 +08:00
|
|
|
|
INIT_LIST_HEAD(&mcspi->ctx.cs);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2014-03-29 21:37:44 +08:00
|
|
|
|
mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
|
|
|
|
|
sizeof(struct omap2_mcspi_dma),
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (mcspi->dma_channels == NULL) {
|
|
|
|
|
status = -ENOMEM;
|
2012-03-17 15:14:01 +08:00
|
|
|
|
goto free_master;
|
2014-03-29 21:37:44 +08:00
|
|
|
|
}
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2011-02-02 20:22:14 +08:00
|
|
|
|
for (i = 0; i < master->num_chipselect; i++) {
|
2016-04-29 21:11:56 +08:00
|
|
|
|
sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
|
|
|
|
|
sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
}
|
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
status = platform_get_irq(pdev, 0);
|
|
|
|
|
if (status == -EPROBE_DEFER)
|
|
|
|
|
goto free_master;
|
|
|
|
|
if (status < 0) {
|
|
|
|
|
dev_err(&pdev->dev, "no irq resource found\n");
|
|
|
|
|
goto free_master;
|
|
|
|
|
}
|
|
|
|
|
init_completion(&mcspi->txdone);
|
|
|
|
|
status = devm_request_irq(&pdev->dev, status,
|
|
|
|
|
omap2_mcspi_irq_handler, 0, pdev->name,
|
|
|
|
|
mcspi);
|
|
|
|
|
if (status) {
|
|
|
|
|
dev_err(&pdev->dev, "Cannot request IRQ");
|
|
|
|
|
goto free_master;
|
|
|
|
|
}
|
|
|
|
|
|
2012-03-26 19:34:22 +08:00
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
|
2011-02-02 20:22:15 +08:00
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
status = omap2_mcspi_controller_setup(mcspi);
|
2013-04-18 11:14:59 +08:00
|
|
|
|
if (status < 0)
|
2011-10-28 19:44:19 +08:00
|
|
|
|
goto disable_pm;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2018-10-15 14:38:29 +08:00
|
|
|
|
status = devm_spi_register_controller(&pdev->dev, master);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
if (status < 0)
|
2012-08-02 19:11:25 +08:00
|
|
|
|
goto disable_pm;
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
return status;
|
|
|
|
|
|
2011-10-28 19:44:19 +08:00
|
|
|
|
disable_pm:
|
2016-02-11 07:02:46 +08:00
|
|
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
2011-10-28 19:44:18 +08:00
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2011-10-28 19:44:19 +08:00
|
|
|
|
free_master:
|
2012-08-02 19:11:25 +08:00
|
|
|
|
spi_master_put(master);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
return status;
|
|
|
|
|
}
|
|
|
|
|
|
2012-12-08 00:57:14 +08:00
|
|
|
|
static int omap2_mcspi_remove(struct platform_device *pdev)
|
2007-07-17 19:04:13 +08:00
|
|
|
|
{
|
2014-03-29 21:37:44 +08:00
|
|
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
2016-02-11 07:02:46 +08:00
|
|
|
|
pm_runtime_dont_use_autosuspend(mcspi->dev);
|
2012-08-22 14:05:14 +08:00
|
|
|
|
pm_runtime_put_sync(mcspi->dev);
|
2011-10-28 19:44:18 +08:00
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2008-04-11 12:29:20 +08:00
|
|
|
|
/* work with hotplug and coldplug */
|
|
|
|
|
MODULE_ALIAS("platform:omap2_mcspi");
|
|
|
|
|
|
2018-11-16 07:59:39 +08:00
|
|
|
|
static int __maybe_unused omap2_mcspi_suspend(struct device *dev)
|
2010-12-29 18:52:53 +08:00
|
|
|
|
{
|
2018-11-16 07:59:39 +08:00
|
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
int error;
|
|
|
|
|
|
|
|
|
|
error = pinctrl_pm_select_sleep_state(dev);
|
|
|
|
|
if (error)
|
|
|
|
|
dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
|
|
|
|
|
__func__, error);
|
|
|
|
|
|
|
|
|
|
error = spi_master_suspend(master);
|
|
|
|
|
if (error)
|
|
|
|
|
dev_warn(mcspi->dev, "%s: master suspend failed: %i\n",
|
|
|
|
|
__func__, error);
|
|
|
|
|
|
|
|
|
|
return pm_runtime_force_suspend(dev);
|
2015-11-19 23:18:28 +08:00
|
|
|
|
}
|
|
|
|
|
|
2018-11-16 07:59:39 +08:00
|
|
|
|
static int __maybe_unused omap2_mcspi_resume(struct device *dev)
|
2015-11-19 23:18:28 +08:00
|
|
|
|
{
|
2018-04-27 23:50:07 +08:00
|
|
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
|
struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
|
|
|
|
|
int error;
|
|
|
|
|
|
|
|
|
|
error = pinctrl_pm_select_default_state(dev);
|
|
|
|
|
if (error)
|
|
|
|
|
dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
|
|
|
|
|
__func__, error);
|
|
|
|
|
|
2018-11-16 07:59:39 +08:00
|
|
|
|
error = spi_master_resume(master);
|
|
|
|
|
if (error)
|
|
|
|
|
dev_warn(mcspi->dev, "%s: master resume failed: %i\n",
|
|
|
|
|
__func__, error);
|
2015-11-19 23:18:28 +08:00
|
|
|
|
|
2018-11-16 07:59:39 +08:00
|
|
|
|
return pm_runtime_force_resume(dev);
|
|
|
|
|
}
|
2010-12-29 18:52:53 +08:00
|
|
|
|
|
|
|
|
|
static const struct dev_pm_ops omap2_mcspi_pm_ops = {
|
2018-11-16 07:59:39 +08:00
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(omap2_mcspi_suspend,
|
|
|
|
|
omap2_mcspi_resume)
|
2011-02-02 20:22:15 +08:00
|
|
|
|
.runtime_resume = omap_mcspi_runtime_resume,
|
2010-12-29 18:52:53 +08:00
|
|
|
|
};
|
|
|
|
|
|
2007-07-17 19:04:13 +08:00
|
|
|
|
static struct platform_driver omap2_mcspi_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "omap2_mcspi",
|
2012-02-16 01:37:34 +08:00
|
|
|
|
.pm = &omap2_mcspi_pm_ops,
|
|
|
|
|
.of_match_table = omap_mcspi_of_match,
|
2007-07-17 19:04:13 +08:00
|
|
|
|
},
|
2012-03-14 17:18:30 +08:00
|
|
|
|
.probe = omap2_mcspi_probe,
|
2012-12-08 00:57:14 +08:00
|
|
|
|
.remove = omap2_mcspi_remove,
|
2007-07-17 19:04:13 +08:00
|
|
|
|
};
|
|
|
|
|
|
2012-03-14 17:18:31 +08:00
|
|
|
|
module_platform_driver(omap2_mcspi_driver);
|
2007-07-17 19:04:13 +08:00
|
|
|
|
MODULE_LICENSE("GPL");
|