2019-03-09 20:20:12 +08:00
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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <drm/lima_drm.h>
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#include "lima_device.h"
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#include "lima_pp.h"
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#include "lima_dlbu.h"
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#include "lima_bcast.h"
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#include "lima_vm.h"
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#include "lima_regs.h"
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#define pp_write(reg, data) writel(data, ip->iomem + reg)
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#define pp_read(reg) readl(ip->iomem + reg)
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static void lima_pp_handle_irq(struct lima_ip *ip, u32 state)
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{
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struct lima_device *dev = ip->dev;
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struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
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if (state & LIMA_PP_IRQ_MASK_ERROR) {
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u32 status = pp_read(LIMA_PP_STATUS);
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dev_err(dev->dev, "pp error irq state=%x status=%x\n",
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state, status);
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pipe->error = true;
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/* mask all interrupts before hard reset */
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pp_write(LIMA_PP_INT_MASK, 0);
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}
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pp_write(LIMA_PP_INT_CLEAR, state);
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}
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static irqreturn_t lima_pp_irq_handler(int irq, void *data)
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{
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struct lima_ip *ip = data;
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struct lima_device *dev = ip->dev;
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struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
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u32 state = pp_read(LIMA_PP_INT_STATUS);
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/* for shared irq case */
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if (!state)
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return IRQ_NONE;
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lima_pp_handle_irq(ip, state);
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if (atomic_dec_and_test(&pipe->task))
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lima_sched_pipe_task_done(pipe);
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return IRQ_HANDLED;
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}
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static irqreturn_t lima_pp_bcast_irq_handler(int irq, void *data)
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{
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int i;
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irqreturn_t ret = IRQ_NONE;
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struct lima_ip *pp_bcast = data;
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struct lima_device *dev = pp_bcast->dev;
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struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
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2019-04-19 16:33:01 +08:00
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struct drm_lima_m450_pp_frame *frame;
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/* for shared irq case */
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if (!pipe->current_task)
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return IRQ_NONE;
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frame = pipe->current_task->frame;
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2019-03-09 20:20:12 +08:00
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for (i = 0; i < frame->num_pp; i++) {
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struct lima_ip *ip = pipe->processor[i];
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u32 status, state;
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if (pipe->done & (1 << i))
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continue;
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/* status read first in case int state change in the middle
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* which may miss the interrupt handling
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*/
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status = pp_read(LIMA_PP_STATUS);
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state = pp_read(LIMA_PP_INT_STATUS);
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if (state) {
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lima_pp_handle_irq(ip, state);
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ret = IRQ_HANDLED;
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} else {
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if (status & LIMA_PP_STATUS_RENDERING_ACTIVE)
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continue;
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}
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pipe->done |= (1 << i);
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if (atomic_dec_and_test(&pipe->task))
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lima_sched_pipe_task_done(pipe);
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}
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return ret;
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}
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static void lima_pp_soft_reset_async(struct lima_ip *ip)
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{
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if (ip->data.async_reset)
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return;
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pp_write(LIMA_PP_INT_MASK, 0);
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pp_write(LIMA_PP_INT_RAWSTAT, LIMA_PP_IRQ_MASK_ALL);
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pp_write(LIMA_PP_CTRL, LIMA_PP_CTRL_SOFT_RESET);
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ip->data.async_reset = true;
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}
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static int lima_pp_soft_reset_poll(struct lima_ip *ip)
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{
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return !(pp_read(LIMA_PP_STATUS) & LIMA_PP_STATUS_RENDERING_ACTIVE) &&
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pp_read(LIMA_PP_INT_RAWSTAT) == LIMA_PP_IRQ_RESET_COMPLETED;
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}
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static int lima_pp_soft_reset_async_wait_one(struct lima_ip *ip)
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{
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struct lima_device *dev = ip->dev;
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int ret;
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ret = lima_poll_timeout(ip, lima_pp_soft_reset_poll, 0, 100);
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if (ret) {
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dev_err(dev->dev, "pp %s reset time out\n", lima_ip_name(ip));
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return ret;
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}
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pp_write(LIMA_PP_INT_CLEAR, LIMA_PP_IRQ_MASK_ALL);
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pp_write(LIMA_PP_INT_MASK, LIMA_PP_IRQ_MASK_USED);
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return 0;
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}
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static int lima_pp_soft_reset_async_wait(struct lima_ip *ip)
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{
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int i, err = 0;
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if (!ip->data.async_reset)
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return 0;
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if (ip->id == lima_ip_pp_bcast) {
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struct lima_device *dev = ip->dev;
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struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
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struct drm_lima_m450_pp_frame *frame = pipe->current_task->frame;
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for (i = 0; i < frame->num_pp; i++)
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err |= lima_pp_soft_reset_async_wait_one(pipe->processor[i]);
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} else
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err = lima_pp_soft_reset_async_wait_one(ip);
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ip->data.async_reset = false;
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return err;
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}
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static void lima_pp_write_frame(struct lima_ip *ip, u32 *frame, u32 *wb)
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{
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int i, j, n = 0;
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for (i = 0; i < LIMA_PP_FRAME_REG_NUM; i++)
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writel(frame[i], ip->iomem + LIMA_PP_FRAME + i * 4);
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for (i = 0; i < 3; i++) {
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for (j = 0; j < LIMA_PP_WB_REG_NUM; j++)
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writel(wb[n++], ip->iomem + LIMA_PP_WB(i) + j * 4);
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}
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}
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static int lima_pp_hard_reset_poll(struct lima_ip *ip)
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{
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pp_write(LIMA_PP_PERF_CNT_0_LIMIT, 0xC01A0000);
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return pp_read(LIMA_PP_PERF_CNT_0_LIMIT) == 0xC01A0000;
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}
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static int lima_pp_hard_reset(struct lima_ip *ip)
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{
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struct lima_device *dev = ip->dev;
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int ret;
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pp_write(LIMA_PP_PERF_CNT_0_LIMIT, 0xC0FFE000);
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pp_write(LIMA_PP_INT_MASK, 0);
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pp_write(LIMA_PP_CTRL, LIMA_PP_CTRL_FORCE_RESET);
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ret = lima_poll_timeout(ip, lima_pp_hard_reset_poll, 10, 100);
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if (ret) {
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dev_err(dev->dev, "pp hard reset timeout\n");
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return ret;
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}
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pp_write(LIMA_PP_PERF_CNT_0_LIMIT, 0);
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pp_write(LIMA_PP_INT_CLEAR, LIMA_PP_IRQ_MASK_ALL);
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pp_write(LIMA_PP_INT_MASK, LIMA_PP_IRQ_MASK_USED);
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return 0;
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}
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static void lima_pp_print_version(struct lima_ip *ip)
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{
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u32 version, major, minor;
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char *name;
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version = pp_read(LIMA_PP_VERSION);
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major = (version >> 8) & 0xFF;
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minor = version & 0xFF;
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switch (version >> 16) {
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case 0xC807:
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name = "mali200";
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break;
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case 0xCE07:
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name = "mali300";
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break;
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case 0xCD07:
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name = "mali400";
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break;
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case 0xCF07:
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name = "mali450";
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break;
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default:
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name = "unknown";
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break;
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}
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dev_info(ip->dev->dev, "%s - %s version major %d minor %d\n",
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lima_ip_name(ip), name, major, minor);
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}
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int lima_pp_init(struct lima_ip *ip)
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{
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struct lima_device *dev = ip->dev;
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int err;
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lima_pp_print_version(ip);
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ip->data.async_reset = false;
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lima_pp_soft_reset_async(ip);
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err = lima_pp_soft_reset_async_wait(ip);
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if (err)
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return err;
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err = devm_request_irq(dev->dev, ip->irq, lima_pp_irq_handler,
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IRQF_SHARED, lima_ip_name(ip), ip);
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if (err) {
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dev_err(dev->dev, "pp %s fail to request irq\n",
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lima_ip_name(ip));
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return err;
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}
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dev->pp_version = pp_read(LIMA_PP_VERSION);
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return 0;
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}
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void lima_pp_fini(struct lima_ip *ip)
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{
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}
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int lima_pp_bcast_init(struct lima_ip *ip)
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{
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struct lima_device *dev = ip->dev;
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int err;
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err = devm_request_irq(dev->dev, ip->irq, lima_pp_bcast_irq_handler,
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IRQF_SHARED, lima_ip_name(ip), ip);
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if (err) {
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dev_err(dev->dev, "pp %s fail to request irq\n",
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lima_ip_name(ip));
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return err;
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}
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return 0;
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}
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void lima_pp_bcast_fini(struct lima_ip *ip)
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{
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}
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static int lima_pp_task_validate(struct lima_sched_pipe *pipe,
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struct lima_sched_task *task)
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{
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u32 num_pp;
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if (pipe->bcast_processor) {
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struct drm_lima_m450_pp_frame *f = task->frame;
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num_pp = f->num_pp;
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if (f->_pad)
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return -EINVAL;
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} else {
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struct drm_lima_m400_pp_frame *f = task->frame;
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num_pp = f->num_pp;
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}
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if (num_pp == 0 || num_pp > pipe->num_processor)
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return -EINVAL;
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return 0;
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}
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static void lima_pp_task_run(struct lima_sched_pipe *pipe,
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struct lima_sched_task *task)
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{
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if (pipe->bcast_processor) {
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struct drm_lima_m450_pp_frame *frame = task->frame;
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struct lima_device *dev = pipe->bcast_processor->dev;
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struct lima_ip *ip = pipe->bcast_processor;
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int i;
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pipe->done = 0;
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atomic_set(&pipe->task, frame->num_pp);
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if (frame->use_dlbu) {
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lima_dlbu_enable(dev, frame->num_pp);
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frame->frame[LIMA_PP_FRAME >> 2] = LIMA_VA_RESERVE_DLBU;
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lima_dlbu_set_reg(dev->ip + lima_ip_dlbu, frame->dlbu_regs);
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} else
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lima_dlbu_disable(dev);
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lima_bcast_enable(dev, frame->num_pp);
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lima_pp_soft_reset_async_wait(ip);
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lima_pp_write_frame(ip, frame->frame, frame->wb);
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for (i = 0; i < frame->num_pp; i++) {
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struct lima_ip *ip = pipe->processor[i];
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pp_write(LIMA_PP_STACK, frame->fragment_stack_address[i]);
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if (!frame->use_dlbu)
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pp_write(LIMA_PP_FRAME, frame->plbu_array_address[i]);
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}
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pp_write(LIMA_PP_CTRL, LIMA_PP_CTRL_START_RENDERING);
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} else {
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struct drm_lima_m400_pp_frame *frame = task->frame;
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int i;
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atomic_set(&pipe->task, frame->num_pp);
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for (i = 0; i < frame->num_pp; i++) {
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struct lima_ip *ip = pipe->processor[i];
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frame->frame[LIMA_PP_FRAME >> 2] =
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frame->plbu_array_address[i];
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frame->frame[LIMA_PP_STACK >> 2] =
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frame->fragment_stack_address[i];
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lima_pp_soft_reset_async_wait(ip);
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lima_pp_write_frame(ip, frame->frame, frame->wb);
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pp_write(LIMA_PP_CTRL, LIMA_PP_CTRL_START_RENDERING);
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}
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}
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}
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static void lima_pp_task_fini(struct lima_sched_pipe *pipe)
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{
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if (pipe->bcast_processor)
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lima_pp_soft_reset_async(pipe->bcast_processor);
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else {
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int i;
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for (i = 0; i < pipe->num_processor; i++)
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lima_pp_soft_reset_async(pipe->processor[i]);
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}
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}
|
|
|
|
|
|
|
|
static void lima_pp_task_error(struct lima_sched_pipe *pipe)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < pipe->num_processor; i++) {
|
|
|
|
struct lima_ip *ip = pipe->processor[i];
|
|
|
|
|
|
|
|
dev_err(ip->dev->dev, "pp task error %d int_state=%x status=%x\n",
|
|
|
|
i, pp_read(LIMA_PP_INT_STATUS), pp_read(LIMA_PP_STATUS));
|
|
|
|
|
|
|
|
lima_pp_hard_reset(ip);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void lima_pp_task_mmu_error(struct lima_sched_pipe *pipe)
|
|
|
|
{
|
|
|
|
if (atomic_dec_and_test(&pipe->task))
|
|
|
|
lima_sched_pipe_task_done(pipe);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct kmem_cache *lima_pp_task_slab;
|
|
|
|
static int lima_pp_task_slab_refcnt;
|
|
|
|
|
|
|
|
int lima_pp_pipe_init(struct lima_device *dev)
|
|
|
|
{
|
|
|
|
int frame_size;
|
|
|
|
struct lima_sched_pipe *pipe = dev->pipe + lima_pipe_pp;
|
|
|
|
|
|
|
|
if (dev->id == lima_gpu_mali400)
|
|
|
|
frame_size = sizeof(struct drm_lima_m400_pp_frame);
|
|
|
|
else
|
|
|
|
frame_size = sizeof(struct drm_lima_m450_pp_frame);
|
|
|
|
|
|
|
|
if (!lima_pp_task_slab) {
|
|
|
|
lima_pp_task_slab = kmem_cache_create_usercopy(
|
|
|
|
"lima_pp_task", sizeof(struct lima_sched_task) + frame_size,
|
|
|
|
0, SLAB_HWCACHE_ALIGN, sizeof(struct lima_sched_task),
|
|
|
|
frame_size, NULL);
|
|
|
|
if (!lima_pp_task_slab)
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
lima_pp_task_slab_refcnt++;
|
|
|
|
|
|
|
|
pipe->frame_size = frame_size;
|
|
|
|
pipe->task_slab = lima_pp_task_slab;
|
|
|
|
|
|
|
|
pipe->task_validate = lima_pp_task_validate;
|
|
|
|
pipe->task_run = lima_pp_task_run;
|
|
|
|
pipe->task_fini = lima_pp_task_fini;
|
|
|
|
pipe->task_error = lima_pp_task_error;
|
|
|
|
pipe->task_mmu_error = lima_pp_task_mmu_error;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void lima_pp_pipe_fini(struct lima_device *dev)
|
|
|
|
{
|
|
|
|
if (!--lima_pp_task_slab_refcnt) {
|
|
|
|
kmem_cache_destroy(lima_pp_task_slab);
|
|
|
|
lima_pp_task_slab = NULL;
|
|
|
|
}
|
|
|
|
}
|