2005-04-17 06:20:36 +08:00
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/*
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2005-08-29 08:18:39 +08:00
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* ata_piix.c - Intel PATA/SATA controllers
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*
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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*
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* Copyright 2003-2005 Red Hat Inc
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* Copyright 2003-2005 Jeff Garzik
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*
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*
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* Copyright header from piix.c:
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*
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* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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2008-10-27 23:09:10 +08:00
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* Copyright (C) 2003 Red Hat Inc
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2005-08-29 08:18:39 +08:00
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available at http://developer.intel.com/
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*
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2005-12-09 03:19:50 +08:00
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* Documentation
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2011-03-31 09:57:33 +08:00
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* Publicly available from Intel web site. Errata documentation
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* is also publicly available. As an aide to anyone hacking on this
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2006-12-05 00:33:20 +08:00
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* driver the list of errata that are relevant is below, going back to
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2005-12-09 03:19:50 +08:00
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* PIIX4. Older device documentation is now a bit tricky to find.
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*
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2010-03-16 18:47:56 +08:00
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* The chipsets all follow very much the same design. The original Triton
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2011-03-31 09:57:33 +08:00
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* series chipsets do _not_ support independent device timings, but this
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2005-12-09 03:19:50 +08:00
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* is fixed in Triton II. With the odd mobile exception the chips then
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* change little except in gaining more modes until SATA arrives. This
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2011-03-31 09:57:33 +08:00
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* driver supports only the chips with independent timing (that is those
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2005-12-09 03:19:50 +08:00
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* with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
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* for the early chip drivers.
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*
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* Errata of note:
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*
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* Unfixable
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* PIIX4 errata #9 - Only on ultra obscure hw
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* ICH3 errata #13 - Not observed to affect real hw
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* by Intel
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*
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* Things we must deal with
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* PIIX4 errata #10 - BM IDE hang with non UDMA
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* (must stop/start dma to recover)
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* 440MX errata #15 - As PIIX4 errata #10
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* PIIX4 errata #15 - Must not read control registers
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* during a PIO transfer
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* 440MX errata #13 - As PIIX4 errata #15
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* ICH2 errata #21 - DMA mode 0 doesn't work right
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* ICH0/1 errata #55 - As ICH2 errata #21
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* ICH2 spec c #9 - Extra operations needed to handle
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* drive hotswap [NOT YET SUPPORTED]
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* ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
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* and must be dword aligned
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* ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
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2009-05-07 00:08:44 +08:00
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* ICH7 errata #16 - MWDMA1 timings are incorrect
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2005-12-09 03:19:50 +08:00
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*
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* Should have been BIOS fixed:
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* 450NX: errata #19 - DMA hangs on old 450NX
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* 450NX: errata #20 - DMA hangs on old 450NX
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* 450NX: errata #25 - Corruption with DMA on old 450NX
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* ICH3 errata #15 - IDE deadlock under high load
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* (BIOS must set dev 31 fn 0 bit 23)
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* ICH3 errata #18 - Don't use native mode
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2005-04-17 06:20:36 +08:00
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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2005-10-30 19:42:18 +08:00
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#include <linux/device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/gfp.h>
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2005-04-17 06:20:36 +08:00
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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2007-07-10 14:55:43 +08:00
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#include <linux/dmi.h>
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2005-04-17 06:20:36 +08:00
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#define DRV_NAME "ata_piix"
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2009-05-07 00:08:44 +08:00
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#define DRV_VERSION "2.13"
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2005-04-17 06:20:36 +08:00
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enum {
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PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
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ICH5_PMR = 0x90, /* port mapping register */
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ICH5_PCS = 0x92, /* port control and status */
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2008-01-18 17:36:30 +08:00
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PIIX_SIDPR_BAR = 5,
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PIIX_SIDPR_LEN = 16,
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PIIX_SIDPR_IDX = 0,
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PIIX_SIDPR_DATA = 4,
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2005-04-17 06:20:36 +08:00
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[PATCH] ata_piix: fix MAP VALUE interpretation for for ICH6/7
Unlike their older siblings, ICH6 and 7 use different scheme for MAP
VALUE. This patch makes ata_piix interpret MV properly on ICH6/7.
Pre-ICH6/7
The value of these bits indicate the address range the SATA port
responds to, and whether or not the SATA and IDE functions are
combined.
000 = Non-combined. P0 is primary master. P1 is secondary master.
001 = Non-combined. P0 is secondary master. P1 is primary master.
100 = Combined. P0 is primary master. P1 is primary slave. P-ATA is
2:0 Map Value secondary.
101 = Combined. P0 is primary slave. P1 is primary master. P-ATA is
secondary.
110 = Combined. P-ATA is primary. P0 is secondary master. P1 is
secondary slave.
111 = Combined. P-ATA is primary. P0 is secondary slave. P1 is
secondary master.
ICH6/7
Map Value - R/W. Map Value (MV): The value in the bits below indicate
the address range the SATA ports responds to, and whether or not the
PATA and SATA functions are combined. When in combined mode, the AHCI
memory space is not available and AHCI may not be used.
00 = Non-combined. P0 is primary master, P2 is the primary slave. P1
is secondary master, P3 is the 1:0 secondary slave (desktop
only). P0 is primary master, P2 is the primary slave (mobile
only).
01 = Combined. IDE is primary. P1 is secondary master, P3 is the
secondary slave. (desktop only)
10 = Combined. P0 is primary master. P2 is primary slave. IDE is secondary
11 = Reserved
Signed-off-by: Tejun Heo <htejun@gmail.com>
--
Jeff, without this patch, ata_piix misdetects my ICH7's combined mode,
ending up not applying bridge limits to PX-710SA and configuring IDE
drive on 40-c cable to UDMA/66.
Thanks.
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2005-12-18 16:17:07 +08:00
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PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
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2008-01-18 17:36:30 +08:00
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PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
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2005-04-17 06:20:36 +08:00
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2006-12-03 20:34:13 +08:00
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PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
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PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
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2006-11-10 17:08:10 +08:00
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2011-10-07 11:50:22 +08:00
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PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
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2005-04-17 06:20:36 +08:00
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PIIX_80C_PRI = (1 << 5) | (1 << 4),
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PIIX_80C_SEC = (1 << 7) | (1 << 6),
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2006-03-01 00:25:39 +08:00
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/* constants for mapping table */
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P0 = 0, /* port 0 */
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P1 = 1, /* port 1 */
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P2 = 2, /* port 2 */
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P3 = 3, /* port 3 */
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IDE = -1, /* IDE */
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2011-03-31 09:57:33 +08:00
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NA = -2, /* not available */
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2006-03-01 00:25:39 +08:00
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RV = -3, /* reserved */
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2005-07-29 03:54:15 +08:00
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PIIX_AHCI_DEVICE = 6,
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2007-07-10 14:55:43 +08:00
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/* host->flags bits */
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PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
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2005-04-17 06:20:36 +08:00
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};
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2007-11-24 20:16:07 +08:00
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enum piix_controller_ids {
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/* controller IDs */
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piix_pata_mwdma, /* PIIX3 MWDMA only */
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piix_pata_33, /* PIIX4 at 33Mhz */
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ich_pata_33, /* ICH up to UDMA 33 only */
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ich_pata_66, /* ICH up to 66 Mhz */
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ich_pata_100, /* ICH up to UDMA 100 */
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2009-05-07 00:08:44 +08:00
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ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
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2007-11-24 20:16:07 +08:00
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ich5_sata,
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ich6_sata,
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2008-03-26 15:00:58 +08:00
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ich6m_sata,
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ich8_sata,
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2007-11-24 20:16:07 +08:00
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ich8_2port_sata,
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2008-03-26 15:00:58 +08:00
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ich8m_apple_sata, /* locks up on second port enable */
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tolapai_sata,
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2007-11-24 20:16:07 +08:00
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piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
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2011-10-07 11:50:22 +08:00
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ich8_sata_snb,
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2007-11-24 20:16:07 +08:00
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};
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2006-03-01 00:25:39 +08:00
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struct piix_map_db {
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const u32 mask;
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2006-07-12 01:11:17 +08:00
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const u16 port_enable;
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2006-03-01 00:25:39 +08:00
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const int map[][4];
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};
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2006-06-29 00:58:28 +08:00
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struct piix_host_priv {
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const int *map;
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2009-01-02 11:04:48 +08:00
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u32 saved_iocfg;
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2008-01-18 17:36:30 +08:00
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void __iomem *sidpr;
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2006-06-29 00:58:28 +08:00
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};
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2007-10-19 18:42:56 +08:00
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static int piix_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent);
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2009-01-02 11:04:48 +08:00
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static void piix_remove_one(struct pci_dev *pdev);
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libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:50 +08:00
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static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
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2007-10-19 18:42:56 +08:00
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static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
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static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
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2007-04-11 07:04:20 +08:00
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static int ich_pata_cable_detect(struct ata_port *ap);
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2008-01-07 18:38:53 +08:00
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static u8 piix_vmw_bmdma_status(struct ata_port *ap);
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2008-07-31 16:02:40 +08:00
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static int piix_sidpr_scr_read(struct ata_link *link,
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unsigned int reg, u32 *val);
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static int piix_sidpr_scr_write(struct ata_link *link,
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unsigned int reg, u32 val);
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2010-09-01 23:50:08 +08:00
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static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
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unsigned hints);
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2010-01-19 09:49:19 +08:00
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static bool piix_irq_check(struct ata_port *ap);
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2011-10-07 11:50:22 +08:00
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static int piix_port_start(struct ata_port *ap);
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2007-07-10 14:55:43 +08:00
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#ifdef CONFIG_PM
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static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
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static int piix_pci_device_resume(struct pci_dev *pdev);
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#endif
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2005-04-17 06:20:36 +08:00
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static unsigned int in_module_init = 1;
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2005-11-11 00:04:11 +08:00
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static const struct pci_device_id piix_pci_tbl[] = {
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2007-01-11 01:13:38 +08:00
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/* Intel PIIX3 for the 430HX etc */
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{ 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
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2008-01-07 18:38:53 +08:00
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/* VMware ICH4 */
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{ 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
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2006-08-30 06:12:40 +08:00
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|
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/* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
|
|
|
|
/* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
|
|
|
|
{ 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
|
|
|
|
/* Intel PIIX4 */
|
|
|
|
{ 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
|
|
|
|
/* Intel PIIX4 */
|
|
|
|
{ 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
|
|
|
|
/* Intel PIIX */
|
|
|
|
{ 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
|
|
|
|
/* Intel ICH (i810, i815, i840) UDMA 66*/
|
|
|
|
{ 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
|
|
|
|
/* Intel ICH0 : UDMA 33*/
|
|
|
|
{ 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
|
|
|
|
/* Intel ICH2M */
|
|
|
|
{ 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
|
|
/* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
|
|
|
|
{ 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
|
|
/* Intel ICH3M */
|
|
|
|
{ 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
|
|
/* Intel ICH3 (E7500/1) UDMA 100 */
|
|
|
|
{ 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
2010-10-11 05:42:21 +08:00
|
|
|
/* Intel ICH4-L */
|
|
|
|
{ 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
|
|
|
|
{ 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
|
|
{ 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
|
|
/* Intel ICH5 */
|
2007-08-11 04:59:51 +08:00
|
|
|
{ 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
2006-08-30 06:12:40 +08:00
|
|
|
/* C-ICH (i810E2) */
|
|
|
|
{ 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
2006-08-31 12:03:49 +08:00
|
|
|
/* ESB (855GME/875P + 6300ESB) UDMA 100 */
|
2006-08-30 06:12:40 +08:00
|
|
|
{ 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
|
|
/* ICH6 (and 6) (i915) UDMA 100 */
|
|
|
|
{ 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
|
|
|
/* ICH7/7-R (i945, i975) UDMA 100*/
|
2009-05-07 00:08:44 +08:00
|
|
|
{ 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
|
|
|
|
{ 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
|
2007-07-03 22:19:20 +08:00
|
|
|
/* ICH8 Mobile PATA Controller */
|
|
|
|
{ 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2009-05-07 00:10:17 +08:00
|
|
|
/* SATA ports */
|
2011-02-15 14:13:24 +08:00
|
|
|
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 82801EB (ICH5) */
|
2005-04-17 06:20:36 +08:00
|
|
|
{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 82801EB (ICH5) */
|
2005-04-17 06:20:36 +08:00
|
|
|
{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 6300ESB (ICH5 variant with broken PCS present bits) */
|
2006-11-10 17:08:10 +08:00
|
|
|
{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 6300ESB pretending RAID */
|
2006-11-10 17:08:10 +08:00
|
|
|
{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 82801FB/FW (ICH6/ICH6W) */
|
2005-04-17 06:20:36 +08:00
|
|
|
{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 82801FR/FRW (ICH6R/ICH6RW) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
|
2008-03-26 14:46:58 +08:00
|
|
|
/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
|
|
|
|
* Attach iff the controller is in IDE mode. */
|
|
|
|
{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
|
2008-03-26 15:00:58 +08:00
|
|
|
PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 82801GB/GR/GH (ICH7, identical to ICH6) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
|
2006-03-01 00:25:39 +08:00
|
|
|
/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* Enterprise Southbridge 2 (631xESB/632xESB) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller 1 IDE (ICH8) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller 2 IDE (ICH8) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2007-11-19 10:54:24 +08:00
|
|
|
/* Mobile SATA Controller IDE (ICH8M), Apple */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
|
2008-05-29 21:04:22 +08:00
|
|
|
{ 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
|
2008-07-29 14:06:26 +08:00
|
|
|
{ 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
|
2008-05-29 21:04:22 +08:00
|
|
|
/* Mobile SATA Controller IDE (ICH8M) */
|
|
|
|
{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9M) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9M) */
|
2007-11-19 10:24:25 +08:00
|
|
|
{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2006-12-08 00:57:32 +08:00
|
|
|
/* SATA Controller IDE (ICH9M) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
2007-08-31 12:36:56 +08:00
|
|
|
/* SATA Controller IDE (Tolapai) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
|
2008-01-29 09:36:45 +08:00
|
|
|
/* SATA Controller IDE (ICH10) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
2008-01-29 09:36:45 +08:00
|
|
|
/* SATA Controller IDE (ICH10) */
|
|
|
|
{ 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
|
|
|
/* SATA Controller IDE (ICH10) */
|
2008-03-26 15:00:58 +08:00
|
|
|
{ 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
2008-01-29 09:36:45 +08:00
|
|
|
/* SATA Controller IDE (ICH10) */
|
|
|
|
{ 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2008-08-12 08:03:18 +08:00
|
|
|
/* SATA Controller IDE (PCH) */
|
|
|
|
{ 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
|
|
|
/* SATA Controller IDE (PCH) */
|
2008-08-28 07:40:06 +08:00
|
|
|
{ 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
|
|
|
/* SATA Controller IDE (PCH) */
|
2008-08-12 08:03:18 +08:00
|
|
|
{ 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
|
|
|
/* SATA Controller IDE (PCH) */
|
2008-08-28 07:40:06 +08:00
|
|
|
{ 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
|
|
|
/* SATA Controller IDE (PCH) */
|
2008-08-12 08:03:18 +08:00
|
|
|
{ 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
|
|
|
/* SATA Controller IDE (PCH) */
|
|
|
|
{ 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
|
2010-01-13 09:01:28 +08:00
|
|
|
/* SATA Controller IDE (CPT) */
|
2011-10-07 11:50:22 +08:00
|
|
|
{ 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
|
2010-01-13 09:01:28 +08:00
|
|
|
/* SATA Controller IDE (CPT) */
|
2011-10-07 11:50:22 +08:00
|
|
|
{ 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
|
2010-01-13 09:01:28 +08:00
|
|
|
/* SATA Controller IDE (CPT) */
|
|
|
|
{ 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
|
|
|
/* SATA Controller IDE (CPT) */
|
|
|
|
{ 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2010-09-10 00:42:40 +08:00
|
|
|
/* SATA Controller IDE (PBG) */
|
2011-10-07 11:50:22 +08:00
|
|
|
{ 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
|
2010-09-10 00:42:40 +08:00
|
|
|
/* SATA Controller IDE (PBG) */
|
|
|
|
{ 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2011-04-20 23:43:37 +08:00
|
|
|
/* SATA Controller IDE (Panther Point) */
|
2011-10-07 11:50:22 +08:00
|
|
|
{ 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
|
2011-04-20 23:43:37 +08:00
|
|
|
/* SATA Controller IDE (Panther Point) */
|
2011-10-07 11:50:22 +08:00
|
|
|
{ 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
|
2011-04-20 23:43:37 +08:00
|
|
|
/* SATA Controller IDE (Panther Point) */
|
|
|
|
{ 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
|
|
|
/* SATA Controller IDE (Panther Point) */
|
|
|
|
{ 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2012-01-24 08:29:50 +08:00
|
|
|
/* SATA Controller IDE (Lynx Point) */
|
|
|
|
{ 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
|
|
|
|
/* SATA Controller IDE (Lynx Point) */
|
|
|
|
{ 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
|
|
|
|
/* SATA Controller IDE (Lynx Point) */
|
|
|
|
{ 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
|
|
|
/* SATA Controller IDE (Lynx Point) */
|
|
|
|
{ 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
|
2005-04-17 06:20:36 +08:00
|
|
|
{ } /* terminate list */
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver piix_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = piix_pci_tbl,
|
|
|
|
.probe = piix_init_one,
|
2009-01-02 11:04:48 +08:00
|
|
|
.remove = piix_remove_one,
|
2007-03-02 16:31:26 +08:00
|
|
|
#ifdef CONFIG_PM
|
2007-07-10 14:55:43 +08:00
|
|
|
.suspend = piix_pci_device_suspend,
|
|
|
|
.resume = piix_pci_device_resume,
|
2007-03-02 16:31:26 +08:00
|
|
|
#endif
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
2005-11-07 13:59:37 +08:00
|
|
|
static struct scsi_host_template piix_sht = {
|
2008-03-25 11:22:49 +08:00
|
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
2010-01-19 09:49:19 +08:00
|
|
|
static struct ata_port_operations piix_sata_ops = {
|
2009-01-05 22:16:39 +08:00
|
|
|
.inherits = &ata_bmdma32_port_ops,
|
2010-01-19 09:49:19 +08:00
|
|
|
.sff_irq_check = piix_irq_check,
|
2011-10-07 11:50:22 +08:00
|
|
|
.port_start = piix_port_start,
|
2010-01-19 09:49:19 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct ata_port_operations piix_pata_ops = {
|
|
|
|
.inherits = &piix_sata_ops,
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
|
|
|
.cable_detect = ata_cable_40wire,
|
2005-04-17 06:20:36 +08:00
|
|
|
.set_piomode = piix_set_piomode,
|
|
|
|
.set_dmamode = piix_set_dmamode,
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:50 +08:00
|
|
|
.prereset = piix_pata_prereset,
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
|
|
|
static struct ata_port_operations piix_vmw_ops = {
|
|
|
|
.inherits = &piix_pata_ops,
|
|
|
|
.bmdma_status = piix_vmw_bmdma_status,
|
2006-08-30 06:12:40 +08:00
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
|
|
|
static struct ata_port_operations ich_pata_ops = {
|
|
|
|
.inherits = &piix_pata_ops,
|
|
|
|
.cable_detect = ich_pata_cable_detect,
|
|
|
|
.set_dmamode = ich_set_dmamode,
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
2010-09-01 23:50:08 +08:00
|
|
|
static struct device_attribute *piix_sidpr_shost_attrs[] = {
|
|
|
|
&dev_attr_link_power_management_policy,
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct scsi_host_template piix_sidpr_sht = {
|
|
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
|
|
|
.shost_attrs = piix_sidpr_shost_attrs,
|
|
|
|
};
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 11:22:49 +08:00
|
|
|
static struct ata_port_operations piix_sidpr_sata_ops = {
|
|
|
|
.inherits = &piix_sata_ops,
|
2008-04-07 21:47:19 +08:00
|
|
|
.hardreset = sata_std_hardreset,
|
2008-01-18 17:36:30 +08:00
|
|
|
.scr_read = piix_sidpr_scr_read,
|
|
|
|
.scr_write = piix_sidpr_scr_write,
|
2010-09-01 23:50:08 +08:00
|
|
|
.set_lpm = piix_sidpr_set_lpm,
|
2008-01-18 17:36:30 +08:00
|
|
|
};
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
static const struct piix_map_db ich5_map_db = {
|
2006-03-01 00:25:39 +08:00
|
|
|
.mask = 0x7,
|
2006-07-11 23:48:50 +08:00
|
|
|
.port_enable = 0x3,
|
2006-03-01 00:25:39 +08:00
|
|
|
.map = {
|
|
|
|
/* PM PS SM SS MAP */
|
|
|
|
{ P0, NA, P1, NA }, /* 000b */
|
|
|
|
{ P1, NA, P0, NA }, /* 001b */
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
{ P0, P1, IDE, IDE }, /* 100b */
|
|
|
|
{ P1, P0, IDE, IDE }, /* 101b */
|
|
|
|
{ IDE, IDE, P0, P1 }, /* 110b */
|
|
|
|
{ IDE, IDE, P1, P0 }, /* 111b */
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
static const struct piix_map_db ich6_map_db = {
|
2006-03-01 00:25:39 +08:00
|
|
|
.mask = 0x3,
|
2006-07-11 23:48:50 +08:00
|
|
|
.port_enable = 0xf,
|
2006-03-01 00:25:39 +08:00
|
|
|
.map = {
|
|
|
|
/* PM PS SM SS MAP */
|
2006-03-31 19:01:50 +08:00
|
|
|
{ P0, P2, P1, P3 }, /* 00b */
|
2006-03-01 00:25:39 +08:00
|
|
|
{ IDE, IDE, P1, P3 }, /* 01b */
|
|
|
|
{ P0, P2, IDE, IDE }, /* 10b */
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
static const struct piix_map_db ich6m_map_db = {
|
2006-03-01 00:25:39 +08:00
|
|
|
.mask = 0x3,
|
2006-07-11 23:48:50 +08:00
|
|
|
.port_enable = 0x5,
|
2006-09-11 05:29:03 +08:00
|
|
|
|
|
|
|
/* Map 01b isn't specified in the doc but some notebooks use
|
2006-10-09 12:23:58 +08:00
|
|
|
* it anyway. MAP 01b have been spotted on both ICH6M and
|
|
|
|
* ICH7M.
|
2006-09-11 05:29:03 +08:00
|
|
|
*/
|
|
|
|
.map = {
|
|
|
|
/* PM PS SM SS MAP */
|
2007-07-10 16:58:21 +08:00
|
|
|
{ P0, P2, NA, NA }, /* 00b */
|
2006-09-11 05:29:03 +08:00
|
|
|
{ IDE, IDE, P1, P3 }, /* 01b */
|
|
|
|
{ P0, P2, IDE, IDE }, /* 10b */
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2006-07-11 23:57:44 +08:00
|
|
|
static const struct piix_map_db ich8_map_db = {
|
|
|
|
.mask = 0x3,
|
2007-11-19 11:06:37 +08:00
|
|
|
.port_enable = 0xf,
|
2006-07-11 23:57:44 +08:00
|
|
|
.map = {
|
|
|
|
/* PM PS SM SS MAP */
|
2006-10-20 04:27:39 +08:00
|
|
|
{ P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
|
2006-07-11 23:57:44 +08:00
|
|
|
{ RV, RV, RV, RV },
|
2007-08-07 01:43:27 +08:00
|
|
|
{ P0, P2, IDE, IDE }, /* 10b (IDE mode) */
|
2006-07-11 23:57:44 +08:00
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2007-11-19 10:24:25 +08:00
|
|
|
static const struct piix_map_db ich8_2port_map_db = {
|
2007-09-08 08:21:03 +08:00
|
|
|
.mask = 0x3,
|
|
|
|
.port_enable = 0x3,
|
|
|
|
.map = {
|
|
|
|
/* PM PS SM SS MAP */
|
|
|
|
{ P0, NA, P1, NA }, /* 00b */
|
|
|
|
{ RV, RV, RV, RV }, /* 01b */
|
|
|
|
{ RV, RV, RV, RV }, /* 10b */
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
},
|
2007-08-31 12:36:56 +08:00
|
|
|
};
|
|
|
|
|
2007-11-19 10:54:24 +08:00
|
|
|
static const struct piix_map_db ich8m_apple_map_db = {
|
|
|
|
.mask = 0x3,
|
|
|
|
.port_enable = 0x1,
|
|
|
|
.map = {
|
|
|
|
/* PM PS SM SS MAP */
|
|
|
|
{ P0, NA, NA, NA }, /* 00b */
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
{ P0, P2, IDE, IDE }, /* 10b */
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2007-11-19 10:24:25 +08:00
|
|
|
static const struct piix_map_db tolapai_map_db = {
|
2007-10-12 07:05:15 +08:00
|
|
|
.mask = 0x3,
|
|
|
|
.port_enable = 0x3,
|
|
|
|
.map = {
|
|
|
|
/* PM PS SM SS MAP */
|
|
|
|
{ P0, NA, P1, NA }, /* 00b */
|
|
|
|
{ RV, RV, RV, RV }, /* 01b */
|
|
|
|
{ RV, RV, RV, RV }, /* 10b */
|
|
|
|
{ RV, RV, RV, RV },
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2006-06-29 00:58:28 +08:00
|
|
|
static const struct piix_map_db *piix_map_db_table[] = {
|
|
|
|
[ich5_sata] = &ich5_map_db,
|
|
|
|
[ich6_sata] = &ich6_map_db,
|
2008-03-26 15:00:58 +08:00
|
|
|
[ich6m_sata] = &ich6m_map_db,
|
|
|
|
[ich8_sata] = &ich8_map_db,
|
2007-11-19 10:24:25 +08:00
|
|
|
[ich8_2port_sata] = &ich8_2port_map_db,
|
2008-03-26 15:00:58 +08:00
|
|
|
[ich8m_apple_sata] = &ich8m_apple_map_db,
|
|
|
|
[tolapai_sata] = &tolapai_map_db,
|
2011-10-07 11:50:22 +08:00
|
|
|
[ich8_sata_snb] = &ich8_map_db,
|
2006-06-29 00:58:28 +08:00
|
|
|
};
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static struct ata_port_info piix_port_info[] = {
|
2007-11-19 10:24:25 +08:00
|
|
|
[piix_pata_mwdma] = /* PIIX3 MWDMA only */
|
|
|
|
{
|
|
|
|
.flags = PIIX_PATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
|
2007-11-19 10:24:25 +08:00
|
|
|
.port_ops = &piix_pata_ops,
|
|
|
|
},
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[piix_pata_33] = /* PIIX4 at 33MHz */
|
2006-03-01 00:25:39 +08:00
|
|
|
{
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_PATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
|
|
|
|
.udma_mask = ATA_UDMA2,
|
2006-03-01 00:25:39 +08:00
|
|
|
.port_ops = &piix_pata_ops,
|
|
|
|
},
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_PATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
|
|
|
|
.udma_mask = ATA_UDMA2,
|
2006-08-30 06:12:40 +08:00
|
|
|
.port_ops = &ich_pata_ops,
|
|
|
|
},
|
2007-09-01 19:17:36 +08:00
|
|
|
|
|
|
|
[ich_pata_66] = /* ICH controllers up to 66MHz */
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_PATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
|
2006-08-30 06:12:40 +08:00
|
|
|
.udma_mask = ATA_UDMA4,
|
|
|
|
.port_ops = &ich_pata_ops,
|
|
|
|
},
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich_pata_100] =
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY,
|
|
|
|
.udma_mask = ATA_UDMA5,
|
2006-08-30 06:12:40 +08:00
|
|
|
.port_ops = &ich_pata_ops,
|
2005-04-17 06:20:36 +08:00
|
|
|
},
|
|
|
|
|
2009-05-07 00:08:44 +08:00
|
|
|
[ich_pata_100_nomwdma1] =
|
|
|
|
{
|
|
|
|
.flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
|
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2_ONLY,
|
|
|
|
.udma_mask = ATA_UDMA5,
|
|
|
|
.port_ops = &ich_pata_ops,
|
|
|
|
},
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich5_sata] =
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2006-11-10 17:08:10 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2005-04-17 06:20:36 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
},
|
|
|
|
|
2007-09-01 19:17:36 +08:00
|
|
|
[ich6_sata] =
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2008-01-04 17:42:20 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2005-04-17 06:20:36 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
},
|
|
|
|
|
2008-03-26 15:00:58 +08:00
|
|
|
[ich6m_sata] =
|
2005-04-17 06:24:44 +08:00
|
|
|
{
|
2008-03-26 14:46:58 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2005-04-17 06:24:44 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
},
|
2006-03-01 00:25:39 +08:00
|
|
|
|
2008-03-26 15:00:58 +08:00
|
|
|
[ich8_sata] =
|
2006-07-11 23:57:44 +08:00
|
|
|
{
|
2008-03-26 14:46:58 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2007-07-10 00:16:50 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2006-07-11 23:57:44 +08:00
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
},
|
2006-08-30 06:12:40 +08:00
|
|
|
|
2007-11-19 10:24:25 +08:00
|
|
|
[ich8_2port_sata] =
|
2007-08-31 12:36:56 +08:00
|
|
|
{
|
2008-03-26 14:46:58 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2007-08-31 12:36:56 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
},
|
2007-10-12 07:05:15 +08:00
|
|
|
|
2008-03-26 15:00:58 +08:00
|
|
|
[tolapai_sata] =
|
2007-10-12 07:05:15 +08:00
|
|
|
{
|
2008-03-26 14:46:58 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2007-10-12 07:05:15 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
},
|
2007-11-19 10:54:24 +08:00
|
|
|
|
2008-03-26 15:00:58 +08:00
|
|
|
[ich8m_apple_sata] =
|
2007-11-19 10:54:24 +08:00
|
|
|
{
|
2008-05-29 21:04:22 +08:00
|
|
|
.flags = PIIX_SATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
2007-11-19 10:54:24 +08:00
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
},
|
|
|
|
|
2008-01-07 18:38:53 +08:00
|
|
|
[piix_pata_vmw] =
|
|
|
|
{
|
|
|
|
.flags = PIIX_PATA_FLAGS,
|
2009-03-15 04:38:24 +08:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
|
|
|
|
.udma_mask = ATA_UDMA2,
|
2008-01-07 18:38:53 +08:00
|
|
|
.port_ops = &piix_vmw_ops,
|
|
|
|
},
|
|
|
|
|
2011-10-07 11:50:22 +08:00
|
|
|
/*
|
|
|
|
* some Sandybridge chipsets have broken 32 mode up to now,
|
|
|
|
* see https://bugzilla.kernel.org/show_bug.cgi?id=40592
|
|
|
|
*/
|
|
|
|
[ich8_sata_snb] =
|
|
|
|
{
|
|
|
|
.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
|
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
.mwdma_mask = ATA_MWDMA2,
|
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &piix_sata_ops,
|
|
|
|
},
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_bits piix_enable_bits[] = {
|
|
|
|
{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
|
|
|
|
{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
|
|
|
|
MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
2006-10-11 05:28:11 +08:00
|
|
|
struct ich_laptop {
|
|
|
|
u16 device;
|
|
|
|
u16 subvendor;
|
|
|
|
u16 subdevice;
|
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* List of laptops that use short cables rather than 80 wire
|
|
|
|
*/
|
|
|
|
|
|
|
|
static const struct ich_laptop ich_laptop[] = {
|
|
|
|
/* devid, subvendor, subdev */
|
|
|
|
{ 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
|
2007-11-06 06:51:09 +08:00
|
|
|
{ 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
|
2007-01-09 01:26:30 +08:00
|
|
|
{ 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
|
2009-07-17 05:27:56 +08:00
|
|
|
{ 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
|
2007-03-29 09:02:07 +08:00
|
|
|
{ 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
|
2007-09-29 16:01:43 +08:00
|
|
|
{ 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
|
tree-wide: fix assorted typos all over the place
That is "success", "unknown", "through", "performance", "[re|un]mapping"
, "access", "default", "reasonable", "[con]currently", "temperature"
, "channel", "[un]used", "application", "example","hierarchy", "therefore"
, "[over|under]flow", "contiguous", "threshold", "enough" and others.
Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2009-11-14 23:09:05 +08:00
|
|
|
{ 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
|
2008-09-18 01:29:05 +08:00
|
|
|
{ 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
|
2009-07-17 05:27:56 +08:00
|
|
|
{ 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
|
2007-05-22 17:34:22 +08:00
|
|
|
{ 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
|
2008-06-04 00:59:02 +08:00
|
|
|
{ 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
|
|
|
|
{ 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
|
2008-04-21 11:03:27 +08:00
|
|
|
{ 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
|
2009-05-07 00:09:41 +08:00
|
|
|
{ 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
|
2006-10-11 05:28:11 +08:00
|
|
|
/* end marker */
|
|
|
|
{ 0, }
|
|
|
|
};
|
|
|
|
|
2011-10-07 11:50:22 +08:00
|
|
|
static int piix_port_start(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
if (!(ap->flags & PIIX_FLAG_PIO16))
|
|
|
|
ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
|
|
|
|
|
|
|
|
return ata_bmdma_port_start(ap);
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/**
|
2007-04-11 07:04:20 +08:00
|
|
|
* ich_pata_cable_detect - Probe host controller cable detect info
|
2005-04-17 06:20:36 +08:00
|
|
|
* @ap: Port for which cable detect info is desired
|
|
|
|
*
|
|
|
|
* Read 80c cable indicator from ATA PCI device's PCI config
|
|
|
|
* register. This register is normally set by firmware (BIOS).
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
2006-08-30 06:12:40 +08:00
|
|
|
|
2007-04-11 07:04:20 +08:00
|
|
|
static int ich_pata_cable_detect(struct ata_port *ap)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2006-08-24 15:19:22 +08:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2009-01-02 11:04:48 +08:00
|
|
|
struct piix_host_priv *hpriv = ap->host->private_data;
|
2006-10-11 05:28:11 +08:00
|
|
|
const struct ich_laptop *lap = &ich_laptop[0];
|
2009-01-02 11:04:48 +08:00
|
|
|
u8 mask;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-10-11 05:28:11 +08:00
|
|
|
/* Check for specials - Acer Aspire 5602WLMi */
|
|
|
|
while (lap->device) {
|
|
|
|
if (lap->device == pdev->device &&
|
|
|
|
lap->subvendor == pdev->subsystem_vendor &&
|
2007-10-19 18:42:56 +08:00
|
|
|
lap->subdevice == pdev->subsystem_device)
|
2007-04-11 07:04:20 +08:00
|
|
|
return ATA_CBL_PATA40_SHORT;
|
2007-10-19 18:42:56 +08:00
|
|
|
|
2006-10-11 05:28:11 +08:00
|
|
|
lap++;
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/* check BIOS cable detect results */
|
2006-08-10 15:59:16 +08:00
|
|
|
mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
|
2009-01-02 11:04:48 +08:00
|
|
|
if ((hpriv->saved_iocfg & mask) == 0)
|
2007-04-11 07:04:20 +08:00
|
|
|
return ATA_CBL_PATA40;
|
|
|
|
return ATA_CBL_PATA80;
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2006-05-31 17:28:14 +08:00
|
|
|
* piix_pata_prereset - prereset for PATA host controller
|
2007-08-06 17:36:23 +08:00
|
|
|
* @link: Target link
|
libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 15:50:52 +08:00
|
|
|
* @deadline: deadline jiffies for the operation
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
2006-02-15 14:01:42 +08:00
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
2007-08-06 17:36:23 +08:00
|
|
|
static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-08-06 17:36:23 +08:00
|
|
|
struct ata_port *ap = link->ap;
|
2006-08-24 15:19:22 +08:00
|
|
|
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2006-09-27 00:53:38 +08:00
|
|
|
if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
|
|
|
|
return -ENOENT;
|
2008-04-07 21:47:16 +08:00
|
|
|
return ata_sff_prereset(link, deadline);
|
2006-05-31 17:28:14 +08:00
|
|
|
}
|
|
|
|
|
ata_piix: parallel scanning on PATA needs an extra locking
Commit log for commit 517d3cc15b36392e518abab6bacbb72089658313
("[libata] ata_piix: Enable parallel scan") says:
This patch turns on parallel scanning for the ata_piix driver.
This driver is used on most netbooks (no AHCI for cheap storage it seems).
The scan is the dominating time factor in the kernel boot for these
devices; with this flag it gets cut in half for the device I used
for testing (eeepc).
Alan took a look at the driver source and concluded that it ought to be safe
to do for this driver. Alan has also checked with the hardware team.
and it is all true but once we put all things together additional
constraints for PATA controllers show up (some hardware registers
have per-host not per-port atomicity) and we risk misprogramming
the controller.
I used the following test to check whether the issue is real:
@@ -736,8 +736,20 @@ static void piix_set_piomode(struct ata_
(timings[pio][1] << 8);
}
pci_write_config_word(dev, master_port, master_data);
- if (is_slave)
+ if (is_slave) {
+ if (ap->port_no == 0) {
+ u8 tmp = slave_data;
+
+ while (slave_data == tmp) {
+ pci_read_config_byte(dev, slave_port, &tmp);
+ msleep(50);
+ }
+
+ dev_printk(KERN_ERR, &dev->dev, "PATA parallel scan "
+ "race detected\n");
+ }
pci_write_config_byte(dev, slave_port, slave_data);
+ }
/* Ensure the UDMA bit is off - it will be turned back on if
UDMA is selected */
and it indeed triggered the error message.
Lets fix all such races by adding an extra locking to ->set_piomode
and ->set_dmamode methods for PATA controllers.
[ Alan: would be better to take the host lock in libata-core for these
cases so that we fix all the adapters in one swoop. "Looks fine as a
temproary quickfix tho" ]
Cc: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Cc: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-08-30 20:56:30 +08:00
|
|
|
static DEFINE_SPINLOCK(piix_lock);
|
|
|
|
|
2011-10-13 21:39:10 +08:00
|
|
|
static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
|
|
|
|
u8 pio)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2006-08-24 15:19:22 +08:00
|
|
|
struct pci_dev *dev = to_pci_dev(ap->host->dev);
|
ata_piix: parallel scanning on PATA needs an extra locking
Commit log for commit 517d3cc15b36392e518abab6bacbb72089658313
("[libata] ata_piix: Enable parallel scan") says:
This patch turns on parallel scanning for the ata_piix driver.
This driver is used on most netbooks (no AHCI for cheap storage it seems).
The scan is the dominating time factor in the kernel boot for these
devices; with this flag it gets cut in half for the device I used
for testing (eeepc).
Alan took a look at the driver source and concluded that it ought to be safe
to do for this driver. Alan has also checked with the hardware team.
and it is all true but once we put all things together additional
constraints for PATA controllers show up (some hardware registers
have per-host not per-port atomicity) and we risk misprogramming
the controller.
I used the following test to check whether the issue is real:
@@ -736,8 +736,20 @@ static void piix_set_piomode(struct ata_
(timings[pio][1] << 8);
}
pci_write_config_word(dev, master_port, master_data);
- if (is_slave)
+ if (is_slave) {
+ if (ap->port_no == 0) {
+ u8 tmp = slave_data;
+
+ while (slave_data == tmp) {
+ pci_read_config_byte(dev, slave_port, &tmp);
+ msleep(50);
+ }
+
+ dev_printk(KERN_ERR, &dev->dev, "PATA parallel scan "
+ "race detected\n");
+ }
pci_write_config_byte(dev, slave_port, slave_data);
+ }
/* Ensure the UDMA bit is off - it will be turned back on if
UDMA is selected */
and it indeed triggered the error message.
Lets fix all such races by adding an extra locking to ->set_piomode
and ->set_dmamode methods for PATA controllers.
[ Alan: would be better to take the host lock in libata-core for these
cases so that we fix all the adapters in one swoop. "Looks fine as a
temproary quickfix tho" ]
Cc: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Cc: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-08-30 20:56:30 +08:00
|
|
|
unsigned long flags;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned int is_slave = (adev->devno != 0);
|
2006-08-10 15:59:16 +08:00
|
|
|
unsigned int master_port= ap->port_no ? 0x42 : 0x40;
|
2005-04-17 06:20:36 +08:00
|
|
|
unsigned int slave_port = 0x44;
|
|
|
|
u16 master_data;
|
|
|
|
u8 slave_data;
|
2006-08-30 06:12:40 +08:00
|
|
|
u8 udma_enable;
|
|
|
|
int control = 0;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/*
|
|
|
|
* See Intel Document 298600-004 for the timing programing rules
|
|
|
|
* for ICH controllers.
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
|
|
|
|
static const /* ISP RTC */
|
|
|
|
u8 timings[][2] = { { 0, 0 },
|
|
|
|
{ 0, 0 },
|
|
|
|
{ 1, 0 },
|
|
|
|
{ 2, 1 },
|
|
|
|
{ 2, 3 }, };
|
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
if (pio >= 2)
|
|
|
|
control |= 1; /* TIME1 enable */
|
|
|
|
if (ata_pio_need_iordy(adev))
|
|
|
|
control |= 2; /* IE enable */
|
2006-08-31 12:03:49 +08:00
|
|
|
/* Intel specifies that the PPE functionality is for disk only */
|
2006-08-30 06:12:40 +08:00
|
|
|
if (adev->class == ATA_DEV_ATA)
|
|
|
|
control |= 4; /* PPE enable */
|
2011-10-13 21:39:10 +08:00
|
|
|
/*
|
|
|
|
* If the drive MWDMA is faster than it can do PIO then
|
|
|
|
* we must force PIO into PIO0
|
|
|
|
*/
|
|
|
|
if (adev->pio_mode < XFER_PIO_0 + pio)
|
|
|
|
/* Enable DMA timing only */
|
|
|
|
control |= 8; /* PIO cycles in PIO0 */
|
2006-08-30 06:12:40 +08:00
|
|
|
|
ata_piix: parallel scanning on PATA needs an extra locking
Commit log for commit 517d3cc15b36392e518abab6bacbb72089658313
("[libata] ata_piix: Enable parallel scan") says:
This patch turns on parallel scanning for the ata_piix driver.
This driver is used on most netbooks (no AHCI for cheap storage it seems).
The scan is the dominating time factor in the kernel boot for these
devices; with this flag it gets cut in half for the device I used
for testing (eeepc).
Alan took a look at the driver source and concluded that it ought to be safe
to do for this driver. Alan has also checked with the hardware team.
and it is all true but once we put all things together additional
constraints for PATA controllers show up (some hardware registers
have per-host not per-port atomicity) and we risk misprogramming
the controller.
I used the following test to check whether the issue is real:
@@ -736,8 +736,20 @@ static void piix_set_piomode(struct ata_
(timings[pio][1] << 8);
}
pci_write_config_word(dev, master_port, master_data);
- if (is_slave)
+ if (is_slave) {
+ if (ap->port_no == 0) {
+ u8 tmp = slave_data;
+
+ while (slave_data == tmp) {
+ pci_read_config_byte(dev, slave_port, &tmp);
+ msleep(50);
+ }
+
+ dev_printk(KERN_ERR, &dev->dev, "PATA parallel scan "
+ "race detected\n");
+ }
pci_write_config_byte(dev, slave_port, slave_data);
+ }
/* Ensure the UDMA bit is off - it will be turned back on if
UDMA is selected */
and it indeed triggered the error message.
Lets fix all such races by adding an extra locking to ->set_piomode
and ->set_dmamode methods for PATA controllers.
[ Alan: would be better to take the host lock in libata-core for these
cases so that we fix all the adapters in one swoop. "Looks fine as a
temproary quickfix tho" ]
Cc: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Cc: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-08-30 20:56:30 +08:00
|
|
|
spin_lock_irqsave(&piix_lock, flags);
|
|
|
|
|
2007-05-26 01:16:58 +08:00
|
|
|
/* PIO configuration clears DTE unconditionally. It will be
|
|
|
|
* programmed in set_dmamode which is guaranteed to be called
|
|
|
|
* after set_piomode if any DMA mode is available.
|
|
|
|
*/
|
2005-04-17 06:20:36 +08:00
|
|
|
pci_read_config_word(dev, master_port, &master_data);
|
|
|
|
if (is_slave) {
|
2007-05-26 01:16:58 +08:00
|
|
|
/* clear TIME1|IE1|PPE1|DTE1 */
|
|
|
|
master_data &= 0xff0f;
|
2006-08-30 06:12:40 +08:00
|
|
|
/* enable PPE1, IE1 and TIME1 as needed */
|
|
|
|
master_data |= (control << 4);
|
2005-04-17 06:20:36 +08:00
|
|
|
pci_read_config_byte(dev, slave_port, &slave_data);
|
2006-08-10 15:59:16 +08:00
|
|
|
slave_data &= (ap->port_no ? 0x0f : 0xf0);
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Load the timing nibble for this slave */
|
2007-05-26 01:16:58 +08:00
|
|
|
slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
|
|
|
|
<< (ap->port_no ? 4 : 0);
|
2005-04-17 06:20:36 +08:00
|
|
|
} else {
|
2007-05-26 01:16:58 +08:00
|
|
|
/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
|
|
|
|
master_data &= 0xccf0;
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Enable PPE, IE and TIME as appropriate */
|
|
|
|
master_data |= control;
|
2007-05-26 01:16:58 +08:00
|
|
|
/* load ISP and RCT */
|
2005-04-17 06:20:36 +08:00
|
|
|
master_data |=
|
|
|
|
(timings[pio][0] << 12) |
|
|
|
|
(timings[pio][1] << 8);
|
|
|
|
}
|
2011-10-13 21:28:30 +08:00
|
|
|
|
|
|
|
/* Enable SITRE (separate slave timing register) */
|
|
|
|
master_data |= 0x4000;
|
2005-04-17 06:20:36 +08:00
|
|
|
pci_write_config_word(dev, master_port, master_data);
|
|
|
|
if (is_slave)
|
|
|
|
pci_write_config_byte(dev, slave_port, slave_data);
|
2006-08-30 06:12:40 +08:00
|
|
|
|
|
|
|
/* Ensure the UDMA bit is off - it will be turned back on if
|
|
|
|
UDMA is selected */
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
if (ap->udma_mask) {
|
|
|
|
pci_read_config_byte(dev, 0x48, &udma_enable);
|
|
|
|
udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
|
|
|
|
pci_write_config_byte(dev, 0x48, udma_enable);
|
|
|
|
}
|
ata_piix: parallel scanning on PATA needs an extra locking
Commit log for commit 517d3cc15b36392e518abab6bacbb72089658313
("[libata] ata_piix: Enable parallel scan") says:
This patch turns on parallel scanning for the ata_piix driver.
This driver is used on most netbooks (no AHCI for cheap storage it seems).
The scan is the dominating time factor in the kernel boot for these
devices; with this flag it gets cut in half for the device I used
for testing (eeepc).
Alan took a look at the driver source and concluded that it ought to be safe
to do for this driver. Alan has also checked with the hardware team.
and it is all true but once we put all things together additional
constraints for PATA controllers show up (some hardware registers
have per-host not per-port atomicity) and we risk misprogramming
the controller.
I used the following test to check whether the issue is real:
@@ -736,8 +736,20 @@ static void piix_set_piomode(struct ata_
(timings[pio][1] << 8);
}
pci_write_config_word(dev, master_port, master_data);
- if (is_slave)
+ if (is_slave) {
+ if (ap->port_no == 0) {
+ u8 tmp = slave_data;
+
+ while (slave_data == tmp) {
+ pci_read_config_byte(dev, slave_port, &tmp);
+ msleep(50);
+ }
+
+ dev_printk(KERN_ERR, &dev->dev, "PATA parallel scan "
+ "race detected\n");
+ }
pci_write_config_byte(dev, slave_port, slave_data);
+ }
/* Ensure the UDMA bit is off - it will be turned back on if
UDMA is selected */
and it indeed triggered the error message.
Lets fix all such races by adding an extra locking to ->set_piomode
and ->set_dmamode methods for PATA controllers.
[ Alan: would be better to take the host lock in libata-core for these
cases so that we fix all the adapters in one swoop. "Looks fine as a
temproary quickfix tho" ]
Cc: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Cc: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-08-30 20:56:30 +08:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&piix_lock, flags);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2011-10-13 21:39:10 +08:00
|
|
|
/**
|
|
|
|
* piix_set_piomode - Initialize host controller PATA PIO timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: Drive in question
|
|
|
|
*
|
|
|
|
* Set PIO mode for device, in host controller PCI config space.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
|
|
|
|
{
|
|
|
|
piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/**
|
2006-08-30 06:12:40 +08:00
|
|
|
* do_pata_set_dmamode - Initialize host controller PATA PIO timings
|
2005-04-17 06:20:36 +08:00
|
|
|
* @ap: Port whose timings we are configuring
|
2006-08-30 06:12:40 +08:00
|
|
|
* @adev: Drive in question
|
2006-09-26 04:00:46 +08:00
|
|
|
* @isich: set if the chip is an ICH device
|
2005-04-17 06:20:36 +08:00
|
|
|
*
|
|
|
|
* Set UDMA mode for device, in host controller PCI config space.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2006-08-24 15:19:22 +08:00
|
|
|
struct pci_dev *dev = to_pci_dev(ap->host->dev);
|
ata_piix: parallel scanning on PATA needs an extra locking
Commit log for commit 517d3cc15b36392e518abab6bacbb72089658313
("[libata] ata_piix: Enable parallel scan") says:
This patch turns on parallel scanning for the ata_piix driver.
This driver is used on most netbooks (no AHCI for cheap storage it seems).
The scan is the dominating time factor in the kernel boot for these
devices; with this flag it gets cut in half for the device I used
for testing (eeepc).
Alan took a look at the driver source and concluded that it ought to be safe
to do for this driver. Alan has also checked with the hardware team.
and it is all true but once we put all things together additional
constraints for PATA controllers show up (some hardware registers
have per-host not per-port atomicity) and we risk misprogramming
the controller.
I used the following test to check whether the issue is real:
@@ -736,8 +736,20 @@ static void piix_set_piomode(struct ata_
(timings[pio][1] << 8);
}
pci_write_config_word(dev, master_port, master_data);
- if (is_slave)
+ if (is_slave) {
+ if (ap->port_no == 0) {
+ u8 tmp = slave_data;
+
+ while (slave_data == tmp) {
+ pci_read_config_byte(dev, slave_port, &tmp);
+ msleep(50);
+ }
+
+ dev_printk(KERN_ERR, &dev->dev, "PATA parallel scan "
+ "race detected\n");
+ }
pci_write_config_byte(dev, slave_port, slave_data);
+ }
/* Ensure the UDMA bit is off - it will be turned back on if
UDMA is selected */
and it indeed triggered the error message.
Lets fix all such races by adding an extra locking to ->set_piomode
and ->set_dmamode methods for PATA controllers.
[ Alan: would be better to take the host lock in libata-core for these
cases so that we fix all the adapters in one swoop. "Looks fine as a
temproary quickfix tho" ]
Cc: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Cc: Jeff Garzik <jgarzik@redhat.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-08-30 20:56:30 +08:00
|
|
|
unsigned long flags;
|
2006-08-30 06:12:40 +08:00
|
|
|
u8 speed = adev->dma_mode;
|
|
|
|
int devid = adev->devno + 2 * ap->port_no;
|
2007-01-11 09:20:34 +08:00
|
|
|
u8 udma_enable = 0;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
if (speed >= XFER_UDMA_0) {
|
2011-10-13 21:39:10 +08:00
|
|
|
unsigned int udma = speed - XFER_UDMA_0;
|
2006-08-30 06:12:40 +08:00
|
|
|
u16 udma_timing;
|
|
|
|
u16 ideconf;
|
|
|
|
int u_clock, u_speed;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2011-10-13 21:39:10 +08:00
|
|
|
spin_lock_irqsave(&piix_lock, flags);
|
|
|
|
|
|
|
|
pci_read_config_byte(dev, 0x48, &udma_enable);
|
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/*
|
2007-10-19 18:42:56 +08:00
|
|
|
* UDMA is handled by a combination of clock switching and
|
2006-08-31 12:03:49 +08:00
|
|
|
* selection of dividers
|
|
|
|
*
|
2006-08-30 06:12:40 +08:00
|
|
|
* Handy rule: Odd modes are UDMATIMx 01, even are 02
|
2006-08-31 12:03:49 +08:00
|
|
|
* except UDMA0 which is 00
|
2006-08-30 06:12:40 +08:00
|
|
|
*/
|
|
|
|
u_speed = min(2 - (udma & 1), udma);
|
|
|
|
if (udma == 5)
|
|
|
|
u_clock = 0x1000; /* 100Mhz */
|
|
|
|
else if (udma > 2)
|
|
|
|
u_clock = 1; /* 66Mhz */
|
|
|
|
else
|
|
|
|
u_clock = 0; /* 33Mhz */
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
udma_enable |= (1 << devid);
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Load the CT/RP selection */
|
|
|
|
pci_read_config_word(dev, 0x4A, &udma_timing);
|
|
|
|
udma_timing &= ~(3 << (4 * devid));
|
|
|
|
udma_timing |= u_speed << (4 * devid);
|
|
|
|
pci_write_config_word(dev, 0x4A, udma_timing);
|
|
|
|
|
2006-08-31 12:03:49 +08:00
|
|
|
if (isich) {
|
2006-08-30 06:12:40 +08:00
|
|
|
/* Select a 33/66/100Mhz clock */
|
|
|
|
pci_read_config_word(dev, 0x54, &ideconf);
|
|
|
|
ideconf &= ~(0x1001 << devid);
|
|
|
|
ideconf |= u_clock << devid;
|
|
|
|
/* For ICH or later we should set bit 10 for better
|
|
|
|
performance (WR_PingPong_En) */
|
|
|
|
pci_write_config_word(dev, 0x54, ideconf);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2011-10-13 21:39:10 +08:00
|
|
|
|
|
|
|
pci_write_config_byte(dev, 0x48, udma_enable);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&piix_lock, flags);
|
2005-04-17 06:20:36 +08:00
|
|
|
} else {
|
2011-10-13 21:39:10 +08:00
|
|
|
/* MWDMA is driven by the PIO timings. */
|
|
|
|
unsigned int mwdma = speed - XFER_MW_DMA_0;
|
2006-08-30 06:12:40 +08:00
|
|
|
const unsigned int needed_pio[3] = {
|
|
|
|
XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
|
|
|
|
};
|
|
|
|
int pio = needed_pio[mwdma] - XFER_PIO_0;
|
2006-08-31 12:03:49 +08:00
|
|
|
|
2011-10-13 21:39:10 +08:00
|
|
|
/* XFER_PIO_0 is never used currently */
|
|
|
|
piix_set_timings(ap, adev, pio);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
2006-08-30 06:12:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* piix_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: um
|
|
|
|
*
|
|
|
|
* Set MW/UDMA mode for device, in host controller PCI config space.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
|
|
|
do_pata_set_dmamode(ap, adev, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* ich_set_dmamode - Initialize host controller PATA DMA timings
|
|
|
|
* @ap: Port whose timings we are configuring
|
|
|
|
* @adev: um
|
|
|
|
*
|
|
|
|
* Set MW/UDMA mode for device, in host controller PCI config space.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* None (inherited from caller).
|
|
|
|
*/
|
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
|
2006-08-30 06:12:40 +08:00
|
|
|
{
|
|
|
|
do_pata_set_dmamode(ap, adev, 1);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2008-01-18 17:36:30 +08:00
|
|
|
/*
|
|
|
|
* Serial ATA Index/Data Pair Superset Registers access
|
|
|
|
*
|
|
|
|
* Beginning from ICH8, there's a sane way to access SCRs using index
|
2008-07-31 16:02:44 +08:00
|
|
|
* and data register pair located at BAR5 which means that we have
|
|
|
|
* separate SCRs for master and slave. This is handled using libata
|
|
|
|
* slave_link facility.
|
2008-01-18 17:36:30 +08:00
|
|
|
*/
|
|
|
|
static const int piix_sidx_map[] = {
|
|
|
|
[SCR_STATUS] = 0,
|
|
|
|
[SCR_ERROR] = 2,
|
|
|
|
[SCR_CONTROL] = 1,
|
|
|
|
};
|
|
|
|
|
2008-07-31 16:02:44 +08:00
|
|
|
static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
|
2008-01-18 17:36:30 +08:00
|
|
|
{
|
2008-07-31 16:02:44 +08:00
|
|
|
struct ata_port *ap = link->ap;
|
2008-01-18 17:36:30 +08:00
|
|
|
struct piix_host_priv *hpriv = ap->host->private_data;
|
|
|
|
|
2008-07-31 16:02:44 +08:00
|
|
|
iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
|
2008-01-18 17:36:30 +08:00
|
|
|
hpriv->sidpr + PIIX_SIDPR_IDX);
|
|
|
|
}
|
|
|
|
|
2008-07-31 16:02:40 +08:00
|
|
|
static int piix_sidpr_scr_read(struct ata_link *link,
|
|
|
|
unsigned int reg, u32 *val)
|
2008-01-18 17:36:30 +08:00
|
|
|
{
|
2008-07-31 16:02:44 +08:00
|
|
|
struct piix_host_priv *hpriv = link->ap->host->private_data;
|
2008-01-18 17:36:30 +08:00
|
|
|
|
|
|
|
if (reg >= ARRAY_SIZE(piix_sidx_map))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2008-07-31 16:02:44 +08:00
|
|
|
piix_sidpr_sel(link, reg);
|
|
|
|
*val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
|
2008-01-18 17:36:30 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-07-31 16:02:40 +08:00
|
|
|
static int piix_sidpr_scr_write(struct ata_link *link,
|
|
|
|
unsigned int reg, u32 val)
|
2008-01-18 17:36:30 +08:00
|
|
|
{
|
2008-07-31 16:02:44 +08:00
|
|
|
struct piix_host_priv *hpriv = link->ap->host->private_data;
|
2008-07-31 16:02:40 +08:00
|
|
|
|
2008-01-18 17:36:30 +08:00
|
|
|
if (reg >= ARRAY_SIZE(piix_sidx_map))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2008-07-31 16:02:44 +08:00
|
|
|
piix_sidpr_sel(link, reg);
|
|
|
|
iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
|
2008-01-18 17:36:30 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-09-01 23:50:08 +08:00
|
|
|
static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
|
|
|
|
unsigned hints)
|
|
|
|
{
|
|
|
|
return sata_link_scr_lpm(link, policy, false);
|
|
|
|
}
|
|
|
|
|
2010-01-19 09:49:19 +08:00
|
|
|
static bool piix_irq_check(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
if (unlikely(!ap->ioaddr.bmdma_addr))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
|
|
|
|
}
|
|
|
|
|
2007-07-10 14:55:43 +08:00
|
|
|
#ifdef CONFIG_PM
|
2007-07-27 13:53:28 +08:00
|
|
|
static int piix_broken_suspend(void)
|
|
|
|
{
|
2007-10-04 03:15:40 +08:00
|
|
|
static const struct dmi_system_id sysids[] = {
|
2007-09-30 16:11:20 +08:00
|
|
|
{
|
|
|
|
.ident = "TECRA M3",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
|
|
|
|
},
|
|
|
|
},
|
2007-11-30 14:28:29 +08:00
|
|
|
{
|
|
|
|
.ident = "TECRA M3",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
|
|
|
|
},
|
|
|
|
},
|
2007-12-05 09:39:49 +08:00
|
|
|
{
|
|
|
|
.ident = "TECRA M4",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
|
|
|
|
},
|
|
|
|
},
|
2008-06-13 17:05:02 +08:00
|
|
|
{
|
|
|
|
.ident = "TECRA M4",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
|
|
|
|
},
|
|
|
|
},
|
2007-07-27 13:53:28 +08:00
|
|
|
{
|
|
|
|
.ident = "TECRA M5",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
|
|
|
|
},
|
2007-07-10 14:55:43 +08:00
|
|
|
},
|
2008-01-17 21:08:55 +08:00
|
|
|
{
|
|
|
|
.ident = "TECRA M6",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
|
|
|
|
},
|
|
|
|
},
|
2007-08-14 18:56:04 +08:00
|
|
|
{
|
|
|
|
.ident = "TECRA M7",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
|
|
|
|
},
|
|
|
|
},
|
2007-11-30 14:28:29 +08:00
|
|
|
{
|
|
|
|
.ident = "TECRA A8",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
|
|
|
|
},
|
|
|
|
},
|
2008-01-17 21:08:55 +08:00
|
|
|
{
|
|
|
|
.ident = "Satellite R20",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
|
|
|
|
},
|
|
|
|
},
|
2007-11-30 14:28:29 +08:00
|
|
|
{
|
|
|
|
.ident = "Satellite R25",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
|
|
|
|
},
|
|
|
|
},
|
2007-08-25 07:31:02 +08:00
|
|
|
{
|
|
|
|
.ident = "Satellite U200",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
|
|
|
|
},
|
|
|
|
},
|
2007-11-30 14:28:29 +08:00
|
|
|
{
|
|
|
|
.ident = "Satellite U200",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
|
|
|
|
},
|
|
|
|
},
|
2007-11-07 11:02:27 +08:00
|
|
|
{
|
|
|
|
.ident = "Satellite Pro U200",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
|
|
|
|
},
|
|
|
|
},
|
2007-07-27 13:53:28 +08:00
|
|
|
{
|
|
|
|
.ident = "Satellite U205",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
|
|
|
|
},
|
2007-07-10 14:55:43 +08:00
|
|
|
},
|
2007-11-12 16:56:24 +08:00
|
|
|
{
|
|
|
|
.ident = "SATELLITE U205",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
|
|
|
|
},
|
|
|
|
},
|
2012-01-08 07:39:10 +08:00
|
|
|
{
|
|
|
|
.ident = "Satellite Pro A120",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
|
|
|
|
},
|
|
|
|
},
|
2007-07-27 13:53:28 +08:00
|
|
|
{
|
|
|
|
.ident = "Portege M500",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
|
|
|
|
},
|
2007-07-10 14:55:43 +08:00
|
|
|
},
|
2009-03-31 09:44:34 +08:00
|
|
|
{
|
|
|
|
.ident = "VGN-BX297XP",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
|
|
|
|
},
|
|
|
|
},
|
2007-09-01 18:48:52 +08:00
|
|
|
|
|
|
|
{ } /* terminate list */
|
2007-07-27 13:53:28 +08:00
|
|
|
};
|
2007-07-27 13:55:07 +08:00
|
|
|
static const char *oemstrs[] = {
|
|
|
|
"Tecra M3,",
|
|
|
|
};
|
|
|
|
int i;
|
2007-07-27 13:53:28 +08:00
|
|
|
|
|
|
|
if (dmi_check_system(sysids))
|
|
|
|
return 1;
|
|
|
|
|
2007-07-27 13:55:07 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
|
|
|
|
if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
|
|
|
|
return 1;
|
|
|
|
|
2008-11-29 21:37:21 +08:00
|
|
|
/* TECRA M4 sometimes forgets its identify and reports bogus
|
|
|
|
* DMI information. As the bogus information is a bit
|
|
|
|
* generic, match as many entries as possible. This manual
|
|
|
|
* matching is necessary because dmi_system_id.matches is
|
|
|
|
* limited to four entries.
|
|
|
|
*/
|
2008-12-10 21:07:22 +08:00
|
|
|
if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
|
|
|
|
dmi_match(DMI_PRODUCT_NAME, "000000") &&
|
|
|
|
dmi_match(DMI_PRODUCT_VERSION, "000000") &&
|
|
|
|
dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
|
|
|
|
dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
|
|
|
|
dmi_match(DMI_BOARD_NAME, "Portable PC") &&
|
|
|
|
dmi_match(DMI_BOARD_VERSION, "Version A0"))
|
2008-11-29 21:37:21 +08:00
|
|
|
return 1;
|
|
|
|
|
2007-07-27 13:53:28 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2007-07-10 14:55:43 +08:00
|
|
|
|
|
|
|
static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
|
|
|
|
{
|
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
|
|
|
unsigned long flags;
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
rc = ata_host_suspend(host, mesg);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
/* Some braindamaged ACPI suspend implementations expect the
|
|
|
|
* controller to be awake on entry; otherwise, it burns cpu
|
|
|
|
* cycles and power trying to do something to the sleeping
|
|
|
|
* beauty.
|
|
|
|
*/
|
2008-02-24 02:13:25 +08:00
|
|
|
if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
|
2007-07-10 14:55:43 +08:00
|
|
|
pci_save_state(pdev);
|
|
|
|
|
|
|
|
/* mark its power state as "unknown", since we don't
|
|
|
|
* know if e.g. the BIOS will change its device state
|
|
|
|
* when we suspend.
|
|
|
|
*/
|
|
|
|
if (pdev->current_state == PCI_D0)
|
|
|
|
pdev->current_state = PCI_UNKNOWN;
|
|
|
|
|
|
|
|
/* tell resume that it's waking up from broken suspend */
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
host->flags |= PIIX_HOST_BROKEN_SUSPEND;
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
} else
|
|
|
|
ata_pci_device_do_suspend(pdev, mesg);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int piix_pci_device_resume(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
|
|
|
unsigned long flags;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
|
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
|
|
pci_restore_state(pdev);
|
|
|
|
|
|
|
|
/* PCI device wasn't disabled during suspend. Use
|
2007-07-27 13:43:35 +08:00
|
|
|
* pci_reenable_device() to avoid affecting the enable
|
|
|
|
* count.
|
2007-07-10 14:55:43 +08:00
|
|
|
*/
|
2007-07-27 13:43:35 +08:00
|
|
|
rc = pci_reenable_device(pdev);
|
2007-07-10 14:55:43 +08:00
|
|
|
if (rc)
|
2011-04-16 06:51:58 +08:00
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"failed to enable device after resume (%d)\n",
|
|
|
|
rc);
|
2007-07-10 14:55:43 +08:00
|
|
|
} else
|
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
|
|
|
|
|
|
if (rc == 0)
|
|
|
|
ata_host_resume(host);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2008-01-07 18:38:53 +08:00
|
|
|
static u8 piix_vmw_bmdma_status(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
#define AHCI_PCI_BAR 5
|
|
|
|
#define AHCI_GLOBAL_CTL 0x04
|
|
|
|
#define AHCI_ENABLE (1 << 31)
|
|
|
|
static int piix_disable_ahci(struct pci_dev *pdev)
|
|
|
|
{
|
2005-08-30 17:18:18 +08:00
|
|
|
void __iomem *mmio;
|
2005-04-17 06:20:36 +08:00
|
|
|
u32 tmp;
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
/* BUG: pci_enable_device has not yet been called. This
|
|
|
|
* works because this device is usually set up by BIOS.
|
|
|
|
*/
|
|
|
|
|
2005-08-30 17:42:52 +08:00
|
|
|
if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
|
|
|
|
!pci_resource_len(pdev, AHCI_PCI_BAR))
|
2005-04-17 06:20:36 +08:00
|
|
|
return 0;
|
2005-07-29 03:54:15 +08:00
|
|
|
|
2005-08-30 17:42:52 +08:00
|
|
|
mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (!mmio)
|
|
|
|
return -ENOMEM;
|
2005-07-29 03:54:15 +08:00
|
|
|
|
2007-11-19 22:28:28 +08:00
|
|
|
tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (tmp & AHCI_ENABLE) {
|
|
|
|
tmp &= ~AHCI_ENABLE;
|
2007-11-19 22:28:28 +08:00
|
|
|
iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-11-19 22:28:28 +08:00
|
|
|
tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (tmp & AHCI_ENABLE)
|
|
|
|
rc = -EIO;
|
|
|
|
}
|
2005-07-29 03:54:15 +08:00
|
|
|
|
2005-08-30 17:42:52 +08:00
|
|
|
pci_iounmap(pdev, mmio);
|
2005-04-17 06:20:36 +08:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2005-12-09 03:22:28 +08:00
|
|
|
/**
|
|
|
|
* piix_check_450nx_errata - Check for problem 450NX setup
|
2006-01-29 02:15:32 +08:00
|
|
|
* @ata_dev: the PCI device to check
|
2006-03-24 22:56:57 +08:00
|
|
|
*
|
2005-12-09 03:22:28 +08:00
|
|
|
* Check for the present of 450NX errata #19 and errata #25. If
|
|
|
|
* they are found return an error code so we can turn off DMA
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = NULL;
|
|
|
|
u16 cfg;
|
|
|
|
int no_piix_dma = 0;
|
2006-03-24 22:56:57 +08:00
|
|
|
|
2007-10-19 18:42:56 +08:00
|
|
|
while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
|
2005-12-09 03:22:28 +08:00
|
|
|
/* Look for 450NX PXB. Check for problem configurations
|
|
|
|
A PCI quirk checks bit 6 already */
|
|
|
|
pci_read_config_word(pdev, 0x41, &cfg);
|
|
|
|
/* Only on the original revision: IDE DMA can hang */
|
2007-06-09 06:46:36 +08:00
|
|
|
if (pdev->revision == 0x00)
|
2005-12-09 03:22:28 +08:00
|
|
|
no_piix_dma = 1;
|
|
|
|
/* On all revisions below 5 PXB bus lock must be disabled for IDE */
|
2007-06-09 06:46:36 +08:00
|
|
|
else if (cfg & (1<<14) && pdev->revision < 5)
|
2005-12-09 03:22:28 +08:00
|
|
|
no_piix_dma = 2;
|
|
|
|
}
|
2006-05-23 05:58:14 +08:00
|
|
|
if (no_piix_dma)
|
2011-04-16 06:51:58 +08:00
|
|
|
dev_warn(&ata_dev->dev,
|
|
|
|
"450NX errata present, disabling IDE DMA%s\n",
|
|
|
|
no_piix_dma == 2 ? " - a BIOS update may resolve this"
|
|
|
|
: "");
|
|
|
|
|
2005-12-09 03:22:28 +08:00
|
|
|
return no_piix_dma;
|
2006-03-24 22:56:57 +08:00
|
|
|
}
|
2005-12-09 03:22:28 +08:00
|
|
|
|
2008-01-18 17:36:29 +08:00
|
|
|
static void __devinit piix_init_pcs(struct ata_host *host,
|
2006-07-11 23:48:50 +08:00
|
|
|
const struct piix_map_db *map_db)
|
|
|
|
{
|
2008-01-18 17:36:29 +08:00
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
2006-07-11 23:48:50 +08:00
|
|
|
u16 pcs, new_pcs;
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, ICH5_PCS, &pcs);
|
|
|
|
|
|
|
|
new_pcs = pcs | map_db->port_enable;
|
|
|
|
|
|
|
|
if (new_pcs != pcs) {
|
|
|
|
DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
|
|
|
|
pci_write_config_word(pdev, ICH5_PCS, new_pcs);
|
|
|
|
msleep(150);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-01-18 17:36:29 +08:00
|
|
|
static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
|
|
|
|
struct ata_port_info *pinfo,
|
|
|
|
const struct piix_map_db *map_db)
|
2006-03-01 00:25:39 +08:00
|
|
|
{
|
2007-10-15 02:35:40 +08:00
|
|
|
const int *map;
|
2006-03-01 00:25:39 +08:00
|
|
|
int i, invalid_map = 0;
|
|
|
|
u8 map_value;
|
|
|
|
|
|
|
|
pci_read_config_byte(pdev, ICH5_PMR, &map_value);
|
|
|
|
|
|
|
|
map = map_db->map[map_value & map_db->mask];
|
|
|
|
|
2011-04-16 06:51:58 +08:00
|
|
|
dev_info(&pdev->dev, "MAP [");
|
2006-03-01 00:25:39 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
switch (map[i]) {
|
|
|
|
case RV:
|
|
|
|
invalid_map = 1;
|
2011-04-16 06:51:58 +08:00
|
|
|
pr_cont(" XX");
|
2006-03-01 00:25:39 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case NA:
|
2011-04-16 06:51:58 +08:00
|
|
|
pr_cont(" --");
|
2006-03-01 00:25:39 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
case IDE:
|
|
|
|
WARN_ON((i & 1) || map[i + 1] != IDE);
|
2006-08-30 06:12:40 +08:00
|
|
|
pinfo[i / 2] = piix_port_info[ich_pata_100];
|
2006-03-01 00:25:39 +08:00
|
|
|
i++;
|
2011-04-16 06:51:58 +08:00
|
|
|
pr_cont(" IDE IDE");
|
2006-03-01 00:25:39 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
2011-04-16 06:51:58 +08:00
|
|
|
pr_cont(" P%d", map[i]);
|
2006-03-01 00:25:39 +08:00
|
|
|
if (i & 1)
|
2006-08-24 15:19:22 +08:00
|
|
|
pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
|
2006-03-01 00:25:39 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2011-04-16 06:51:58 +08:00
|
|
|
pr_cont(" ]\n");
|
2006-03-01 00:25:39 +08:00
|
|
|
|
|
|
|
if (invalid_map)
|
2011-04-16 06:51:58 +08:00
|
|
|
dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
|
2006-03-01 00:25:39 +08:00
|
|
|
|
2008-01-18 17:36:29 +08:00
|
|
|
return map;
|
2006-03-01 00:25:39 +08:00
|
|
|
}
|
|
|
|
|
2009-03-03 12:52:16 +08:00
|
|
|
static bool piix_no_sidpr(struct ata_host *host)
|
|
|
|
{
|
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Samsung DB-P70 only has three ATA ports exposed and
|
|
|
|
* curiously the unconnected first port reports link online
|
|
|
|
* while not responding to SRST protocol causing excessive
|
|
|
|
* detection delay.
|
|
|
|
*
|
|
|
|
* Unfortunately, the system doesn't carry enough DMI
|
|
|
|
* information to identify the machine but does have subsystem
|
|
|
|
* vendor and device set. As it's unclear whether the
|
|
|
|
* subsystem vendor/device is used only for this specific
|
|
|
|
* board, the port can't be disabled solely with the
|
|
|
|
* information; however, turning off SIDPR access works around
|
|
|
|
* the problem. Turn it off.
|
|
|
|
*
|
|
|
|
* This problem is reported in bnc#441240.
|
|
|
|
*
|
|
|
|
* https://bugzilla.novell.com/show_bug.cgi?id=441420
|
|
|
|
*/
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
|
|
|
|
pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
|
|
|
|
pdev->subsystem_device == 0xb049) {
|
2011-04-16 06:51:58 +08:00
|
|
|
dev_warn(host->dev,
|
|
|
|
"Samsung DB-P70 detected, disabling SIDPR\n");
|
2009-03-03 12:52:16 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2008-07-31 16:02:44 +08:00
|
|
|
static int __devinit piix_init_sidpr(struct ata_host *host)
|
2008-01-18 17:36:30 +08:00
|
|
|
{
|
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
|
|
|
struct piix_host_priv *hpriv = host->private_data;
|
2008-07-31 16:02:44 +08:00
|
|
|
struct ata_link *link0 = &host->ports[0]->link;
|
2008-05-01 09:03:08 +08:00
|
|
|
u32 scontrol;
|
2008-07-31 16:02:44 +08:00
|
|
|
int i, rc;
|
2008-01-18 17:36:30 +08:00
|
|
|
|
|
|
|
/* check for availability */
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
if (hpriv->map[i] == IDE)
|
2008-07-31 16:02:44 +08:00
|
|
|
return 0;
|
2008-01-18 17:36:30 +08:00
|
|
|
|
2009-03-03 12:52:16 +08:00
|
|
|
/* is it blacklisted? */
|
|
|
|
if (piix_no_sidpr(host))
|
|
|
|
return 0;
|
|
|
|
|
2008-01-18 17:36:30 +08:00
|
|
|
if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
|
2008-07-31 16:02:44 +08:00
|
|
|
return 0;
|
2008-01-18 17:36:30 +08:00
|
|
|
|
|
|
|
if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
|
|
|
|
pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
|
2008-07-31 16:02:44 +08:00
|
|
|
return 0;
|
2008-01-18 17:36:30 +08:00
|
|
|
|
|
|
|
if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
|
2008-07-31 16:02:44 +08:00
|
|
|
return 0;
|
2008-01-18 17:36:30 +08:00
|
|
|
|
|
|
|
hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
|
2008-05-01 09:03:08 +08:00
|
|
|
|
|
|
|
/* SCR access via SIDPR doesn't work on some configurations.
|
|
|
|
* Give it a test drive by inhibiting power save modes which
|
|
|
|
* we'll do anyway.
|
|
|
|
*/
|
2008-07-31 16:02:44 +08:00
|
|
|
piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
|
2008-05-01 09:03:08 +08:00
|
|
|
|
|
|
|
/* if IPM is already 3, SCR access is probably working. Don't
|
|
|
|
* un-inhibit power save modes as BIOS might have inhibited
|
|
|
|
* them for a reason.
|
|
|
|
*/
|
|
|
|
if ((scontrol & 0xf00) != 0x300) {
|
|
|
|
scontrol |= 0x300;
|
2008-07-31 16:02:44 +08:00
|
|
|
piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
|
|
|
|
piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
|
2008-05-01 09:03:08 +08:00
|
|
|
|
|
|
|
if ((scontrol & 0xf00) != 0x300) {
|
2011-04-16 06:51:58 +08:00
|
|
|
dev_info(host->dev,
|
|
|
|
"SCR access via SIDPR is available but doesn't work\n");
|
2008-07-31 16:02:44 +08:00
|
|
|
return 0;
|
2008-05-01 09:03:08 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-31 16:02:44 +08:00
|
|
|
/* okay, SCRs available, set ops and ask libata for slave_link */
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
struct ata_port *ap = host->ports[i];
|
|
|
|
|
|
|
|
ap->ops = &piix_sidpr_sata_ops;
|
|
|
|
|
|
|
|
if (ap->flags & ATA_FLAG_SLAVE_POSS) {
|
|
|
|
rc = ata_slave_link_init(ap);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2008-01-18 17:36:30 +08:00
|
|
|
}
|
|
|
|
|
2009-01-02 11:04:48 +08:00
|
|
|
static void piix_iocfg_bit18_quirk(struct ata_host *host)
|
2007-08-23 09:15:18 +08:00
|
|
|
{
|
2007-10-04 03:15:40 +08:00
|
|
|
static const struct dmi_system_id sysids[] = {
|
2007-08-23 09:15:18 +08:00
|
|
|
{
|
|
|
|
/* Clevo M570U sets IOCFG bit 18 if the cdrom
|
|
|
|
* isn't used to boot the system which
|
|
|
|
* disables the channel.
|
|
|
|
*/
|
|
|
|
.ident = "M570U",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
|
|
|
|
},
|
|
|
|
},
|
2007-09-01 18:48:52 +08:00
|
|
|
|
|
|
|
{ } /* terminate list */
|
2007-08-23 09:15:18 +08:00
|
|
|
};
|
2009-01-02 11:04:48 +08:00
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
|
|
|
struct piix_host_priv *hpriv = host->private_data;
|
2007-08-23 09:15:18 +08:00
|
|
|
|
|
|
|
if (!dmi_check_system(sysids))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* The datasheet says that bit 18 is NOOP but certain systems
|
|
|
|
* seem to use it to disable a channel. Clear the bit on the
|
|
|
|
* affected systems.
|
|
|
|
*/
|
2009-01-02 11:04:48 +08:00
|
|
|
if (hpriv->saved_iocfg & (1 << 18)) {
|
2011-04-16 06:51:58 +08:00
|
|
|
dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
|
2009-01-02 11:04:48 +08:00
|
|
|
pci_write_config_dword(pdev, PIIX_IOCFG,
|
|
|
|
hpriv->saved_iocfg & ~(1 << 18));
|
2007-08-23 09:15:18 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-01-20 03:59:22 +08:00
|
|
|
static bool piix_broken_system_poweroff(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
static const struct dmi_system_id broken_systems[] = {
|
|
|
|
{
|
|
|
|
.ident = "HP Compaq 2510p",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
|
|
|
|
},
|
|
|
|
/* PCI slot number of the controller */
|
|
|
|
.driver_data = (void *)0x1FUL,
|
|
|
|
},
|
2009-05-19 06:37:44 +08:00
|
|
|
{
|
|
|
|
.ident = "HP Compaq nc6000",
|
|
|
|
.matches = {
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
|
|
|
|
},
|
|
|
|
/* PCI slot number of the controller */
|
|
|
|
.driver_data = (void *)0x1FUL,
|
|
|
|
},
|
2009-01-20 03:59:22 +08:00
|
|
|
|
|
|
|
{ } /* terminate list */
|
|
|
|
};
|
|
|
|
const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
|
|
|
|
|
|
|
|
if (dmi) {
|
|
|
|
unsigned long slot = (unsigned long)dmi->driver_data;
|
|
|
|
/* apply the quirk only to on-board controllers */
|
|
|
|
return slot == PCI_SLOT(pdev->devfn);
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/**
|
|
|
|
* piix_init_one - Register PIIX ATA PCI device with kernel services
|
|
|
|
* @pdev: PCI device to register
|
|
|
|
* @ent: Entry in piix_pci_tbl matching with @pdev
|
|
|
|
*
|
|
|
|
* Called from kernel PCI layer. We probe for combined mode (sigh),
|
|
|
|
* and then hand over control to libata, for it to do the rest.
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* Inherited from PCI layer (may sleep).
|
|
|
|
*
|
|
|
|
* RETURNS:
|
|
|
|
* Zero on success, or -ERRNO value.
|
|
|
|
*/
|
|
|
|
|
2008-01-31 04:02:02 +08:00
|
|
|
static int __devinit piix_init_one(struct pci_dev *pdev,
|
|
|
|
const struct pci_device_id *ent)
|
2005-04-17 06:20:36 +08:00
|
|
|
{
|
2007-01-20 15:00:28 +08:00
|
|
|
struct device *dev = &pdev->dev;
|
2006-03-01 00:25:39 +08:00
|
|
|
struct ata_port_info port_info[2];
|
2007-05-04 18:43:58 +08:00
|
|
|
const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
|
2010-09-01 23:50:08 +08:00
|
|
|
struct scsi_host_template *sht = &piix_sht;
|
2006-08-24 15:19:22 +08:00
|
|
|
unsigned long port_flags;
|
2008-01-18 17:36:29 +08:00
|
|
|
struct ata_host *host;
|
|
|
|
struct piix_host_priv *hpriv;
|
|
|
|
int rc;
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2011-04-16 06:52:00 +08:00
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2009-05-07 00:10:08 +08:00
|
|
|
/* no hotplugging support for later devices (FIXME) */
|
|
|
|
if (!in_module_init && ent->driver_data >= ich5_sata)
|
2005-04-17 06:20:36 +08:00
|
|
|
return -ENODEV;
|
|
|
|
|
2009-01-20 03:59:22 +08:00
|
|
|
if (piix_broken_system_poweroff(pdev)) {
|
|
|
|
piix_port_info[ent->driver_data].flags |=
|
|
|
|
ATA_FLAG_NO_POWEROFF_SPINDOWN |
|
|
|
|
ATA_FLAG_NO_HIBERNATE_SPINDOWN;
|
|
|
|
dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
|
|
|
|
"on poweroff and hibernation\n");
|
|
|
|
}
|
|
|
|
|
2008-01-18 17:36:29 +08:00
|
|
|
port_info[0] = piix_port_info[ent->driver_data];
|
|
|
|
port_info[1] = piix_port_info[ent->driver_data];
|
|
|
|
|
|
|
|
port_flags = port_info[0].flags;
|
|
|
|
|
|
|
|
/* enable device and prepare host */
|
|
|
|
rc = pcim_enable_device(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2009-01-02 11:04:48 +08:00
|
|
|
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
|
|
|
|
if (!hpriv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
/* Save IOCFG, this will be used for cable detection, quirk
|
|
|
|
* detection and restoration on detach. This is necessary
|
|
|
|
* because some ACPI implementations mess up cable related
|
|
|
|
* bits on _STM. Reported on kernel bz#11879.
|
|
|
|
*/
|
|
|
|
pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
|
|
|
|
|
2008-03-26 14:46:58 +08:00
|
|
|
/* ICH6R may be driven by either ata_piix or ahci driver
|
|
|
|
* regardless of BIOS configuration. Make sure AHCI mode is
|
|
|
|
* off.
|
|
|
|
*/
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
|
2008-09-09 00:31:39 +08:00
|
|
|
rc = piix_disable_ahci(pdev);
|
2008-03-26 14:46:58 +08:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2008-01-18 17:36:29 +08:00
|
|
|
/* SATA map init can change port_info, do it before prepping host */
|
|
|
|
if (port_flags & ATA_FLAG_SATA)
|
|
|
|
hpriv->map = piix_init_sata_map(pdev, port_info,
|
|
|
|
piix_map_db_table[ent->driver_data]);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2010-05-20 04:10:22 +08:00
|
|
|
rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
|
2008-01-18 17:36:29 +08:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
host->private_data = hpriv;
|
[PATCH] ata_piix: fix MAP VALUE interpretation for for ICH6/7
Unlike their older siblings, ICH6 and 7 use different scheme for MAP
VALUE. This patch makes ata_piix interpret MV properly on ICH6/7.
Pre-ICH6/7
The value of these bits indicate the address range the SATA port
responds to, and whether or not the SATA and IDE functions are
combined.
000 = Non-combined. P0 is primary master. P1 is secondary master.
001 = Non-combined. P0 is secondary master. P1 is primary master.
100 = Combined. P0 is primary master. P1 is primary slave. P-ATA is
2:0 Map Value secondary.
101 = Combined. P0 is primary slave. P1 is primary master. P-ATA is
secondary.
110 = Combined. P-ATA is primary. P0 is secondary master. P1 is
secondary slave.
111 = Combined. P-ATA is primary. P0 is secondary slave. P1 is
secondary master.
ICH6/7
Map Value - R/W. Map Value (MV): The value in the bits below indicate
the address range the SATA ports responds to, and whether or not the
PATA and SATA functions are combined. When in combined mode, the AHCI
memory space is not available and AHCI may not be used.
00 = Non-combined. P0 is primary master, P2 is the primary slave. P1
is secondary master, P3 is the 1:0 secondary slave (desktop
only). P0 is primary master, P2 is the primary slave (mobile
only).
01 = Combined. IDE is primary. P1 is secondary master, P3 is the
secondary slave. (desktop only)
10 = Combined. P0 is primary master. P2 is primary slave. IDE is secondary
11 = Reserved
Signed-off-by: Tejun Heo <htejun@gmail.com>
--
Jeff, without this patch, ata_piix misdetects my ICH7's combined mode,
ending up not applying bridge limits to PX-710SA and configuring IDE
drive on 40-c cable to UDMA/66.
Thanks.
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
2005-12-18 16:17:07 +08:00
|
|
|
|
2008-01-18 17:36:29 +08:00
|
|
|
/* initialize controller */
|
2008-01-18 17:36:30 +08:00
|
|
|
if (port_flags & ATA_FLAG_SATA) {
|
2008-01-18 17:36:29 +08:00
|
|
|
piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
|
2008-07-31 16:02:44 +08:00
|
|
|
rc = piix_init_sidpr(host);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2010-09-01 23:50:08 +08:00
|
|
|
if (host->ports[0]->ops == &piix_sidpr_sata_ops)
|
|
|
|
sht = &piix_sidpr_sht;
|
2008-01-18 17:36:30 +08:00
|
|
|
}
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2007-08-23 09:15:18 +08:00
|
|
|
/* apply IOCFG bit18 quirk */
|
2009-01-02 11:04:48 +08:00
|
|
|
piix_iocfg_bit18_quirk(host);
|
2007-08-23 09:15:18 +08:00
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
/* On ICH5, some BIOSen disable the interrupt using the
|
|
|
|
* PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
|
|
|
|
* On ICH6, this bit has the same effect, but only when
|
|
|
|
* MSI is disabled (and it is disabled, as we don't use
|
|
|
|
* message-signalled interrupts currently).
|
|
|
|
*/
|
2006-08-24 15:19:22 +08:00
|
|
|
if (port_flags & PIIX_FLAG_CHECKINTR)
|
2005-08-16 03:23:41 +08:00
|
|
|
pci_intx(pdev, 1);
|
2005-04-17 06:20:36 +08:00
|
|
|
|
2005-12-09 03:22:28 +08:00
|
|
|
if (piix_check_450nx_errata(pdev)) {
|
|
|
|
/* This writes into the master table but it does not
|
|
|
|
really matter for this errata as we will apply it to
|
|
|
|
all the PIIX devices on the board */
|
2008-01-18 17:36:29 +08:00
|
|
|
host->ports[0]->mwdma_mask = 0;
|
|
|
|
host->ports[0]->udma_mask = 0;
|
|
|
|
host->ports[1]->mwdma_mask = 0;
|
|
|
|
host->ports[1]->udma_mask = 0;
|
2005-12-09 03:22:28 +08:00
|
|
|
}
|
2009-05-13 22:02:42 +08:00
|
|
|
host->flags |= ATA_HOST_PARALLEL_SCAN;
|
2008-01-18 17:36:29 +08:00
|
|
|
|
|
|
|
pci_set_master(pdev);
|
2010-09-01 23:50:08 +08:00
|
|
|
return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
|
2005-04-17 06:20:36 +08:00
|
|
|
}
|
|
|
|
|
2009-01-02 11:04:48 +08:00
|
|
|
static void piix_remove_one(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
|
|
|
struct piix_host_priv *hpriv = host->private_data;
|
|
|
|
|
|
|
|
pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
|
|
|
|
|
|
|
|
ata_pci_remove_one(pdev);
|
|
|
|
}
|
|
|
|
|
2005-04-17 06:20:36 +08:00
|
|
|
static int __init piix_init(void)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
2006-08-10 17:13:18 +08:00
|
|
|
DPRINTK("pci_register_driver\n");
|
|
|
|
rc = pci_register_driver(&piix_pci_driver);
|
2005-04-17 06:20:36 +08:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
in_module_init = 0;
|
|
|
|
|
|
|
|
DPRINTK("done\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit piix_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&piix_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(piix_init);
|
|
|
|
module_exit(piix_exit);
|