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linux/arch/arm/mach-omap2/sram34xx.S

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ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
/*
* linux/arch/arm/mach-omap3/sram.S
*
* Omap3 specific functions that need to be run in internal SRAM
*
* (C) Copyright 2007
* Texas Instruments Inc.
* Rajendra Nayak <rnayak@ti.com>
*
* (C) Copyright 2004
* Texas Instruments, <www.ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include "sdrc.h"
#include "cm.h"
.text
/*
* Change frequency of core dpll
* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:26:32 +08:00
* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
* SDRC rates < 83MHz
OMAP3 clock: add a short delay when lowering CORE clk rate When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-20 09:08:26 +08:00
* r5 = number of MPU cycles to wait for SDRC to stabilize after
* reprogramming the SDRC when switching to a slower MPU speed
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-20 09:08:27 +08:00
* r6 = SDRC_MR_0 register value
OMAP3 clock: add a short delay when lowering CORE clk rate When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-20 09:08:26 +08:00
*
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
*/
ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack
OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:26:32 +08:00
ldr r4, [sp, #52] @ pull extra args off the stack
OMAP3 clock: add a short delay when lowering CORE clk rate When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-20 09:08:26 +08:00
ldr r5, [sp, #56] @ load extra args from the stack
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-20 09:08:27 +08:00
ldr r6, [sp, #60] @ load extra args from the stack
OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll Add more barriers in the SRAM CORE DPLL M2 divider change code. - Add a DSB SY after the function's entry point to flush all cached and buffered writes and wait for the interconnect to claim that they have completed[1]. The idea here is to force all delayed write traffic going to the SDRAM to at least post to the L3 interconnect before continuing. If these writes are allowed to occur after the SDRC is idled, the writes will not be acknowledged and the ARM will stall. Note that in this case, it does not matter if the writes actually complete to the SDRAM - it is only necessary for the writes to leave the ARM itself. If the writes are posted by the interconnect when the SDRC goes into idle, the writes will be delayed until the SDRC returns from idle[2]. If the SDRC is in the middle of a write when it is requested to enter idle, the SDRC will not acknowledge the idle request until the writes complete to the SDRAM.[3] The old-style DMB in sdram_in_selfrefresh is now superfluous, so, remove it. - Add an ISB before the function's exit point to prevent the ARM from speculatively executing into SDRAM before the SDRAM is enabled[4]. ... 1. ARMv7 ARM (DDI 0406A) A3-47, A3-48. 2. Private communication with Richard Woodruff <r-woodruff2@ti.com>. 3. Private communication with Richard Woodruff <r-woodruff2@ti.com>. 4. ARMv7 ARM (DDI 0406A) A3-48. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
2009-05-13 07:27:09 +08:00
dsb @ flush buffered writes to interconnect
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
cmp r3, #0x2
blne configure_sdrc
OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:26:32 +08:00
cmp r4, #0x1
bleq unlock_dll
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
blne lock_dll
bl sdram_in_selfrefresh @ put the SDRAM in self refresh
bl configure_core_dpll
bl enable_sdrc
OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems unnecessary and error-prone, as the DLL is no longer able to compensate for process, voltage, and temperature variations. Instead, only unlock the DLL when the SDRC clock rate would be less than 83MHz. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:26:32 +08:00
cmp r4, #0x1
bleq wait_dll_unlock
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
blne wait_dll_lock
cmp r3, #0x1
OMAP3 clock: add a short delay when lowering CORE clk rate When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-20 09:08:26 +08:00
beq return_to_sdram
bl configure_sdrc
mov r12, r5 @ if slowing, wait for SDRC to stabilize
bl wait_clk_stable
return_to_sdram:
OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll Add more barriers in the SRAM CORE DPLL M2 divider change code. - Add a DSB SY after the function's entry point to flush all cached and buffered writes and wait for the interconnect to claim that they have completed[1]. The idea here is to force all delayed write traffic going to the SDRAM to at least post to the L3 interconnect before continuing. If these writes are allowed to occur after the SDRC is idled, the writes will not be acknowledged and the ARM will stall. Note that in this case, it does not matter if the writes actually complete to the SDRAM - it is only necessary for the writes to leave the ARM itself. If the writes are posted by the interconnect when the SDRC goes into idle, the writes will be delayed until the SDRC returns from idle[2]. If the SDRC is in the middle of a write when it is requested to enter idle, the SDRC will not acknowledge the idle request until the writes complete to the SDRAM.[3] The old-style DMB in sdram_in_selfrefresh is now superfluous, so, remove it. - Add an ISB before the function's exit point to prevent the ARM from speculatively executing into SDRAM before the SDRAM is enabled[4]. ... 1. ARMv7 ARM (DDI 0406A) A3-47, A3-48. 2. Private communication with Richard Woodruff <r-woodruff2@ti.com>. 3. Private communication with Richard Woodruff <r-woodruff2@ti.com>. 4. ARMv7 ARM (DDI 0406A) A3-48. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
2009-05-13 07:27:09 +08:00
isb @ prevent speculative exec past here
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
mov r0, #0 @ return value
ldmfd sp!, {r1-r12, pc} @ restore regs and return
unlock_dll:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_sdrc_dlla_ctrl
ldr r12, [r11]
orr r12, r12, #0x4
str r12, [r11] @ (no OCP barrier needed)
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bx lr
lock_dll:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_sdrc_dlla_ctrl
ldr r12, [r11]
bic r12, r12, #0x4
str r12, [r11] @ (no OCP barrier needed)
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bx lr
sdram_in_selfrefresh:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
ldr r12, [r11] @ read the contents of SDRC_POWER
mov r9, r12 @ keep a copy of SDRC_POWER bits
orr r12, r12, #0x40 @ enable self refresh on idle req
bic r12, r12, #0x4 @ clear PWDENA
str r12, [r11] @ write back to SDRC_POWER register
ldr r12, [r11] @ posted-write barrier for SDRC
ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
ldr r12, [r11]
bic r12, r12, #0x2 @ disable iclk bit for SDRC
str r12, [r11]
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
wait_sdrc_idle:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_cm_idlest1_core
ldr r12, [r11]
and r12, r12, #0x2 @ check for SDRC idle
cmp r12, #2
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bne wait_sdrc_idle
bx lr
configure_core_dpll:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_cm_clksel1_pll
ldr r12, [r11]
ldr r10, core_m2_mask_val @ modify m2 for core dpll
and r12, r12, r10
orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
str r12, [r11]
ldr r12, [r11] @ posted-write barrier for CM
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bx lr
wait_clk_stable:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
subs r12, r12, #1
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bne wait_clk_stable
bx lr
enable_sdrc:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_cm_iclken1_core
ldr r12, [r11]
orr r12, r12, #0x2 @ enable iclk bit for SDRC
str r12, [r11]
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
wait_sdrc_idle1:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_cm_idlest1_core
ldr r12, [r11]
and r12, r12, #0x2
cmp r12, #0
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bne wait_sdrc_idle1
OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh mode. This prevents the SDRC from attempting to power off the SDRAM, which can cause the system to hang. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:09 +08:00
restore_sdrc_power_val:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_sdrc_power
str r9, [r11] @ restore SDRC_POWER, no barrier needed
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bx lr
wait_dll_lock:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_sdrc_dlla_status
ldr r12, [r11]
and r12, r12, #0x4
cmp r12, #0x4
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bne wait_dll_lock
bx lr
wait_dll_unlock:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_sdrc_dlla_status
ldr r12, [r11]
and r12, r12, #0x4
cmp r12, #0x0
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bne wait_dll_unlock
bx lr
configure_sdrc:
OMAP3 SRAM: renumber registers to make space for argument passing Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-05-13 07:27:10 +08:00
ldr r11, omap3_sdrc_rfr_ctrl
str r0, [r11]
ldr r11, omap3_sdrc_actim_ctrla
str r1, [r11]
ldr r11, omap3_sdrc_actim_ctrlb
str r2, [r11]
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-20 09:08:27 +08:00
ldr r11, omap3_sdrc_mr_0
str r6, [r11]
ldr r6, [r11] @ posted-write barrier for SDRC
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
bx lr
omap3_sdrc_power:
.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
omap3_cm_clksel1_pll:
.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
omap3_cm_idlest1_core:
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
omap3_cm_iclken1_core:
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
omap3_sdrc_rfr_ctrl:
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap3_sdrc_actim_ctrla:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <paul@pwsan.com>
2009-06-20 09:08:27 +08:00
omap3_sdrc_mr_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
ARM: OMAP3: Add minimal omap3430 support Add minimal omap3430 support based on earlier patches from Syed Mohammed Khasim. Also merge in omap34xx SRAM support from Karthik Dasu and use consistent naming for sram init functions. Also do following changes that make 34xx support usable: - Remove unused sram.c functions for 34xx - Rename IRQ_SIR_IRQ to INTCPS_SIR_IRQ and define it locally in entry-macro.S - Update mach-omap2/io.c to support 2420, 2430, and 34xx - Also merge in 34xx GPMC changes to add fields wr_access and wr_data_mux_bus from Adrian Hunter - Remove memory initialization call omap2_init_memory() until until more generic memory initialization patches are posted. It's OK to rely on bootloader initialization until then. Signed-off-by: Syed Mohammed, Khasim <khasim@ti.com> Signed-off-by: Karthik Dasu<karthik-dp@ti.com> Signed-off-by: Adrian Hunter <ext-adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-10-09 22:51:41 +08:00
omap3_sdrc_dlla_status:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
core_m2_mask_val:
.word 0x07FFFFFF
ENTRY(omap3_sram_configure_core_dpll_sz)
.word . - omap3_sram_configure_core_dpll