2015-07-16 06:28:38 +08:00
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/*
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This file is provided under a dual BSD/GPLv2 license. When using or
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redistributing this file, you may do so under either license.
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GPL LICENSE SUMMARY
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Copyright(c) 2014 Intel Corporation.
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This program is free software; you can redistribute it and/or modify
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it under the terms of version 2 of the GNU General Public License as
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published by the Free Software Foundation.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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Contact Information:
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qat-linux@intel.com
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BSD LICENSE
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Copyright(c) 2014 Intel Corporation.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <crypto/internal/rsa.h>
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#include <crypto/internal/akcipher.h>
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#include <crypto/akcipher.h>
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2016-07-07 22:27:29 +08:00
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#include <crypto/kpp.h>
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#include <crypto/internal/kpp.h>
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#include <crypto/dh.h>
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2015-07-16 06:28:38 +08:00
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#include <linux/dma-mapping.h>
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#include <linux/fips.h>
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2015-10-09 00:26:55 +08:00
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#include <crypto/scatterwalk.h>
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2015-07-16 06:28:38 +08:00
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#include "icp_qat_fw_pke.h"
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#include "adf_accel_devices.h"
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#include "adf_transport.h"
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#include "adf_common_drv.h"
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#include "qat_crypto.h"
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2015-07-22 13:07:47 +08:00
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static DEFINE_MUTEX(algs_lock);
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static unsigned int active_devs;
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2015-07-16 06:28:38 +08:00
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struct qat_rsa_input_params {
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union {
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struct {
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dma_addr_t m;
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dma_addr_t e;
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dma_addr_t n;
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} enc;
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struct {
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dma_addr_t c;
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dma_addr_t d;
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dma_addr_t n;
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} dec;
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2016-07-05 00:21:40 +08:00
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struct {
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dma_addr_t c;
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dma_addr_t p;
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dma_addr_t q;
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dma_addr_t dp;
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dma_addr_t dq;
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dma_addr_t qinv;
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} dec_crt;
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2015-07-16 06:28:38 +08:00
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u64 in_tab[8];
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};
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} __packed __aligned(64);
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struct qat_rsa_output_params {
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union {
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struct {
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dma_addr_t c;
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} enc;
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struct {
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dma_addr_t m;
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} dec;
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u64 out_tab[8];
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};
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} __packed __aligned(64);
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struct qat_rsa_ctx {
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char *n;
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char *e;
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char *d;
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2016-07-05 00:21:40 +08:00
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char *p;
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char *q;
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char *dp;
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char *dq;
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char *qinv;
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2015-07-16 06:28:38 +08:00
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dma_addr_t dma_n;
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dma_addr_t dma_e;
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dma_addr_t dma_d;
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2016-07-05 00:21:40 +08:00
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dma_addr_t dma_p;
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dma_addr_t dma_q;
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dma_addr_t dma_dp;
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dma_addr_t dma_dq;
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dma_addr_t dma_qinv;
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2015-07-16 06:28:38 +08:00
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unsigned int key_sz;
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2016-07-05 00:21:40 +08:00
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bool crt_mode;
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2015-07-16 06:28:38 +08:00
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struct qat_crypto_instance *inst;
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} __packed __aligned(64);
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2016-07-07 22:27:29 +08:00
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struct qat_dh_input_params {
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union {
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struct {
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dma_addr_t b;
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dma_addr_t xa;
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dma_addr_t p;
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} in;
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struct {
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dma_addr_t xa;
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dma_addr_t p;
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} in_g2;
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u64 in_tab[8];
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};
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} __packed __aligned(64);
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struct qat_dh_output_params {
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union {
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dma_addr_t r;
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u64 out_tab[8];
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};
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} __packed __aligned(64);
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struct qat_dh_ctx {
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char *g;
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char *xa;
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char *p;
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dma_addr_t dma_g;
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dma_addr_t dma_xa;
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dma_addr_t dma_p;
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unsigned int p_size;
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bool g2;
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struct qat_crypto_instance *inst;
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} __packed __aligned(64);
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struct qat_asym_request {
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union {
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struct qat_rsa_input_params rsa;
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struct qat_dh_input_params dh;
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} in;
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union {
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struct qat_rsa_output_params rsa;
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struct qat_dh_output_params dh;
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} out;
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2015-07-16 06:28:38 +08:00
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dma_addr_t phy_in;
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dma_addr_t phy_out;
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char *src_align;
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2015-10-09 00:26:55 +08:00
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char *dst_align;
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2015-07-16 06:28:38 +08:00
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struct icp_qat_fw_pke_request req;
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2016-07-07 22:27:29 +08:00
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union {
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struct qat_rsa_ctx *rsa;
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struct qat_dh_ctx *dh;
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} ctx;
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union {
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struct akcipher_request *rsa;
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struct kpp_request *dh;
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} areq;
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2015-07-16 06:28:38 +08:00
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int err;
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2016-07-07 22:27:29 +08:00
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void (*cb)(struct icp_qat_fw_pke_resp *resp);
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2015-07-16 06:28:38 +08:00
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} __aligned(64);
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2016-07-07 22:27:29 +08:00
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static void qat_dh_cb(struct icp_qat_fw_pke_resp *resp)
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{
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struct qat_asym_request *req = (void *)(__force long)resp->opaque;
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struct kpp_request *areq = req->areq.dh;
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struct device *dev = &GET_DEV(req->ctx.dh->inst->accel_dev);
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int err = ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(
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resp->pke_resp_hdr.comn_resp_flags);
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err = (err == ICP_QAT_FW_COMN_STATUS_FLAG_OK) ? 0 : -EINVAL;
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if (areq->src) {
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if (req->src_align)
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dma_free_coherent(dev, req->ctx.dh->p_size,
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req->src_align, req->in.dh.in.b);
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else
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dma_unmap_single(dev, req->in.dh.in.b,
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req->ctx.dh->p_size, DMA_TO_DEVICE);
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}
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areq->dst_len = req->ctx.dh->p_size;
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if (req->dst_align) {
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scatterwalk_map_and_copy(req->dst_align, areq->dst, 0,
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areq->dst_len, 1);
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dma_free_coherent(dev, req->ctx.dh->p_size, req->dst_align,
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req->out.dh.r);
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} else {
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dma_unmap_single(dev, req->out.dh.r, req->ctx.dh->p_size,
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DMA_FROM_DEVICE);
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}
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dma_unmap_single(dev, req->phy_in, sizeof(struct qat_dh_input_params),
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DMA_TO_DEVICE);
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dma_unmap_single(dev, req->phy_out,
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sizeof(struct qat_dh_output_params),
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DMA_TO_DEVICE);
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kpp_request_complete(areq, err);
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}
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#define PKE_DH_1536 0x390c1a49
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#define PKE_DH_G2_1536 0x2e0b1a3e
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#define PKE_DH_2048 0x4d0c1a60
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#define PKE_DH_G2_2048 0x3e0b1a55
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#define PKE_DH_3072 0x510c1a77
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#define PKE_DH_G2_3072 0x3a0b1a6c
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#define PKE_DH_4096 0x690c1a8e
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#define PKE_DH_G2_4096 0x4a0b1a83
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static unsigned long qat_dh_fn_id(unsigned int len, bool g2)
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{
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unsigned int bitslen = len << 3;
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switch (bitslen) {
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case 1536:
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return g2 ? PKE_DH_G2_1536 : PKE_DH_1536;
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case 2048:
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return g2 ? PKE_DH_G2_2048 : PKE_DH_2048;
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case 3072:
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return g2 ? PKE_DH_G2_3072 : PKE_DH_3072;
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case 4096:
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return g2 ? PKE_DH_G2_4096 : PKE_DH_4096;
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default:
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return 0;
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};
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}
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static inline struct qat_dh_ctx *qat_dh_get_params(struct crypto_kpp *tfm)
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{
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return kpp_tfm_ctx(tfm);
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}
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static int qat_dh_compute_value(struct kpp_request *req)
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{
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struct crypto_kpp *tfm = crypto_kpp_reqtfm(req);
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struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
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struct qat_crypto_instance *inst = ctx->inst;
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struct device *dev = &GET_DEV(inst->accel_dev);
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struct qat_asym_request *qat_req =
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PTR_ALIGN(kpp_request_ctx(req), 64);
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struct icp_qat_fw_pke_request *msg = &qat_req->req;
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int ret, ctr = 0;
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int n_input_params = 0;
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if (unlikely(!ctx->xa))
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return -EINVAL;
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if (req->dst_len < ctx->p_size) {
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req->dst_len = ctx->p_size;
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return -EOVERFLOW;
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}
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memset(msg, '\0', sizeof(*msg));
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ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(msg->pke_hdr,
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ICP_QAT_FW_COMN_REQ_FLAG_SET);
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msg->pke_hdr.cd_pars.func_id = qat_dh_fn_id(ctx->p_size,
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!req->src && ctx->g2);
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if (unlikely(!msg->pke_hdr.cd_pars.func_id))
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return -EINVAL;
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qat_req->cb = qat_dh_cb;
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qat_req->ctx.dh = ctx;
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qat_req->areq.dh = req;
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msg->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
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msg->pke_hdr.comn_req_flags =
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ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_PTR_TYPE_FLAT,
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QAT_COMN_CD_FLD_TYPE_64BIT_ADR);
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/*
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* If no source is provided use g as base
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*/
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if (req->src) {
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qat_req->in.dh.in.xa = ctx->dma_xa;
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qat_req->in.dh.in.p = ctx->dma_p;
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n_input_params = 3;
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} else {
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if (ctx->g2) {
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qat_req->in.dh.in_g2.xa = ctx->dma_xa;
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qat_req->in.dh.in_g2.p = ctx->dma_p;
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n_input_params = 2;
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} else {
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qat_req->in.dh.in.b = ctx->dma_g;
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qat_req->in.dh.in.xa = ctx->dma_xa;
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qat_req->in.dh.in.p = ctx->dma_p;
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n_input_params = 3;
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}
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}
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ret = -ENOMEM;
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if (req->src) {
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/*
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* src can be of any size in valid range, but HW expects it to
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* be the same as modulo p so in case it is different we need
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* to allocate a new buf and copy src data.
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* In other case we just need to map the user provided buffer.
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* Also need to make sure that it is in contiguous buffer.
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*/
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if (sg_is_last(req->src) && req->src_len == ctx->p_size) {
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qat_req->src_align = NULL;
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qat_req->in.dh.in.b = dma_map_single(dev,
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sg_virt(req->src),
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req->src_len,
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DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(dev,
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qat_req->in.dh.in.b)))
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return ret;
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} else {
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int shift = ctx->p_size - req->src_len;
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qat_req->src_align = dma_zalloc_coherent(dev,
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ctx->p_size,
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&qat_req->in.dh.in.b,
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GFP_KERNEL);
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if (unlikely(!qat_req->src_align))
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return ret;
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scatterwalk_map_and_copy(qat_req->src_align + shift,
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|
|
req->src, 0, req->src_len, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* dst can be of any size in valid range, but HW expects it to be the
|
|
|
|
* same as modulo m so in case it is different we need to allocate a
|
|
|
|
* new buf and copy src data.
|
|
|
|
* In other case we just need to map the user provided buffer.
|
|
|
|
* Also need to make sure that it is in contiguous buffer.
|
|
|
|
*/
|
|
|
|
if (sg_is_last(req->dst) && req->dst_len == ctx->p_size) {
|
|
|
|
qat_req->dst_align = NULL;
|
|
|
|
qat_req->out.dh.r = dma_map_single(dev, sg_virt(req->dst),
|
|
|
|
req->dst_len,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->out.dh.r)))
|
|
|
|
goto unmap_src;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
qat_req->dst_align = dma_zalloc_coherent(dev, ctx->p_size,
|
|
|
|
&qat_req->out.dh.r,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (unlikely(!qat_req->dst_align))
|
|
|
|
goto unmap_src;
|
|
|
|
}
|
|
|
|
|
|
|
|
qat_req->in.dh.in_tab[n_input_params] = 0;
|
|
|
|
qat_req->out.dh.out_tab[1] = 0;
|
|
|
|
/* Mapping in.in.b or in.in_g2.xa is the same */
|
|
|
|
qat_req->phy_in = dma_map_single(dev, &qat_req->in.dh.in.b,
|
|
|
|
sizeof(struct qat_dh_input_params),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->phy_in)))
|
|
|
|
goto unmap_dst;
|
|
|
|
|
|
|
|
qat_req->phy_out = dma_map_single(dev, &qat_req->out.dh.r,
|
|
|
|
sizeof(struct qat_dh_output_params),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->phy_out)))
|
|
|
|
goto unmap_in_params;
|
|
|
|
|
|
|
|
msg->pke_mid.src_data_addr = qat_req->phy_in;
|
|
|
|
msg->pke_mid.dest_data_addr = qat_req->phy_out;
|
|
|
|
msg->pke_mid.opaque = (uint64_t)(__force long)qat_req;
|
|
|
|
msg->input_param_count = n_input_params;
|
|
|
|
msg->output_param_count = 1;
|
|
|
|
|
|
|
|
do {
|
|
|
|
ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg);
|
|
|
|
} while (ret == -EBUSY && ctr++ < 100);
|
|
|
|
|
|
|
|
if (!ret)
|
|
|
|
return -EINPROGRESS;
|
|
|
|
|
|
|
|
if (!dma_mapping_error(dev, qat_req->phy_out))
|
|
|
|
dma_unmap_single(dev, qat_req->phy_out,
|
|
|
|
sizeof(struct qat_dh_output_params),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
unmap_in_params:
|
|
|
|
if (!dma_mapping_error(dev, qat_req->phy_in))
|
|
|
|
dma_unmap_single(dev, qat_req->phy_in,
|
|
|
|
sizeof(struct qat_dh_input_params),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
unmap_dst:
|
|
|
|
if (qat_req->dst_align)
|
|
|
|
dma_free_coherent(dev, ctx->p_size, qat_req->dst_align,
|
|
|
|
qat_req->out.dh.r);
|
|
|
|
else
|
|
|
|
if (!dma_mapping_error(dev, qat_req->out.dh.r))
|
|
|
|
dma_unmap_single(dev, qat_req->out.dh.r, ctx->p_size,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
unmap_src:
|
|
|
|
if (req->src) {
|
|
|
|
if (qat_req->src_align)
|
|
|
|
dma_free_coherent(dev, ctx->p_size, qat_req->src_align,
|
|
|
|
qat_req->in.dh.in.b);
|
|
|
|
else
|
|
|
|
if (!dma_mapping_error(dev, qat_req->in.dh.in.b))
|
|
|
|
dma_unmap_single(dev, qat_req->in.dh.in.b,
|
|
|
|
ctx->p_size,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qat_dh_check_params_length(unsigned int p_len)
|
|
|
|
{
|
|
|
|
switch (p_len) {
|
|
|
|
case 1536:
|
|
|
|
case 2048:
|
|
|
|
case 3072:
|
|
|
|
case 4096:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qat_dh_set_params(struct qat_dh_ctx *ctx, struct dh *params)
|
|
|
|
{
|
|
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
|
|
|
|
|
|
if (qat_dh_check_params_length(params->p_size << 3))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ctx->p_size = params->p_size;
|
|
|
|
ctx->p = dma_zalloc_coherent(dev, ctx->p_size, &ctx->dma_p, GFP_KERNEL);
|
|
|
|
if (!ctx->p)
|
|
|
|
return -ENOMEM;
|
|
|
|
memcpy(ctx->p, params->p, ctx->p_size);
|
|
|
|
|
|
|
|
/* If g equals 2 don't copy it */
|
|
|
|
if (params->g_size == 1 && *(char *)params->g == 0x02) {
|
|
|
|
ctx->g2 = true;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->g = dma_zalloc_coherent(dev, ctx->p_size, &ctx->dma_g, GFP_KERNEL);
|
2017-11-06 10:30:47 +08:00
|
|
|
if (!ctx->g)
|
2016-07-07 22:27:29 +08:00
|
|
|
return -ENOMEM;
|
|
|
|
memcpy(ctx->g + (ctx->p_size - params->g_size), params->g,
|
|
|
|
params->g_size);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qat_dh_clear_ctx(struct device *dev, struct qat_dh_ctx *ctx)
|
|
|
|
{
|
|
|
|
if (ctx->g) {
|
|
|
|
dma_free_coherent(dev, ctx->p_size, ctx->g, ctx->dma_g);
|
|
|
|
ctx->g = NULL;
|
|
|
|
}
|
|
|
|
if (ctx->xa) {
|
|
|
|
dma_free_coherent(dev, ctx->p_size, ctx->xa, ctx->dma_xa);
|
|
|
|
ctx->xa = NULL;
|
|
|
|
}
|
|
|
|
if (ctx->p) {
|
|
|
|
dma_free_coherent(dev, ctx->p_size, ctx->p, ctx->dma_p);
|
|
|
|
ctx->p = NULL;
|
|
|
|
}
|
|
|
|
ctx->p_size = 0;
|
|
|
|
ctx->g2 = false;
|
|
|
|
}
|
|
|
|
|
2017-02-25 07:46:58 +08:00
|
|
|
static int qat_dh_set_secret(struct crypto_kpp *tfm, const void *buf,
|
2016-07-07 22:27:29 +08:00
|
|
|
unsigned int len)
|
|
|
|
{
|
|
|
|
struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
|
|
|
|
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
|
|
|
|
struct dh params;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (crypto_dh_decode_key(buf, len, ¶ms) < 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* Free old secret if any */
|
|
|
|
qat_dh_clear_ctx(dev, ctx);
|
|
|
|
|
|
|
|
ret = qat_dh_set_params(ctx, ¶ms);
|
|
|
|
if (ret < 0)
|
2017-11-06 10:30:47 +08:00
|
|
|
goto err_clear_ctx;
|
2016-07-07 22:27:29 +08:00
|
|
|
|
|
|
|
ctx->xa = dma_zalloc_coherent(dev, ctx->p_size, &ctx->dma_xa,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!ctx->xa) {
|
2017-11-06 10:30:47 +08:00
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_clear_ctx;
|
2016-07-07 22:27:29 +08:00
|
|
|
}
|
|
|
|
memcpy(ctx->xa + (ctx->p_size - params.key_size), params.key,
|
|
|
|
params.key_size);
|
|
|
|
|
|
|
|
return 0;
|
2017-11-06 10:30:47 +08:00
|
|
|
|
|
|
|
err_clear_ctx:
|
|
|
|
qat_dh_clear_ctx(dev, ctx);
|
|
|
|
return ret;
|
2016-07-07 22:27:29 +08:00
|
|
|
}
|
|
|
|
|
2017-05-25 15:18:11 +08:00
|
|
|
static unsigned int qat_dh_max_size(struct crypto_kpp *tfm)
|
2016-07-07 22:27:29 +08:00
|
|
|
{
|
|
|
|
struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
|
|
|
|
|
2017-05-25 15:18:11 +08:00
|
|
|
return ctx->p_size;
|
2016-07-07 22:27:29 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int qat_dh_init_tfm(struct crypto_kpp *tfm)
|
|
|
|
{
|
|
|
|
struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
|
|
|
|
struct qat_crypto_instance *inst =
|
|
|
|
qat_crypto_get_instance_node(get_current_node());
|
|
|
|
|
|
|
|
if (!inst)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ctx->p_size = 0;
|
|
|
|
ctx->g2 = false;
|
|
|
|
ctx->inst = inst;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qat_dh_exit_tfm(struct crypto_kpp *tfm)
|
|
|
|
{
|
|
|
|
struct qat_dh_ctx *ctx = kpp_tfm_ctx(tfm);
|
|
|
|
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
|
|
|
|
|
|
|
|
qat_dh_clear_ctx(dev, ctx);
|
|
|
|
qat_crypto_put_instance(ctx->inst);
|
|
|
|
}
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
static void qat_rsa_cb(struct icp_qat_fw_pke_resp *resp)
|
|
|
|
{
|
2016-07-07 22:27:29 +08:00
|
|
|
struct qat_asym_request *req = (void *)(__force long)resp->opaque;
|
|
|
|
struct akcipher_request *areq = req->areq.rsa;
|
|
|
|
struct device *dev = &GET_DEV(req->ctx.rsa->inst->accel_dev);
|
2015-07-16 06:28:38 +08:00
|
|
|
int err = ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(
|
|
|
|
resp->pke_resp_hdr.comn_resp_flags);
|
|
|
|
|
|
|
|
err = (err == ICP_QAT_FW_COMN_STATUS_FLAG_OK) ? 0 : -EINVAL;
|
|
|
|
|
|
|
|
if (req->src_align)
|
2016-07-07 22:27:29 +08:00
|
|
|
dma_free_coherent(dev, req->ctx.rsa->key_sz, req->src_align,
|
|
|
|
req->in.rsa.enc.m);
|
2015-07-16 06:28:38 +08:00
|
|
|
else
|
2016-07-07 22:27:29 +08:00
|
|
|
dma_unmap_single(dev, req->in.rsa.enc.m, req->ctx.rsa->key_sz,
|
2015-07-16 06:28:38 +08:00
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
areq->dst_len = req->ctx.rsa->key_sz;
|
2015-10-09 00:26:55 +08:00
|
|
|
if (req->dst_align) {
|
|
|
|
scatterwalk_map_and_copy(req->dst_align, areq->dst, 0,
|
|
|
|
areq->dst_len, 1);
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
dma_free_coherent(dev, req->ctx.rsa->key_sz, req->dst_align,
|
|
|
|
req->out.rsa.enc.c);
|
2015-10-09 00:26:55 +08:00
|
|
|
} else {
|
2016-07-07 22:27:29 +08:00
|
|
|
dma_unmap_single(dev, req->out.rsa.enc.c, req->ctx.rsa->key_sz,
|
2015-10-09 00:26:55 +08:00
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
}
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
dma_unmap_single(dev, req->phy_in, sizeof(struct qat_rsa_input_params),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
dma_unmap_single(dev, req->phy_out,
|
|
|
|
sizeof(struct qat_rsa_output_params),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
akcipher_request_complete(areq, err);
|
|
|
|
}
|
|
|
|
|
|
|
|
void qat_alg_asym_callback(void *_resp)
|
|
|
|
{
|
|
|
|
struct icp_qat_fw_pke_resp *resp = _resp;
|
2016-07-07 22:27:29 +08:00
|
|
|
struct qat_asym_request *areq = (void *)(__force long)resp->opaque;
|
2015-07-16 06:28:38 +08:00
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
areq->cb(resp);
|
2015-07-16 06:28:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
#define PKE_RSA_EP_512 0x1c161b21
|
|
|
|
#define PKE_RSA_EP_1024 0x35111bf7
|
|
|
|
#define PKE_RSA_EP_1536 0x4d111cdc
|
|
|
|
#define PKE_RSA_EP_2048 0x6e111dba
|
|
|
|
#define PKE_RSA_EP_3072 0x7d111ea3
|
|
|
|
#define PKE_RSA_EP_4096 0xa5101f7e
|
|
|
|
|
|
|
|
static unsigned long qat_rsa_enc_fn_id(unsigned int len)
|
|
|
|
{
|
|
|
|
unsigned int bitslen = len << 3;
|
|
|
|
|
|
|
|
switch (bitslen) {
|
|
|
|
case 512:
|
|
|
|
return PKE_RSA_EP_512;
|
|
|
|
case 1024:
|
|
|
|
return PKE_RSA_EP_1024;
|
|
|
|
case 1536:
|
|
|
|
return PKE_RSA_EP_1536;
|
|
|
|
case 2048:
|
|
|
|
return PKE_RSA_EP_2048;
|
|
|
|
case 3072:
|
|
|
|
return PKE_RSA_EP_3072;
|
|
|
|
case 4096:
|
|
|
|
return PKE_RSA_EP_4096;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
|
|
|
#define PKE_RSA_DP1_512 0x1c161b3c
|
|
|
|
#define PKE_RSA_DP1_1024 0x35111c12
|
|
|
|
#define PKE_RSA_DP1_1536 0x4d111cf7
|
|
|
|
#define PKE_RSA_DP1_2048 0x6e111dda
|
|
|
|
#define PKE_RSA_DP1_3072 0x7d111ebe
|
|
|
|
#define PKE_RSA_DP1_4096 0xa5101f98
|
|
|
|
|
|
|
|
static unsigned long qat_rsa_dec_fn_id(unsigned int len)
|
|
|
|
{
|
|
|
|
unsigned int bitslen = len << 3;
|
|
|
|
|
|
|
|
switch (bitslen) {
|
|
|
|
case 512:
|
|
|
|
return PKE_RSA_DP1_512;
|
|
|
|
case 1024:
|
|
|
|
return PKE_RSA_DP1_1024;
|
|
|
|
case 1536:
|
|
|
|
return PKE_RSA_DP1_1536;
|
|
|
|
case 2048:
|
|
|
|
return PKE_RSA_DP1_2048;
|
|
|
|
case 3072:
|
|
|
|
return PKE_RSA_DP1_3072;
|
|
|
|
case 4096:
|
|
|
|
return PKE_RSA_DP1_4096;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2016-07-05 00:21:40 +08:00
|
|
|
#define PKE_RSA_DP2_512 0x1c131b57
|
|
|
|
#define PKE_RSA_DP2_1024 0x26131c2d
|
|
|
|
#define PKE_RSA_DP2_1536 0x45111d12
|
|
|
|
#define PKE_RSA_DP2_2048 0x59121dfa
|
|
|
|
#define PKE_RSA_DP2_3072 0x81121ed9
|
|
|
|
#define PKE_RSA_DP2_4096 0xb1111fb2
|
|
|
|
|
|
|
|
static unsigned long qat_rsa_dec_fn_id_crt(unsigned int len)
|
|
|
|
{
|
|
|
|
unsigned int bitslen = len << 3;
|
|
|
|
|
|
|
|
switch (bitslen) {
|
|
|
|
case 512:
|
|
|
|
return PKE_RSA_DP2_512;
|
|
|
|
case 1024:
|
|
|
|
return PKE_RSA_DP2_1024;
|
|
|
|
case 1536:
|
|
|
|
return PKE_RSA_DP2_1536;
|
|
|
|
case 2048:
|
|
|
|
return PKE_RSA_DP2_2048;
|
|
|
|
case 3072:
|
|
|
|
return PKE_RSA_DP2_3072;
|
|
|
|
case 4096:
|
|
|
|
return PKE_RSA_DP2_4096;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
};
|
|
|
|
}
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
static int qat_rsa_enc(struct akcipher_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
|
|
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
2016-07-07 22:27:29 +08:00
|
|
|
struct qat_asym_request *qat_req =
|
2015-07-16 06:28:38 +08:00
|
|
|
PTR_ALIGN(akcipher_request_ctx(req), 64);
|
|
|
|
struct icp_qat_fw_pke_request *msg = &qat_req->req;
|
|
|
|
int ret, ctr = 0;
|
|
|
|
|
|
|
|
if (unlikely(!ctx->n || !ctx->e))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (req->dst_len < ctx->key_sz) {
|
|
|
|
req->dst_len = ctx->key_sz;
|
|
|
|
return -EOVERFLOW;
|
|
|
|
}
|
|
|
|
memset(msg, '\0', sizeof(*msg));
|
|
|
|
ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(msg->pke_hdr,
|
|
|
|
ICP_QAT_FW_COMN_REQ_FLAG_SET);
|
|
|
|
msg->pke_hdr.cd_pars.func_id = qat_rsa_enc_fn_id(ctx->key_sz);
|
|
|
|
if (unlikely(!msg->pke_hdr.cd_pars.func_id))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->cb = qat_rsa_cb;
|
|
|
|
qat_req->ctx.rsa = ctx;
|
|
|
|
qat_req->areq.rsa = req;
|
2015-07-16 06:28:38 +08:00
|
|
|
msg->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
|
|
|
|
msg->pke_hdr.comn_req_flags =
|
|
|
|
ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_PTR_TYPE_FLAT,
|
|
|
|
QAT_COMN_CD_FLD_TYPE_64BIT_ADR);
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.enc.e = ctx->dma_e;
|
|
|
|
qat_req->in.rsa.enc.n = ctx->dma_n;
|
2015-07-16 06:28:38 +08:00
|
|
|
ret = -ENOMEM;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* src can be of any size in valid range, but HW expects it to be the
|
|
|
|
* same as modulo n so in case it is different we need to allocate a
|
|
|
|
* new buf and copy src data.
|
|
|
|
* In other case we just need to map the user provided buffer.
|
2015-10-09 00:26:55 +08:00
|
|
|
* Also need to make sure that it is in contiguous buffer.
|
2015-07-16 06:28:38 +08:00
|
|
|
*/
|
2015-10-09 00:26:55 +08:00
|
|
|
if (sg_is_last(req->src) && req->src_len == ctx->key_sz) {
|
|
|
|
qat_req->src_align = NULL;
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.enc.m = dma_map_single(dev, sg_virt(req->src),
|
2015-10-09 00:26:55 +08:00
|
|
|
req->src_len, DMA_TO_DEVICE);
|
2016-07-07 22:27:29 +08:00
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->in.rsa.enc.m)))
|
2015-10-09 00:26:55 +08:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
} else {
|
2015-07-16 06:28:38 +08:00
|
|
|
int shift = ctx->key_sz - req->src_len;
|
|
|
|
|
|
|
|
qat_req->src_align = dma_zalloc_coherent(dev, ctx->key_sz,
|
2016-07-07 22:27:29 +08:00
|
|
|
&qat_req->in.rsa.enc.m,
|
2015-07-16 06:28:38 +08:00
|
|
|
GFP_KERNEL);
|
|
|
|
if (unlikely(!qat_req->src_align))
|
|
|
|
return ret;
|
|
|
|
|
2015-10-09 00:26:55 +08:00
|
|
|
scatterwalk_map_and_copy(qat_req->src_align + shift, req->src,
|
|
|
|
0, req->src_len, 0);
|
|
|
|
}
|
|
|
|
if (sg_is_last(req->dst) && req->dst_len == ctx->key_sz) {
|
|
|
|
qat_req->dst_align = NULL;
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->out.rsa.enc.c = dma_map_single(dev, sg_virt(req->dst),
|
|
|
|
req->dst_len,
|
|
|
|
DMA_FROM_DEVICE);
|
2015-10-09 00:26:55 +08:00
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->out.rsa.enc.c)))
|
2015-10-09 00:26:55 +08:00
|
|
|
goto unmap_src;
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
} else {
|
2015-10-09 00:26:55 +08:00
|
|
|
qat_req->dst_align = dma_zalloc_coherent(dev, ctx->key_sz,
|
2016-07-07 22:27:29 +08:00
|
|
|
&qat_req->out.rsa.enc.c,
|
2015-10-09 00:26:55 +08:00
|
|
|
GFP_KERNEL);
|
|
|
|
if (unlikely(!qat_req->dst_align))
|
|
|
|
goto unmap_src;
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
}
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.in_tab[3] = 0;
|
|
|
|
qat_req->out.rsa.out_tab[1] = 0;
|
|
|
|
qat_req->phy_in = dma_map_single(dev, &qat_req->in.rsa.enc.m,
|
2015-07-16 06:28:38 +08:00
|
|
|
sizeof(struct qat_rsa_input_params),
|
|
|
|
DMA_TO_DEVICE);
|
2015-10-09 00:26:55 +08:00
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->phy_in)))
|
|
|
|
goto unmap_dst;
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->phy_out = dma_map_single(dev, &qat_req->out.rsa.enc.c,
|
2015-07-16 06:28:38 +08:00
|
|
|
sizeof(struct qat_rsa_output_params),
|
2015-10-09 00:26:55 +08:00
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->phy_out)))
|
|
|
|
goto unmap_in_params;
|
2015-07-16 06:28:38 +08:00
|
|
|
|
|
|
|
msg->pke_mid.src_data_addr = qat_req->phy_in;
|
|
|
|
msg->pke_mid.dest_data_addr = qat_req->phy_out;
|
2016-07-07 22:27:29 +08:00
|
|
|
msg->pke_mid.opaque = (uint64_t)(__force long)qat_req;
|
2015-07-16 06:28:38 +08:00
|
|
|
msg->input_param_count = 3;
|
|
|
|
msg->output_param_count = 1;
|
|
|
|
do {
|
|
|
|
ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg);
|
|
|
|
} while (ret == -EBUSY && ctr++ < 100);
|
|
|
|
|
|
|
|
if (!ret)
|
|
|
|
return -EINPROGRESS;
|
2016-02-11 06:59:44 +08:00
|
|
|
|
|
|
|
if (!dma_mapping_error(dev, qat_req->phy_out))
|
|
|
|
dma_unmap_single(dev, qat_req->phy_out,
|
|
|
|
sizeof(struct qat_rsa_output_params),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
unmap_in_params:
|
|
|
|
if (!dma_mapping_error(dev, qat_req->phy_in))
|
|
|
|
dma_unmap_single(dev, qat_req->phy_in,
|
|
|
|
sizeof(struct qat_rsa_input_params),
|
|
|
|
DMA_TO_DEVICE);
|
2015-10-09 00:26:55 +08:00
|
|
|
unmap_dst:
|
|
|
|
if (qat_req->dst_align)
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, qat_req->dst_align,
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->out.rsa.enc.c);
|
2015-10-09 00:26:55 +08:00
|
|
|
else
|
2016-07-07 22:27:29 +08:00
|
|
|
if (!dma_mapping_error(dev, qat_req->out.rsa.enc.c))
|
|
|
|
dma_unmap_single(dev, qat_req->out.rsa.enc.c,
|
|
|
|
ctx->key_sz, DMA_FROM_DEVICE);
|
2016-02-11 06:59:44 +08:00
|
|
|
unmap_src:
|
|
|
|
if (qat_req->src_align)
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, qat_req->src_align,
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.enc.m);
|
2016-02-11 06:59:44 +08:00
|
|
|
else
|
2016-07-07 22:27:29 +08:00
|
|
|
if (!dma_mapping_error(dev, qat_req->in.rsa.enc.m))
|
|
|
|
dma_unmap_single(dev, qat_req->in.rsa.enc.m,
|
|
|
|
ctx->key_sz, DMA_TO_DEVICE);
|
2015-07-16 06:28:38 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qat_rsa_dec(struct akcipher_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req);
|
|
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
2016-07-07 22:27:29 +08:00
|
|
|
struct qat_asym_request *qat_req =
|
2015-07-16 06:28:38 +08:00
|
|
|
PTR_ALIGN(akcipher_request_ctx(req), 64);
|
|
|
|
struct icp_qat_fw_pke_request *msg = &qat_req->req;
|
|
|
|
int ret, ctr = 0;
|
|
|
|
|
|
|
|
if (unlikely(!ctx->n || !ctx->d))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (req->dst_len < ctx->key_sz) {
|
|
|
|
req->dst_len = ctx->key_sz;
|
|
|
|
return -EOVERFLOW;
|
|
|
|
}
|
|
|
|
memset(msg, '\0', sizeof(*msg));
|
|
|
|
ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(msg->pke_hdr,
|
|
|
|
ICP_QAT_FW_COMN_REQ_FLAG_SET);
|
2016-07-05 00:21:40 +08:00
|
|
|
msg->pke_hdr.cd_pars.func_id = ctx->crt_mode ?
|
|
|
|
qat_rsa_dec_fn_id_crt(ctx->key_sz) :
|
|
|
|
qat_rsa_dec_fn_id(ctx->key_sz);
|
2015-07-16 06:28:38 +08:00
|
|
|
if (unlikely(!msg->pke_hdr.cd_pars.func_id))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->cb = qat_rsa_cb;
|
|
|
|
qat_req->ctx.rsa = ctx;
|
|
|
|
qat_req->areq.rsa = req;
|
2015-07-16 06:28:38 +08:00
|
|
|
msg->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;
|
|
|
|
msg->pke_hdr.comn_req_flags =
|
|
|
|
ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_PTR_TYPE_FLAT,
|
|
|
|
QAT_COMN_CD_FLD_TYPE_64BIT_ADR);
|
|
|
|
|
2016-07-05 00:21:40 +08:00
|
|
|
if (ctx->crt_mode) {
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.dec_crt.p = ctx->dma_p;
|
|
|
|
qat_req->in.rsa.dec_crt.q = ctx->dma_q;
|
|
|
|
qat_req->in.rsa.dec_crt.dp = ctx->dma_dp;
|
|
|
|
qat_req->in.rsa.dec_crt.dq = ctx->dma_dq;
|
|
|
|
qat_req->in.rsa.dec_crt.qinv = ctx->dma_qinv;
|
2016-07-05 00:21:40 +08:00
|
|
|
} else {
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.dec.d = ctx->dma_d;
|
|
|
|
qat_req->in.rsa.dec.n = ctx->dma_n;
|
2016-07-05 00:21:40 +08:00
|
|
|
}
|
2015-07-16 06:28:38 +08:00
|
|
|
ret = -ENOMEM;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* src can be of any size in valid range, but HW expects it to be the
|
|
|
|
* same as modulo n so in case it is different we need to allocate a
|
|
|
|
* new buf and copy src data.
|
|
|
|
* In other case we just need to map the user provided buffer.
|
2015-10-09 00:26:55 +08:00
|
|
|
* Also need to make sure that it is in contiguous buffer.
|
2015-07-16 06:28:38 +08:00
|
|
|
*/
|
2015-10-09 00:26:55 +08:00
|
|
|
if (sg_is_last(req->src) && req->src_len == ctx->key_sz) {
|
|
|
|
qat_req->src_align = NULL;
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.dec.c = dma_map_single(dev, sg_virt(req->src),
|
2015-10-09 00:26:55 +08:00
|
|
|
req->dst_len, DMA_TO_DEVICE);
|
2016-07-07 22:27:29 +08:00
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->in.rsa.dec.c)))
|
2015-10-09 00:26:55 +08:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
} else {
|
2015-07-16 06:28:38 +08:00
|
|
|
int shift = ctx->key_sz - req->src_len;
|
|
|
|
|
|
|
|
qat_req->src_align = dma_zalloc_coherent(dev, ctx->key_sz,
|
2016-07-07 22:27:29 +08:00
|
|
|
&qat_req->in.rsa.dec.c,
|
2015-07-16 06:28:38 +08:00
|
|
|
GFP_KERNEL);
|
|
|
|
if (unlikely(!qat_req->src_align))
|
|
|
|
return ret;
|
|
|
|
|
2015-10-09 00:26:55 +08:00
|
|
|
scatterwalk_map_and_copy(qat_req->src_align + shift, req->src,
|
|
|
|
0, req->src_len, 0);
|
|
|
|
}
|
|
|
|
if (sg_is_last(req->dst) && req->dst_len == ctx->key_sz) {
|
|
|
|
qat_req->dst_align = NULL;
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->out.rsa.dec.m = dma_map_single(dev, sg_virt(req->dst),
|
2015-10-09 00:26:55 +08:00
|
|
|
req->dst_len,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->out.rsa.dec.m)))
|
2015-10-09 00:26:55 +08:00
|
|
|
goto unmap_src;
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
} else {
|
2015-10-09 00:26:55 +08:00
|
|
|
qat_req->dst_align = dma_zalloc_coherent(dev, ctx->key_sz,
|
2016-07-07 22:27:29 +08:00
|
|
|
&qat_req->out.rsa.dec.m,
|
2015-10-09 00:26:55 +08:00
|
|
|
GFP_KERNEL);
|
|
|
|
if (unlikely(!qat_req->dst_align))
|
|
|
|
goto unmap_src;
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
}
|
2015-10-09 00:26:55 +08:00
|
|
|
|
2016-07-05 00:21:40 +08:00
|
|
|
if (ctx->crt_mode)
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.in_tab[6] = 0;
|
2016-07-05 00:21:40 +08:00
|
|
|
else
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.in_tab[3] = 0;
|
|
|
|
qat_req->out.rsa.out_tab[1] = 0;
|
|
|
|
qat_req->phy_in = dma_map_single(dev, &qat_req->in.rsa.dec.c,
|
2015-07-16 06:28:38 +08:00
|
|
|
sizeof(struct qat_rsa_input_params),
|
|
|
|
DMA_TO_DEVICE);
|
2015-10-09 00:26:55 +08:00
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->phy_in)))
|
|
|
|
goto unmap_dst;
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->phy_out = dma_map_single(dev, &qat_req->out.rsa.dec.m,
|
2015-07-16 06:28:38 +08:00
|
|
|
sizeof(struct qat_rsa_output_params),
|
2015-10-09 00:26:55 +08:00
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (unlikely(dma_mapping_error(dev, qat_req->phy_out)))
|
|
|
|
goto unmap_in_params;
|
2015-07-16 06:28:38 +08:00
|
|
|
|
|
|
|
msg->pke_mid.src_data_addr = qat_req->phy_in;
|
|
|
|
msg->pke_mid.dest_data_addr = qat_req->phy_out;
|
2016-07-07 22:27:29 +08:00
|
|
|
msg->pke_mid.opaque = (uint64_t)(__force long)qat_req;
|
2016-07-05 00:21:40 +08:00
|
|
|
if (ctx->crt_mode)
|
|
|
|
msg->input_param_count = 6;
|
|
|
|
else
|
|
|
|
msg->input_param_count = 3;
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
msg->output_param_count = 1;
|
|
|
|
do {
|
|
|
|
ret = adf_send_message(ctx->inst->pke_tx, (uint32_t *)msg);
|
|
|
|
} while (ret == -EBUSY && ctr++ < 100);
|
|
|
|
|
|
|
|
if (!ret)
|
|
|
|
return -EINPROGRESS;
|
2016-02-11 06:59:44 +08:00
|
|
|
|
|
|
|
if (!dma_mapping_error(dev, qat_req->phy_out))
|
|
|
|
dma_unmap_single(dev, qat_req->phy_out,
|
|
|
|
sizeof(struct qat_rsa_output_params),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
unmap_in_params:
|
|
|
|
if (!dma_mapping_error(dev, qat_req->phy_in))
|
|
|
|
dma_unmap_single(dev, qat_req->phy_in,
|
|
|
|
sizeof(struct qat_rsa_input_params),
|
|
|
|
DMA_TO_DEVICE);
|
2015-10-09 00:26:55 +08:00
|
|
|
unmap_dst:
|
|
|
|
if (qat_req->dst_align)
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, qat_req->dst_align,
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->out.rsa.dec.m);
|
2015-10-09 00:26:55 +08:00
|
|
|
else
|
2016-07-07 22:27:29 +08:00
|
|
|
if (!dma_mapping_error(dev, qat_req->out.rsa.dec.m))
|
|
|
|
dma_unmap_single(dev, qat_req->out.rsa.dec.m,
|
|
|
|
ctx->key_sz, DMA_FROM_DEVICE);
|
2016-02-11 06:59:44 +08:00
|
|
|
unmap_src:
|
|
|
|
if (qat_req->src_align)
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, qat_req->src_align,
|
2016-07-07 22:27:29 +08:00
|
|
|
qat_req->in.rsa.dec.c);
|
2016-02-11 06:59:44 +08:00
|
|
|
else
|
2016-07-07 22:27:29 +08:00
|
|
|
if (!dma_mapping_error(dev, qat_req->in.rsa.dec.c))
|
|
|
|
dma_unmap_single(dev, qat_req->in.rsa.dec.c,
|
|
|
|
ctx->key_sz, DMA_TO_DEVICE);
|
2015-07-16 06:28:38 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-02-07 07:36:42 +08:00
|
|
|
static int qat_rsa_set_n(struct qat_rsa_ctx *ctx, const char *value,
|
|
|
|
size_t vlen)
|
2015-07-16 06:28:38 +08:00
|
|
|
{
|
|
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
|
|
const char *ptr = value;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
while (!*ptr && vlen) {
|
|
|
|
ptr++;
|
|
|
|
vlen--;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->key_sz = vlen;
|
|
|
|
ret = -EINVAL;
|
|
|
|
/* invalid key size provided */
|
|
|
|
if (!qat_rsa_enc_fn_id(ctx->key_sz))
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = -ENOMEM;
|
|
|
|
ctx->n = dma_zalloc_coherent(dev, ctx->key_sz, &ctx->dma_n, GFP_KERNEL);
|
|
|
|
if (!ctx->n)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
memcpy(ctx->n, ptr, ctx->key_sz);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
ctx->key_sz = 0;
|
|
|
|
ctx->n = NULL;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-02-07 07:36:42 +08:00
|
|
|
static int qat_rsa_set_e(struct qat_rsa_ctx *ctx, const char *value,
|
|
|
|
size_t vlen)
|
2015-07-16 06:28:38 +08:00
|
|
|
{
|
|
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
|
|
const char *ptr = value;
|
|
|
|
|
|
|
|
while (!*ptr && vlen) {
|
|
|
|
ptr++;
|
|
|
|
vlen--;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!ctx->key_sz || !vlen || vlen > ctx->key_sz) {
|
|
|
|
ctx->e = NULL;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->e = dma_zalloc_coherent(dev, ctx->key_sz, &ctx->dma_e, GFP_KERNEL);
|
2016-07-04 17:49:28 +08:00
|
|
|
if (!ctx->e)
|
2015-07-16 06:28:38 +08:00
|
|
|
return -ENOMEM;
|
2016-07-04 17:49:28 +08:00
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
memcpy(ctx->e + (ctx->key_sz - vlen), ptr, vlen);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-02-07 07:36:42 +08:00
|
|
|
static int qat_rsa_set_d(struct qat_rsa_ctx *ctx, const char *value,
|
|
|
|
size_t vlen)
|
2015-07-16 06:28:38 +08:00
|
|
|
{
|
|
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
|
|
const char *ptr = value;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
while (!*ptr && vlen) {
|
|
|
|
ptr++;
|
|
|
|
vlen--;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = -EINVAL;
|
|
|
|
if (!ctx->key_sz || !vlen || vlen > ctx->key_sz)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = -ENOMEM;
|
|
|
|
ctx->d = dma_zalloc_coherent(dev, ctx->key_sz, &ctx->dma_d, GFP_KERNEL);
|
2016-03-23 23:06:39 +08:00
|
|
|
if (!ctx->d)
|
2015-07-16 06:28:38 +08:00
|
|
|
goto err;
|
|
|
|
|
|
|
|
memcpy(ctx->d + (ctx->key_sz - vlen), ptr, vlen);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
ctx->d = NULL;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-07-05 00:21:40 +08:00
|
|
|
static void qat_rsa_drop_leading_zeros(const char **ptr, unsigned int *len)
|
2015-07-16 06:28:38 +08:00
|
|
|
{
|
2016-07-05 00:21:40 +08:00
|
|
|
while (!**ptr && *len) {
|
|
|
|
(*ptr)++;
|
|
|
|
(*len)--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qat_rsa_setkey_crt(struct qat_rsa_ctx *ctx, struct rsa_key *rsa_key)
|
|
|
|
{
|
|
|
|
struct qat_crypto_instance *inst = ctx->inst;
|
|
|
|
struct device *dev = &GET_DEV(inst->accel_dev);
|
|
|
|
const char *ptr;
|
|
|
|
unsigned int len;
|
|
|
|
unsigned int half_key_sz = ctx->key_sz / 2;
|
|
|
|
|
|
|
|
/* p */
|
|
|
|
ptr = rsa_key->p;
|
|
|
|
len = rsa_key->p_sz;
|
|
|
|
qat_rsa_drop_leading_zeros(&ptr, &len);
|
|
|
|
if (!len)
|
|
|
|
goto err;
|
|
|
|
ctx->p = dma_zalloc_coherent(dev, half_key_sz, &ctx->dma_p, GFP_KERNEL);
|
|
|
|
if (!ctx->p)
|
|
|
|
goto err;
|
|
|
|
memcpy(ctx->p + (half_key_sz - len), ptr, len);
|
|
|
|
|
|
|
|
/* q */
|
|
|
|
ptr = rsa_key->q;
|
|
|
|
len = rsa_key->q_sz;
|
|
|
|
qat_rsa_drop_leading_zeros(&ptr, &len);
|
|
|
|
if (!len)
|
|
|
|
goto free_p;
|
|
|
|
ctx->q = dma_zalloc_coherent(dev, half_key_sz, &ctx->dma_q, GFP_KERNEL);
|
|
|
|
if (!ctx->q)
|
|
|
|
goto free_p;
|
|
|
|
memcpy(ctx->q + (half_key_sz - len), ptr, len);
|
|
|
|
|
|
|
|
/* dp */
|
|
|
|
ptr = rsa_key->dp;
|
|
|
|
len = rsa_key->dp_sz;
|
|
|
|
qat_rsa_drop_leading_zeros(&ptr, &len);
|
|
|
|
if (!len)
|
|
|
|
goto free_q;
|
|
|
|
ctx->dp = dma_zalloc_coherent(dev, half_key_sz, &ctx->dma_dp,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!ctx->dp)
|
|
|
|
goto free_q;
|
|
|
|
memcpy(ctx->dp + (half_key_sz - len), ptr, len);
|
|
|
|
|
|
|
|
/* dq */
|
|
|
|
ptr = rsa_key->dq;
|
|
|
|
len = rsa_key->dq_sz;
|
|
|
|
qat_rsa_drop_leading_zeros(&ptr, &len);
|
|
|
|
if (!len)
|
|
|
|
goto free_dp;
|
|
|
|
ctx->dq = dma_zalloc_coherent(dev, half_key_sz, &ctx->dma_dq,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!ctx->dq)
|
|
|
|
goto free_dp;
|
|
|
|
memcpy(ctx->dq + (half_key_sz - len), ptr, len);
|
|
|
|
|
|
|
|
/* qinv */
|
|
|
|
ptr = rsa_key->qinv;
|
|
|
|
len = rsa_key->qinv_sz;
|
|
|
|
qat_rsa_drop_leading_zeros(&ptr, &len);
|
|
|
|
if (!len)
|
|
|
|
goto free_dq;
|
|
|
|
ctx->qinv = dma_zalloc_coherent(dev, half_key_sz, &ctx->dma_qinv,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!ctx->qinv)
|
|
|
|
goto free_dq;
|
|
|
|
memcpy(ctx->qinv + (half_key_sz - len), ptr, len);
|
|
|
|
|
|
|
|
ctx->crt_mode = true;
|
|
|
|
return;
|
|
|
|
|
|
|
|
free_dq:
|
|
|
|
memset(ctx->dq, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->dq, ctx->dma_dq);
|
|
|
|
ctx->dq = NULL;
|
|
|
|
free_dp:
|
|
|
|
memset(ctx->dp, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->dp, ctx->dma_dp);
|
|
|
|
ctx->dp = NULL;
|
|
|
|
free_q:
|
|
|
|
memset(ctx->q, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->q, ctx->dma_q);
|
|
|
|
ctx->q = NULL;
|
|
|
|
free_p:
|
|
|
|
memset(ctx->p, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->p, ctx->dma_p);
|
|
|
|
ctx->p = NULL;
|
|
|
|
err:
|
|
|
|
ctx->crt_mode = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qat_rsa_clear_ctx(struct device *dev, struct qat_rsa_ctx *ctx)
|
|
|
|
{
|
|
|
|
unsigned int half_key_sz = ctx->key_sz / 2;
|
2015-07-16 06:28:38 +08:00
|
|
|
|
|
|
|
/* Free the old key if any */
|
|
|
|
if (ctx->n)
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->n, ctx->dma_n);
|
|
|
|
if (ctx->e)
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->e, ctx->dma_e);
|
|
|
|
if (ctx->d) {
|
|
|
|
memset(ctx->d, '\0', ctx->key_sz);
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->d, ctx->dma_d);
|
|
|
|
}
|
2016-07-05 00:21:40 +08:00
|
|
|
if (ctx->p) {
|
|
|
|
memset(ctx->p, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->p, ctx->dma_p);
|
|
|
|
}
|
|
|
|
if (ctx->q) {
|
|
|
|
memset(ctx->q, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->q, ctx->dma_q);
|
|
|
|
}
|
|
|
|
if (ctx->dp) {
|
|
|
|
memset(ctx->dp, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->dp, ctx->dma_dp);
|
|
|
|
}
|
|
|
|
if (ctx->dq) {
|
|
|
|
memset(ctx->dq, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->dq, ctx->dma_dq);
|
|
|
|
}
|
|
|
|
if (ctx->qinv) {
|
|
|
|
memset(ctx->qinv, '\0', half_key_sz);
|
|
|
|
dma_free_coherent(dev, half_key_sz, ctx->qinv, ctx->dma_qinv);
|
|
|
|
}
|
2015-07-16 06:28:38 +08:00
|
|
|
|
|
|
|
ctx->n = NULL;
|
|
|
|
ctx->e = NULL;
|
|
|
|
ctx->d = NULL;
|
2016-07-05 00:21:40 +08:00
|
|
|
ctx->p = NULL;
|
|
|
|
ctx->q = NULL;
|
|
|
|
ctx->dp = NULL;
|
|
|
|
ctx->dq = NULL;
|
|
|
|
ctx->qinv = NULL;
|
|
|
|
ctx->crt_mode = false;
|
|
|
|
ctx->key_sz = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qat_rsa_setkey(struct crypto_akcipher *tfm, const void *key,
|
|
|
|
unsigned int keylen, bool private)
|
|
|
|
{
|
|
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
|
|
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
|
|
|
|
struct rsa_key rsa_key;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
qat_rsa_clear_ctx(dev, ctx);
|
2015-10-09 00:26:55 +08:00
|
|
|
|
|
|
|
if (private)
|
2016-07-04 17:49:28 +08:00
|
|
|
ret = rsa_parse_priv_key(&rsa_key, key, keylen);
|
2015-10-09 00:26:55 +08:00
|
|
|
else
|
2016-07-04 17:49:28 +08:00
|
|
|
ret = rsa_parse_pub_key(&rsa_key, key, keylen);
|
|
|
|
if (ret < 0)
|
|
|
|
goto free;
|
|
|
|
|
|
|
|
ret = qat_rsa_set_n(ctx, rsa_key.n, rsa_key.n_sz);
|
2015-07-16 06:28:38 +08:00
|
|
|
if (ret < 0)
|
|
|
|
goto free;
|
2016-07-04 17:49:28 +08:00
|
|
|
ret = qat_rsa_set_e(ctx, rsa_key.e, rsa_key.e_sz);
|
|
|
|
if (ret < 0)
|
|
|
|
goto free;
|
|
|
|
if (private) {
|
|
|
|
ret = qat_rsa_set_d(ctx, rsa_key.d, rsa_key.d_sz);
|
|
|
|
if (ret < 0)
|
|
|
|
goto free;
|
2016-07-05 00:21:40 +08:00
|
|
|
qat_rsa_setkey_crt(ctx, &rsa_key);
|
2016-07-04 17:49:28 +08:00
|
|
|
}
|
2015-07-16 06:28:38 +08:00
|
|
|
|
|
|
|
if (!ctx->n || !ctx->e) {
|
|
|
|
/* invalid key provided */
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto free;
|
|
|
|
}
|
2015-10-09 00:26:55 +08:00
|
|
|
if (private && !ctx->d) {
|
|
|
|
/* invalid private key provided */
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto free;
|
|
|
|
}
|
2015-07-16 06:28:38 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
free:
|
2016-07-05 00:21:40 +08:00
|
|
|
qat_rsa_clear_ctx(dev, ctx);
|
2015-07-16 06:28:38 +08:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-10-09 00:26:55 +08:00
|
|
|
static int qat_rsa_setpubkey(struct crypto_akcipher *tfm, const void *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
|
|
|
return qat_rsa_setkey(tfm, key, keylen, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int qat_rsa_setprivkey(struct crypto_akcipher *tfm, const void *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
|
|
|
return qat_rsa_setkey(tfm, key, keylen, true);
|
|
|
|
}
|
|
|
|
|
2017-05-25 15:18:15 +08:00
|
|
|
static unsigned int qat_rsa_max_size(struct crypto_akcipher *tfm)
|
2015-10-09 00:26:55 +08:00
|
|
|
{
|
|
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
|
|
|
2017-05-25 15:18:15 +08:00
|
|
|
return ctx->key_sz;
|
2015-10-09 00:26:55 +08:00
|
|
|
}
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
static int qat_rsa_init_tfm(struct crypto_akcipher *tfm)
|
|
|
|
{
|
|
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
|
|
struct qat_crypto_instance *inst =
|
|
|
|
qat_crypto_get_instance_node(get_current_node());
|
|
|
|
|
|
|
|
if (!inst)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
ctx->key_sz = 0;
|
|
|
|
ctx->inst = inst;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void qat_rsa_exit_tfm(struct crypto_akcipher *tfm)
|
|
|
|
{
|
|
|
|
struct qat_rsa_ctx *ctx = akcipher_tfm_ctx(tfm);
|
|
|
|
struct device *dev = &GET_DEV(ctx->inst->accel_dev);
|
|
|
|
|
|
|
|
if (ctx->n)
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->n, ctx->dma_n);
|
|
|
|
if (ctx->e)
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->e, ctx->dma_e);
|
|
|
|
if (ctx->d) {
|
|
|
|
memset(ctx->d, '\0', ctx->key_sz);
|
|
|
|
dma_free_coherent(dev, ctx->key_sz, ctx->d, ctx->dma_d);
|
|
|
|
}
|
|
|
|
qat_crypto_put_instance(ctx->inst);
|
|
|
|
ctx->n = NULL;
|
2016-03-23 23:06:40 +08:00
|
|
|
ctx->e = NULL;
|
2015-07-16 06:28:38 +08:00
|
|
|
ctx->d = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct akcipher_alg rsa = {
|
|
|
|
.encrypt = qat_rsa_enc,
|
|
|
|
.decrypt = qat_rsa_dec,
|
|
|
|
.sign = qat_rsa_dec,
|
|
|
|
.verify = qat_rsa_enc,
|
2015-10-09 00:26:55 +08:00
|
|
|
.set_pub_key = qat_rsa_setpubkey,
|
|
|
|
.set_priv_key = qat_rsa_setprivkey,
|
|
|
|
.max_size = qat_rsa_max_size,
|
2015-07-16 06:28:38 +08:00
|
|
|
.init = qat_rsa_init_tfm,
|
|
|
|
.exit = qat_rsa_exit_tfm,
|
2016-07-07 22:27:29 +08:00
|
|
|
.reqsize = sizeof(struct qat_asym_request) + 64,
|
2015-07-16 06:28:38 +08:00
|
|
|
.base = {
|
|
|
|
.cra_name = "rsa",
|
|
|
|
.cra_driver_name = "qat-rsa",
|
|
|
|
.cra_priority = 1000,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_ctxsize = sizeof(struct qat_rsa_ctx),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2016-07-07 22:27:29 +08:00
|
|
|
static struct kpp_alg dh = {
|
|
|
|
.set_secret = qat_dh_set_secret,
|
|
|
|
.generate_public_key = qat_dh_compute_value,
|
|
|
|
.compute_shared_secret = qat_dh_compute_value,
|
|
|
|
.max_size = qat_dh_max_size,
|
|
|
|
.init = qat_dh_init_tfm,
|
|
|
|
.exit = qat_dh_exit_tfm,
|
|
|
|
.reqsize = sizeof(struct qat_asym_request) + 64,
|
|
|
|
.base = {
|
|
|
|
.cra_name = "dh",
|
|
|
|
.cra_driver_name = "qat-dh",
|
|
|
|
.cra_priority = 1000,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
.cra_ctxsize = sizeof(struct qat_dh_ctx),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2015-07-16 06:28:38 +08:00
|
|
|
int qat_asym_algs_register(void)
|
|
|
|
{
|
2015-07-22 13:07:47 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
mutex_lock(&algs_lock);
|
|
|
|
if (++active_devs == 1) {
|
|
|
|
rsa.base.cra_flags = 0;
|
|
|
|
ret = crypto_register_akcipher(&rsa);
|
2016-07-07 22:27:29 +08:00
|
|
|
if (ret)
|
|
|
|
goto unlock;
|
|
|
|
ret = crypto_register_kpp(&dh);
|
2015-07-22 13:07:47 +08:00
|
|
|
}
|
2016-07-07 22:27:29 +08:00
|
|
|
unlock:
|
2015-07-22 13:07:47 +08:00
|
|
|
mutex_unlock(&algs_lock);
|
|
|
|
return ret;
|
2015-07-16 06:28:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void qat_asym_algs_unregister(void)
|
|
|
|
{
|
2015-07-22 13:07:47 +08:00
|
|
|
mutex_lock(&algs_lock);
|
2016-07-07 22:27:29 +08:00
|
|
|
if (--active_devs == 0) {
|
2015-07-22 13:07:47 +08:00
|
|
|
crypto_unregister_akcipher(&rsa);
|
2016-07-07 22:27:29 +08:00
|
|
|
crypto_unregister_kpp(&dh);
|
|
|
|
}
|
2015-07-22 13:07:47 +08:00
|
|
|
mutex_unlock(&algs_lock);
|
2015-07-16 06:28:38 +08:00
|
|
|
}
|