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linux/arch/arm/mach-uniphier/headsmp.S

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ARM: uniphier: rework SMP operations to use trampoline code The complexity of the boot sequence of UniPhier SoC family is a PITA due to the following hardware limitations: [1] No dedicated on-chip SRAM SoCs in general have small SRAM, on which a tiny firmware or a boot loader can run before SDRAM is initialized. As UniPhier SoCs do not have any dedicated SRAM accessible from CPUs, the locked outer cache is used instead. Due to the ARM specification, to have access to the outer cache, the MMU must be enabled. This is done for all CPU cores by the program hard-wired in the boot ROM. The boot ROM code loads a small amount of program (this is usually SPL of U-Boot) from a non-volatile device onto the locked outer cache, and the primary CPU jumps to it. The secondary CPUs stay in the boot ROM until they are kicked by the primary CPU. [2] CPUs can not directly jump to SDRAM address space As mentioned above, the MMU is enable for all the CPUs with the page table hard-wired in the boot ROM. Unfortunately, the page table only has minimal sets of valid sections; all the sections of SDRAM address space are zero-filled. That means all the CPUs, including secondary ones, can not jump directly to SDRAM address space. So, the primary CPU must bring up secondary CPUs to accessible address mapped onto the outer cache, then again kick them to SDRAM address space. Before this commit, this complex task was done with help of a boot loader (U-Boot); U-Boot SPL brings up the secondary CPUs to the entry of U-Boot SPL and they stay there until they are kicked by Linux. This is not nice because a boot loader must put the secondary CPUs into a certain state expected by the kernel. It makes difficult to port another boot loader because the boot loader and the kernel must work in sync to wake up the secondary CPUs. This commit reworks the SMP operations so that they do not rely on particular boot loader implementation; the SMP operations (platsmp.c) put trampoline code (headsmp.S) on a locked way of the outer cache. The secondary CPUs jump from the boot ROM to secondary_entry via the trampoline code. The boot loader no longer needs to take care of SMP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-02 12:42:20 +08:00
/*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/cp15.h>
ENTRY(uniphier_smp_trampoline)
ARM_BE8(setend be) @ ensure we are in BE8 mode
mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
and r2, r0, #0x3 @ CPU ID
ldr r1, uniphier_smp_trampoline_jump
ldr r3, uniphier_smp_trampoline_poll_addr
mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
orr r0, r0, #CR_I @ Enable ICache
bic r0, r0, #(CR_C | CR_M) @ Disable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
b 1f @ cache the following 5 instructions
0: wfe
1: ldr r0, [r3]
cmp r0, r2
bxeq r1 @ branch to secondary_startup
b 0b
.globl uniphier_smp_trampoline_jump
uniphier_smp_trampoline_jump:
.word 0 @ set virt_to_phys(secondary_startup)
.globl uniphier_smp_trampoline_poll_addr
uniphier_smp_trampoline_poll_addr:
.word 0 @ set CPU ID to be kicked to this reg
.globl uniphier_smp_trampoline_end
uniphier_smp_trampoline_end:
ENDPROC(uniphier_smp_trampoline)