2020-02-26 01:35:34 +08:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2021-01-30 21:08:40 +08:00
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#include <linux/context_tracking.h>
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2020-02-26 01:35:34 +08:00
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#include <linux/err.h>
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2021-02-08 23:10:29 +08:00
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#include <linux/compat.h>
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2020-02-26 01:35:34 +08:00
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#include <asm/asm-prototypes.h>
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2020-11-19 20:43:53 +08:00
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#include <asm/kup.h>
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2020-02-26 01:35:34 +08:00
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#include <asm/cputime.h>
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2021-01-30 21:08:40 +08:00
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#include <asm/interrupt.h>
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2020-02-26 01:35:34 +08:00
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#include <asm/hw_irq.h>
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2021-01-30 21:08:38 +08:00
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#include <asm/interrupt.h>
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2020-02-26 01:35:34 +08:00
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#include <asm/kprobes.h>
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#include <asm/paca.h>
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#include <asm/ptrace.h>
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#include <asm/reg.h>
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#include <asm/signal.h>
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#include <asm/switch_to.h>
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#include <asm/syscall.h>
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#include <asm/time.h>
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#include <asm/unistd.h>
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typedef long (*syscall_fn)(long, long, long, long, long, long);
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2020-02-26 01:35:39 +08:00
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/* Has to run notrace because it is entered not completely "reconciled" */
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notrace long system_call_exception(long r3, long r4, long r5,
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long r6, long r7, long r8,
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unsigned long r0, struct pt_regs *regs)
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2020-02-26 01:35:34 +08:00
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{
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syscall_fn f;
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2021-02-08 23:10:30 +08:00
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regs->orig_gpr3 = r3;
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2020-02-26 01:35:39 +08:00
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if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
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BUG_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED);
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2021-01-30 21:08:40 +08:00
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CT_WARN_ON(ct_state() == CONTEXT_KERNEL);
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user_exit_irqoff();
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2020-02-26 01:35:39 +08:00
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trace_hardirqs_off(); /* finish reconciling */
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2021-02-08 23:10:31 +08:00
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if (!IS_ENABLED(CONFIG_BOOKE) && !IS_ENABLED(CONFIG_40x))
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powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
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BUG_ON(!(regs->msr & MSR_RI));
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2020-02-26 01:35:34 +08:00
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BUG_ON(!(regs->msr & MSR_PR));
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powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
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BUG_ON(!FULL_REGS(regs));
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2021-02-08 23:10:28 +08:00
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BUG_ON(arch_irq_disabled_regs(regs));
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2020-02-26 01:35:34 +08:00
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2020-11-27 12:44:12 +08:00
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#ifdef CONFIG_PPC_PKEY
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if (mmu_has_feature(MMU_FTR_PKEY)) {
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unsigned long amr, iamr;
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2020-11-27 12:44:24 +08:00
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bool flush_needed = false;
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2020-11-27 12:44:12 +08:00
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/*
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* When entering from userspace we mostly have the AMR/IAMR
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* different from kernel default values. Hence don't compare.
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*/
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amr = mfspr(SPRN_AMR);
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iamr = mfspr(SPRN_IAMR);
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regs->amr = amr;
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regs->iamr = iamr;
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2020-11-27 12:44:24 +08:00
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if (mmu_has_feature(MMU_FTR_BOOK3S_KUAP)) {
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2020-11-27 12:44:12 +08:00
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mtspr(SPRN_AMR, AMR_KUAP_BLOCKED);
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2020-11-27 12:44:24 +08:00
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flush_needed = true;
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}
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if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) {
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2020-11-27 12:44:12 +08:00
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mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED);
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2020-11-27 12:44:24 +08:00
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flush_needed = true;
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}
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if (flush_needed)
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isync();
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2020-11-27 12:44:12 +08:00
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} else
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#endif
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2021-02-08 23:10:28 +08:00
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#ifdef CONFIG_PPC64
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2020-11-27 12:44:12 +08:00
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kuap_check_amr();
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2021-02-08 23:10:28 +08:00
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#endif
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2020-04-29 14:56:49 +08:00
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2021-02-10 03:29:28 +08:00
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booke_restore_dbcr0();
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2020-02-26 01:35:34 +08:00
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account_cpu_user_entry();
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2021-01-30 21:08:47 +08:00
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account_stolen_time();
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2020-02-26 01:35:34 +08:00
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/*
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* This is not required for the syscall exit path, but makes the
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* stack frame look nicer. If this was initialised in the first stack
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* frame, or if the unwinder was taught the first stack frame always
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* returns to user with IRQS_ENABLED, this store could be avoided!
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*/
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2021-02-08 23:10:28 +08:00
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irq_soft_mask_regs_set_state(regs, IRQS_ENABLED);
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2020-02-26 01:35:34 +08:00
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2020-02-26 01:35:39 +08:00
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local_irq_enable();
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2020-02-26 01:35:34 +08:00
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2020-03-20 18:20:16 +08:00
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if (unlikely(current_thread_info()->flags & _TIF_SYSCALL_DOTRACE)) {
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2021-02-10 03:29:27 +08:00
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if (unlikely(trap_is_unsupported_scv(regs))) {
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2020-06-11 16:12:03 +08:00
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/* Unsupported scv vector */
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_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
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return regs->gpr[3];
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}
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2020-02-26 01:35:34 +08:00
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/*
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* We use the return value of do_syscall_trace_enter() as the
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* syscall number. If the syscall was rejected for any reason
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* do_syscall_trace_enter() returns an invalid syscall number
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* and the test against NR_syscalls will fail and the return
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* value to be used is in regs->gpr[3].
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*/
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r0 = do_syscall_trace_enter(regs);
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if (unlikely(r0 >= NR_syscalls))
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return regs->gpr[3];
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r3 = regs->gpr[3];
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r4 = regs->gpr[4];
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r5 = regs->gpr[5];
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r6 = regs->gpr[6];
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r7 = regs->gpr[7];
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r8 = regs->gpr[8];
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} else if (unlikely(r0 >= NR_syscalls)) {
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2021-02-10 03:29:27 +08:00
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if (unlikely(trap_is_unsupported_scv(regs))) {
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2020-06-11 16:12:03 +08:00
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/* Unsupported scv vector */
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_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
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return regs->gpr[3];
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}
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2020-02-26 01:35:34 +08:00
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return -ENOSYS;
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}
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/* May be faster to do array_index_nospec? */
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barrier_nospec();
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2021-02-08 23:10:29 +08:00
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if (unlikely(is_compat_task())) {
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2020-02-26 01:35:34 +08:00
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f = (void *)compat_sys_call_table[r0];
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r3 &= 0x00000000ffffffffULL;
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r4 &= 0x00000000ffffffffULL;
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r5 &= 0x00000000ffffffffULL;
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r6 &= 0x00000000ffffffffULL;
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r7 &= 0x00000000ffffffffULL;
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r8 &= 0x00000000ffffffffULL;
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} else {
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f = (void *)sys_call_table[r0];
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}
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return f(r3, r4, r5, r6, r7, r8);
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}
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2020-04-29 14:24:21 +08:00
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/*
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* local irqs must be disabled. Returns false if the caller must re-enable
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* them, check for new work, and try again.
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2021-01-30 21:08:11 +08:00
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*
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* This should be called with local irqs disabled, but if they were previously
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* enabled when the interrupt handler returns (indicating a process-context /
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* synchronous interrupt) then irqs_enabled should be true.
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2020-04-29 14:24:21 +08:00
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*/
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2021-01-30 21:08:40 +08:00
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static notrace inline bool __prep_irq_for_enabled_exit(bool clear_ri)
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2020-04-29 14:24:21 +08:00
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{
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/* This must be done with RI=1 because tracing may touch vmaps */
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trace_hardirqs_on();
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/* This pattern matches prep_irq_for_idle */
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2020-06-11 16:12:03 +08:00
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if (clear_ri)
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__hard_EE_RI_disable();
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else
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__hard_irq_disable();
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2021-02-08 23:10:28 +08:00
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#ifdef CONFIG_PPC64
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2020-04-29 14:24:21 +08:00
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if (unlikely(lazy_irq_pending_nocheck())) {
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/* Took an interrupt, may have more exit work to do. */
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2020-06-11 16:12:03 +08:00
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if (clear_ri)
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__hard_RI_enable();
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2020-04-29 14:24:21 +08:00
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trace_hardirqs_off();
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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return false;
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}
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local_paca->irq_happened = 0;
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irq_soft_mask_set(IRQS_ENABLED);
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2021-02-08 23:10:28 +08:00
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#endif
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2020-04-29 14:24:21 +08:00
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return true;
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}
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2021-01-30 21:08:40 +08:00
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static notrace inline bool prep_irq_for_enabled_exit(bool clear_ri, bool irqs_enabled)
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{
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if (__prep_irq_for_enabled_exit(clear_ri))
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return true;
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/*
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* Must replay pending soft-masked interrupts now. Don't just
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* local_irq_enabe(); local_irq_disable(); because if we are
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* returning from an asynchronous interrupt here, another one
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* might hit after irqs are enabled, and it would exit via this
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* same path allowing another to fire, and so on unbounded.
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*
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* If interrupts were enabled when this interrupt exited,
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* indicating a process context (synchronous) interrupt,
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* local_irq_enable/disable can be used, which will enable
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* interrupts rather than keeping them masked (unclear how
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* much benefit this is over just replaying for all cases,
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* because we immediately disable again, so all we're really
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* doing is allowing hard interrupts to execute directly for
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* a very small time, rather than being masked and replayed).
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*/
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if (irqs_enabled) {
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local_irq_enable();
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local_irq_disable();
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} else {
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replay_soft_interrupts();
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}
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return false;
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}
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2021-02-10 03:29:28 +08:00
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static notrace void booke_load_dbcr0(void)
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{
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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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unsigned long dbcr0 = current->thread.debug.dbcr0;
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if (likely(!(dbcr0 & DBCR0_IDM)))
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return;
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/*
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* Check to see if the dbcr0 register is set up to debug.
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* Use the internal debug mode bit to do this.
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*/
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mtmsr(mfmsr() & ~MSR_DE);
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if (IS_ENABLED(CONFIG_PPC32)) {
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isync();
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global_dbcr0[smp_processor_id()] = mfspr(SPRN_DBCR0);
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}
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mtspr(SPRN_DBCR0, dbcr0);
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mtspr(SPRN_DBSR, -1);
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#endif
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}
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2020-02-26 01:35:34 +08:00
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/*
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* This should be called after a syscall returns, with r3 the return value
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* from the syscall. If this function returns non-zero, the system call
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* exit assembly should additionally load all GPR registers and CTR and XER
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* from the interrupt frame.
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*
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* The function graph tracer can not trace the return side of this function,
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* because RI=0 and soft mask state is "unreconciled", so it is marked notrace.
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*/
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|
|
notrace unsigned long syscall_exit_prepare(unsigned long r3,
|
2020-06-11 16:12:03 +08:00
|
|
|
struct pt_regs *regs,
|
|
|
|
|
long scv)
|
2020-02-26 01:35:34 +08:00
|
|
|
{
|
|
|
|
|
unsigned long *ti_flagsp = ¤t_thread_info()->flags;
|
|
|
|
|
unsigned long ti_flags;
|
|
|
|
|
unsigned long ret = 0;
|
2021-02-10 03:29:27 +08:00
|
|
|
bool is_not_scv = !IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !scv;
|
2020-02-26 01:35:34 +08:00
|
|
|
|
2021-01-30 21:08:40 +08:00
|
|
|
CT_WARN_ON(ct_state() == CONTEXT_USER);
|
|
|
|
|
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
2020-04-29 14:56:49 +08:00
|
|
|
kuap_check_amr();
|
2021-02-08 23:10:28 +08:00
|
|
|
#endif
|
2020-04-29 14:56:49 +08:00
|
|
|
|
2020-02-26 01:35:34 +08:00
|
|
|
regs->result = r3;
|
|
|
|
|
|
|
|
|
|
/* Check whether the syscall is issued inside a restartable sequence */
|
|
|
|
|
rseq_syscall(regs);
|
|
|
|
|
|
|
|
|
|
ti_flags = *ti_flagsp;
|
|
|
|
|
|
2021-02-10 03:29:27 +08:00
|
|
|
if (unlikely(r3 >= (unsigned long)-MAX_ERRNO) && is_not_scv) {
|
2020-02-26 01:35:34 +08:00
|
|
|
if (likely(!(ti_flags & (_TIF_NOERROR | _TIF_RESTOREALL)))) {
|
|
|
|
|
r3 = -r3;
|
|
|
|
|
regs->ccr |= 0x10000000; /* Set SO bit in CR */
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (unlikely(ti_flags & _TIF_PERSYSCALL_MASK)) {
|
|
|
|
|
if (ti_flags & _TIF_RESTOREALL)
|
|
|
|
|
ret = _TIF_RESTOREALL;
|
|
|
|
|
else
|
|
|
|
|
regs->gpr[3] = r3;
|
|
|
|
|
clear_bits(_TIF_PERSYSCALL_MASK, ti_flagsp);
|
|
|
|
|
} else {
|
|
|
|
|
regs->gpr[3] = r3;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (unlikely(ti_flags & _TIF_SYSCALL_DOTRACE)) {
|
|
|
|
|
do_syscall_trace_leave(regs);
|
|
|
|
|
ret |= _TIF_RESTOREALL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
local_irq_disable();
|
2021-01-30 21:08:11 +08:00
|
|
|
|
2021-01-30 21:08:45 +08:00
|
|
|
again:
|
2020-02-26 01:35:34 +08:00
|
|
|
ti_flags = READ_ONCE(*ti_flagsp);
|
|
|
|
|
while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) {
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
if (ti_flags & _TIF_NEED_RESCHED) {
|
|
|
|
|
schedule();
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* SIGPENDING must restore signal handler function
|
|
|
|
|
* argument GPRs, and some non-volatiles (e.g., r1).
|
|
|
|
|
* Restore all for now. This could be made lighter.
|
|
|
|
|
*/
|
|
|
|
|
if (ti_flags & _TIF_SIGPENDING)
|
|
|
|
|
ret |= _TIF_RESTOREALL;
|
|
|
|
|
do_notify_resume(regs, ti_flags);
|
|
|
|
|
}
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
ti_flags = READ_ONCE(*ti_flagsp);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && IS_ENABLED(CONFIG_PPC_FPU)) {
|
|
|
|
|
if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) &&
|
|
|
|
|
unlikely((ti_flags & _TIF_RESTORE_TM))) {
|
|
|
|
|
restore_tm_state(regs);
|
|
|
|
|
} else {
|
|
|
|
|
unsigned long mathflags = MSR_FP;
|
|
|
|
|
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_VSX))
|
|
|
|
|
mathflags |= MSR_VEC | MSR_VSX;
|
|
|
|
|
else if (cpu_has_feature(CPU_FTR_ALTIVEC))
|
|
|
|
|
mathflags |= MSR_VEC;
|
|
|
|
|
|
powerpc/64s: Fix restore_math unnecessarily changing MSR
Before returning to user, if there are missing FP/VEC/VSX bits from the
user MSR then those registers had been saved and must be restored again
before use. restore_math will decide whether to restore immediately, or
skip the restore and let fp/vec/vsx unavailable faults demand load the
registers.
Each time restore_math restores one of the FP/VSX or VEC register sets
is loaded, an 8-bit counter is incremented (load_fp and load_vec). When
these wrap to zero, restore_math no longer restores that register set
until after they are next demand faulted.
It's quite usual for those counters to have different values, so if one
wraps to zero and restore_math no longer restores its registers or user
MSR bit but the other is not zero yet does not need to be restored
(because the kernel is not frequently using the FPU), then restore_math
will be called and it will also not return in the early exit check.
This causes msr_check_and_set to test and set the MSR at every kernel
exit despite having no work to do.
This can cause workloads (e.g., a NULL syscall microbenchmark) to run
fast for a time while both counters are non-zero, then slow down when
one of the counters reaches zero, then speed up again after the second
counter reaches zero. The cost is significant, about 10% slowdown on a
NULL syscall benchmark, and the jittery behaviour is very undesirable.
Fix this by having restore_math test all conditions first, and only
update MSR if we will be loading registers.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200623234139.2262227-2-npiggin@gmail.com
2020-06-24 07:41:38 +08:00
|
|
|
/*
|
|
|
|
|
* If userspace MSR has all available FP bits set,
|
|
|
|
|
* then they are live and no need to restore. If not,
|
|
|
|
|
* it means the regs were given up and restore_math
|
|
|
|
|
* may decide to restore them (to avoid taking an FP
|
|
|
|
|
* fault).
|
|
|
|
|
*/
|
2020-02-26 01:35:34 +08:00
|
|
|
if ((regs->msr & mathflags) != mathflags)
|
|
|
|
|
restore_math(regs);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-01-30 21:08:40 +08:00
|
|
|
user_enter_irqoff();
|
|
|
|
|
|
2020-06-11 16:12:03 +08:00
|
|
|
/* scv need not set RI=0 because SRRs are not used */
|
2021-02-10 03:29:27 +08:00
|
|
|
if (unlikely(!__prep_irq_for_enabled_exit(is_not_scv))) {
|
2021-01-30 21:08:40 +08:00
|
|
|
user_exit_irqoff();
|
|
|
|
|
local_irq_enable();
|
2021-01-30 21:08:45 +08:00
|
|
|
local_irq_disable();
|
2020-02-26 01:35:34 +08:00
|
|
|
goto again;
|
2021-01-30 21:08:40 +08:00
|
|
|
}
|
2020-02-26 01:35:34 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
|
|
|
|
local_paca->tm_scratch = regs->msr;
|
|
|
|
|
#endif
|
|
|
|
|
|
2021-02-10 03:29:28 +08:00
|
|
|
booke_load_dbcr0();
|
|
|
|
|
|
2020-02-26 01:35:34 +08:00
|
|
|
account_cpu_user_exit();
|
|
|
|
|
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64 /* BOOK3E and ppc32 not using this */
|
2020-11-27 12:44:12 +08:00
|
|
|
/*
|
|
|
|
|
* We do this at the end so that we do context switch with KERNEL AMR
|
|
|
|
|
*/
|
|
|
|
|
kuap_user_restore(regs);
|
|
|
|
|
#endif
|
2020-02-26 01:35:34 +08:00
|
|
|
return ret;
|
|
|
|
|
}
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifndef CONFIG_PPC_BOOK3E_64 /* BOOK3E not yet using this */
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs, unsigned long msr)
|
|
|
|
|
{
|
|
|
|
|
unsigned long *ti_flagsp = ¤t_thread_info()->flags;
|
|
|
|
|
unsigned long ti_flags;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
unsigned long ret = 0;
|
|
|
|
|
|
2021-02-08 23:10:31 +08:00
|
|
|
if (!IS_ENABLED(CONFIG_BOOKE) && !IS_ENABLED(CONFIG_40x))
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
BUG_ON(!(regs->msr & MSR_RI));
|
|
|
|
|
BUG_ON(!(regs->msr & MSR_PR));
|
|
|
|
|
BUG_ON(!FULL_REGS(regs));
|
2021-02-08 23:10:28 +08:00
|
|
|
BUG_ON(arch_irq_disabled_regs(regs));
|
2021-01-30 21:08:45 +08:00
|
|
|
CT_WARN_ON(ct_state() == CONTEXT_USER);
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
|
2020-04-29 14:56:51 +08:00
|
|
|
/*
|
|
|
|
|
* We don't need to restore AMR on the way back to userspace for KUAP.
|
|
|
|
|
* AMR can only have been unlocked if we interrupted the kernel.
|
|
|
|
|
*/
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
2020-04-29 14:56:49 +08:00
|
|
|
kuap_check_amr();
|
2021-02-08 23:10:28 +08:00
|
|
|
#endif
|
2020-04-29 14:56:49 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
local_irq_save(flags);
|
|
|
|
|
|
|
|
|
|
again:
|
|
|
|
|
ti_flags = READ_ONCE(*ti_flagsp);
|
|
|
|
|
while (unlikely(ti_flags & (_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM))) {
|
|
|
|
|
local_irq_enable(); /* returning to user: may enable */
|
|
|
|
|
if (ti_flags & _TIF_NEED_RESCHED) {
|
|
|
|
|
schedule();
|
|
|
|
|
} else {
|
|
|
|
|
if (ti_flags & _TIF_SIGPENDING)
|
|
|
|
|
ret |= _TIF_RESTOREALL;
|
|
|
|
|
do_notify_resume(regs, ti_flags);
|
|
|
|
|
}
|
|
|
|
|
local_irq_disable();
|
|
|
|
|
ti_flags = READ_ONCE(*ti_flagsp);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_PPC_BOOK3S) && IS_ENABLED(CONFIG_PPC_FPU)) {
|
|
|
|
|
if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) &&
|
|
|
|
|
unlikely((ti_flags & _TIF_RESTORE_TM))) {
|
|
|
|
|
restore_tm_state(regs);
|
|
|
|
|
} else {
|
|
|
|
|
unsigned long mathflags = MSR_FP;
|
|
|
|
|
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_VSX))
|
|
|
|
|
mathflags |= MSR_VEC | MSR_VSX;
|
|
|
|
|
else if (cpu_has_feature(CPU_FTR_ALTIVEC))
|
|
|
|
|
mathflags |= MSR_VEC;
|
|
|
|
|
|
powerpc/64s: Fix restore_math unnecessarily changing MSR
Before returning to user, if there are missing FP/VEC/VSX bits from the
user MSR then those registers had been saved and must be restored again
before use. restore_math will decide whether to restore immediately, or
skip the restore and let fp/vec/vsx unavailable faults demand load the
registers.
Each time restore_math restores one of the FP/VSX or VEC register sets
is loaded, an 8-bit counter is incremented (load_fp and load_vec). When
these wrap to zero, restore_math no longer restores that register set
until after they are next demand faulted.
It's quite usual for those counters to have different values, so if one
wraps to zero and restore_math no longer restores its registers or user
MSR bit but the other is not zero yet does not need to be restored
(because the kernel is not frequently using the FPU), then restore_math
will be called and it will also not return in the early exit check.
This causes msr_check_and_set to test and set the MSR at every kernel
exit despite having no work to do.
This can cause workloads (e.g., a NULL syscall microbenchmark) to run
fast for a time while both counters are non-zero, then slow down when
one of the counters reaches zero, then speed up again after the second
counter reaches zero. The cost is significant, about 10% slowdown on a
NULL syscall benchmark, and the jittery behaviour is very undesirable.
Fix this by having restore_math test all conditions first, and only
update MSR if we will be loading registers.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200623234139.2262227-2-npiggin@gmail.com
2020-06-24 07:41:38 +08:00
|
|
|
/* See above restore_math comment */
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
if ((regs->msr & mathflags) != mathflags)
|
|
|
|
|
restore_math(regs);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-01-30 21:08:45 +08:00
|
|
|
user_enter_irqoff();
|
|
|
|
|
|
|
|
|
|
if (unlikely(!__prep_irq_for_enabled_exit(true))) {
|
|
|
|
|
user_exit_irqoff();
|
|
|
|
|
local_irq_enable();
|
|
|
|
|
local_irq_disable();
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
goto again;
|
2021-01-30 21:08:45 +08:00
|
|
|
}
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
|
2021-02-10 03:29:28 +08:00
|
|
|
booke_load_dbcr0();
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
|
|
|
|
local_paca->tm_scratch = regs->msr;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
account_cpu_user_exit();
|
|
|
|
|
|
2020-11-27 12:44:12 +08:00
|
|
|
/*
|
|
|
|
|
* We do this at the end so that we do context switch with KERNEL AMR
|
|
|
|
|
*/
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
2020-11-27 12:44:12 +08:00
|
|
|
kuap_user_restore(regs);
|
2021-02-08 23:10:28 +08:00
|
|
|
#endif
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void unrecoverable_exception(struct pt_regs *regs);
|
|
|
|
|
void preempt_schedule_irq(void);
|
|
|
|
|
|
|
|
|
|
notrace unsigned long interrupt_exit_kernel_prepare(struct pt_regs *regs, unsigned long msr)
|
|
|
|
|
{
|
|
|
|
|
unsigned long *ti_flagsp = ¤t_thread_info()->flags;
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
unsigned long ret = 0;
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
2020-04-29 14:56:51 +08:00
|
|
|
unsigned long amr;
|
2021-02-08 23:10:28 +08:00
|
|
|
#endif
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
|
2021-02-08 23:10:31 +08:00
|
|
|
if (!IS_ENABLED(CONFIG_BOOKE) && !IS_ENABLED(CONFIG_40x) &&
|
|
|
|
|
unlikely(!(regs->msr & MSR_RI)))
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
unrecoverable_exception(regs);
|
|
|
|
|
BUG_ON(regs->msr & MSR_PR);
|
|
|
|
|
BUG_ON(!FULL_REGS(regs));
|
2021-01-30 21:08:45 +08:00
|
|
|
/*
|
|
|
|
|
* CT_WARN_ON comes here via program_check_exception,
|
|
|
|
|
* so avoid recursion.
|
|
|
|
|
*/
|
|
|
|
|
if (TRAP(regs) != 0x700)
|
|
|
|
|
CT_WARN_ON(ct_state() == CONTEXT_USER);
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
2020-04-29 14:56:51 +08:00
|
|
|
amr = kuap_get_and_check_amr();
|
2021-02-08 23:10:28 +08:00
|
|
|
#endif
|
2020-04-29 14:56:49 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
if (unlikely(*ti_flagsp & _TIF_EMULATE_STACK_STORE)) {
|
|
|
|
|
clear_bits(_TIF_EMULATE_STACK_STORE, ti_flagsp);
|
|
|
|
|
ret = 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
|
|
2021-02-08 23:10:28 +08:00
|
|
|
if (!arch_irq_disabled_regs(regs)) {
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
/* Returning to a kernel context with local irqs enabled. */
|
|
|
|
|
WARN_ON_ONCE(!(regs->msr & MSR_EE));
|
|
|
|
|
again:
|
|
|
|
|
if (IS_ENABLED(CONFIG_PREEMPT)) {
|
|
|
|
|
/* Return to preemptible kernel context */
|
|
|
|
|
if (unlikely(*ti_flagsp & _TIF_NEED_RESCHED)) {
|
|
|
|
|
if (preempt_count() == 0)
|
|
|
|
|
preempt_schedule_irq();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-01-30 21:08:11 +08:00
|
|
|
if (unlikely(!prep_irq_for_enabled_exit(true, !irqs_disabled_flags(flags))))
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
goto again;
|
|
|
|
|
} else {
|
|
|
|
|
/* Returning to a kernel context with local irqs disabled. */
|
|
|
|
|
__hard_EE_RI_disable();
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
if (regs->msr & MSR_EE)
|
|
|
|
|
local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
|
2021-02-08 23:10:28 +08:00
|
|
|
#endif
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
|
|
|
|
local_paca->tm_scratch = regs->msr;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*
|
2020-04-29 14:56:51 +08:00
|
|
|
* Don't want to mfspr(SPRN_AMR) here, because this comes after mtmsr,
|
|
|
|
|
* which would cause Read-After-Write stalls. Hence, we take the AMR
|
|
|
|
|
* value from the check above.
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
*/
|
2021-02-08 23:10:28 +08:00
|
|
|
#ifdef CONFIG_PPC64
|
2020-11-27 12:44:12 +08:00
|
|
|
kuap_kernel_restore(regs, amr);
|
2021-02-08 23:10:28 +08:00
|
|
|
#endif
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
#endif
|