2009-05-29 04:23:52 +08:00
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/*
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* linux/arch/arm/mach-omap2/gpmc-onenand.c
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*
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* Copyright (C) 2006 - 2009 Nokia Corporation
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* Contacts: Juha Yrjola
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* Tony Lindgren
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2011-07-31 22:52:44 +08:00
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#include <linux/string.h>
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2009-05-29 04:23:52 +08:00
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/onenand_regs.h>
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#include <linux/io.h>
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2012-08-24 21:21:06 +08:00
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#include <linux/platform_data/mtd-onenand-omap2.h>
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2012-06-05 12:41:48 +08:00
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#include <linux/err.h>
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2009-05-29 04:23:52 +08:00
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#include <asm/mach/flash.h>
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2012-10-05 13:07:27 +08:00
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#include "gpmc.h"
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2012-09-01 01:59:07 +08:00
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#include "soc.h"
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2012-09-29 13:02:42 +08:00
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#include "gpmc-onenand.h"
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2012-09-01 01:59:07 +08:00
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2012-08-31 03:53:23 +08:00
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#define ONENAND_IO_SIZE SZ_128K
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2012-06-05 12:41:48 +08:00
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#define ONENAND_FLAG_SYNCREAD (1 << 0)
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#define ONENAND_FLAG_SYNCWRITE (1 << 1)
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#define ONENAND_FLAG_HF (1 << 2)
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#define ONENAND_FLAG_VHF (1 << 3)
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static unsigned onenand_flags;
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static unsigned latency;
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2009-05-29 04:23:52 +08:00
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static struct omap_onenand_platform_data *gpmc_onenand_data;
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2012-08-31 03:53:23 +08:00
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static struct resource gpmc_onenand_resource = {
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.flags = IORESOURCE_MEM,
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};
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2009-05-29 04:23:52 +08:00
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static struct platform_device gpmc_onenand_device = {
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.name = "omap2-onenand",
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.id = -1,
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2012-08-31 03:53:23 +08:00
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.num_resources = 1,
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.resource = &gpmc_onenand_resource,
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2009-05-29 04:23:52 +08:00
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};
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2013-02-22 03:46:22 +08:00
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static struct gpmc_settings onenand_async = {
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2013-02-22 02:42:22 +08:00
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.device_width = GPMC_DEVWIDTH_16BIT,
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2013-02-22 03:46:22 +08:00
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.mux_add_data = GPMC_MUX_AD,
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};
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static struct gpmc_settings onenand_sync = {
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.burst_read = true,
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2013-02-22 02:42:22 +08:00
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.burst_wrap = true,
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.burst_len = GPMC_BURST_16,
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.device_width = GPMC_DEVWIDTH_16BIT,
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2013-02-22 03:46:22 +08:00
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.mux_add_data = GPMC_MUX_AD,
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2013-02-22 02:42:22 +08:00
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.wait_pin = 0,
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2013-02-22 03:46:22 +08:00
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};
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2013-02-22 05:20:53 +08:00
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static void omap2_onenand_calc_async_timings(struct gpmc_timings *t)
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2009-05-29 04:23:52 +08:00
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{
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2012-11-09 20:35:17 +08:00
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struct gpmc_device_timings dev_t;
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2009-05-29 04:23:52 +08:00
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_aavdh = 7;
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const int t_ce = 76;
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const int t_aa = 76;
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const int t_oe = 20;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_wpl = 40;
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const int t_wph = 30;
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2012-11-09 20:35:17 +08:00
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memset(&dev_t, 0, sizeof(dev_t));
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dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;
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dev_t.t_avdp_w = dev_t.t_avdp_r;
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dev_t.t_aavdh = t_aavdh * 1000;
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dev_t.t_aa = t_aa * 1000;
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dev_t.t_ce = t_ce * 1000;
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dev_t.t_oe = t_oe * 1000;
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dev_t.t_cez_r = t_cez * 1000;
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dev_t.t_cez_w = dev_t.t_cez_r;
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dev_t.t_wpl = t_wpl * 1000;
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dev_t.t_wph = t_wph * 1000;
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2013-02-22 03:46:22 +08:00
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gpmc_calc_timings(t, &onenand_async, &dev_t);
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2012-06-05 12:41:48 +08:00
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}
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static void omap2_onenand_set_async_mode(void __iomem *onenand_base)
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{
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u32 reg;
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2009-06-23 18:30:24 +08:00
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/* Ensure sync read and sync write are disabled */
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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2009-05-29 04:23:52 +08:00
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}
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2012-06-05 12:41:48 +08:00
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static void set_onenand_cfg(void __iomem *onenand_base)
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2009-05-29 04:23:52 +08:00
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{
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u32 reg;
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reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
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reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
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reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
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ONENAND_SYS_CFG1_BL_16;
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2012-06-05 12:41:48 +08:00
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if (onenand_flags & ONENAND_FLAG_SYNCREAD)
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2009-05-29 04:23:52 +08:00
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reg |= ONENAND_SYS_CFG1_SYNC_READ;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_READ;
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2012-06-05 12:41:48 +08:00
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if (onenand_flags & ONENAND_FLAG_SYNCWRITE)
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2009-05-29 04:23:52 +08:00
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reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
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else
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reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
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2012-06-05 12:41:48 +08:00
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if (onenand_flags & ONENAND_FLAG_HF)
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2009-05-29 04:23:52 +08:00
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reg |= ONENAND_SYS_CFG1_HF;
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else
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reg &= ~ONENAND_SYS_CFG1_HF;
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2012-06-05 12:41:48 +08:00
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if (onenand_flags & ONENAND_FLAG_VHF)
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2011-02-07 16:46:58 +08:00
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reg |= ONENAND_SYS_CFG1_VHF;
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else
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reg &= ~ONENAND_SYS_CFG1_VHF;
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2009-05-29 04:23:52 +08:00
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writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
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}
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2011-02-07 16:47:00 +08:00
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static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
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2012-06-29 02:41:29 +08:00
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void __iomem *onenand_base)
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2011-02-07 16:47:00 +08:00
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{
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u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
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2012-06-29 02:41:29 +08:00
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int freq;
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2011-02-07 16:47:00 +08:00
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switch ((ver >> 4) & 0xf) {
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case 0:
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freq = 40;
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break;
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case 1:
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freq = 54;
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break;
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case 2:
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freq = 66;
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break;
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case 3:
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freq = 83;
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break;
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case 4:
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freq = 104;
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break;
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default:
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freq = 54;
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break;
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}
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return freq;
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}
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2013-02-22 05:20:53 +08:00
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static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
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unsigned int flags,
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int freq)
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2009-05-29 04:23:52 +08:00
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{
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2012-11-09 20:35:17 +08:00
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struct gpmc_device_timings dev_t;
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2009-05-29 04:23:52 +08:00
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const int t_cer = 15;
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const int t_avdp = 12;
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const int t_cez = 20; /* max of t_cez, t_oez */
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const int t_wpl = 40;
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const int t_wph = 30;
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int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
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2012-11-09 20:35:17 +08:00
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int div, gpmc_clk_ns;
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2009-05-29 04:23:52 +08:00
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2013-02-22 05:20:53 +08:00
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if (flags & ONENAND_SYNC_READ)
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2012-06-05 12:41:48 +08:00
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onenand_flags = ONENAND_FLAG_SYNCREAD;
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2013-02-22 05:20:53 +08:00
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else if (flags & ONENAND_SYNC_READWRITE)
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2012-06-05 12:41:48 +08:00
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onenand_flags = ONENAND_FLAG_SYNCREAD | ONENAND_FLAG_SYNCWRITE;
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2009-05-29 04:23:52 +08:00
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switch (freq) {
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2010-12-09 17:22:50 +08:00
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case 104:
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min_gpmc_clk_period = 9600; /* 104 MHz */
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t_ces = 3;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 3;
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t_aavdh = 6;
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2011-02-07 16:46:58 +08:00
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t_rdyo = 6;
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2010-12-09 17:22:50 +08:00
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break;
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2009-05-29 04:23:52 +08:00
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case 83:
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2010-12-09 16:48:27 +08:00
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min_gpmc_clk_period = 12000; /* 83 MHz */
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2009-05-29 04:23:52 +08:00
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t_ces = 5;
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t_avds = 4;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 9;
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break;
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case 66:
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2010-12-09 16:48:27 +08:00
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min_gpmc_clk_period = 15000; /* 66 MHz */
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2009-05-29 04:23:52 +08:00
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t_ces = 6;
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t_avds = 5;
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t_avdh = 2;
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t_ach = 6;
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t_aavdh = 6;
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t_rdyo = 11;
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break;
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default:
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2010-12-09 16:48:27 +08:00
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min_gpmc_clk_period = 18500; /* 54 MHz */
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2009-05-29 04:23:52 +08:00
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t_ces = 7;
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t_avds = 7;
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t_avdh = 7;
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t_ach = 9;
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t_aavdh = 7;
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t_rdyo = 15;
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2012-06-05 12:41:48 +08:00
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onenand_flags &= ~ONENAND_FLAG_SYNCWRITE;
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2009-05-29 04:23:52 +08:00
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break;
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}
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2012-08-19 20:59:45 +08:00
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div = gpmc_calc_divider(min_gpmc_clk_period);
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2009-05-29 04:23:52 +08:00
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gpmc_clk_ns = gpmc_ticks_to_ns(div);
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if (gpmc_clk_ns < 15) /* >66Mhz */
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2012-06-05 12:41:48 +08:00
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onenand_flags |= ONENAND_FLAG_HF;
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else
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onenand_flags &= ~ONENAND_FLAG_HF;
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2011-02-07 16:46:58 +08:00
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if (gpmc_clk_ns < 12) /* >83Mhz */
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2012-06-05 12:41:48 +08:00
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onenand_flags |= ONENAND_FLAG_VHF;
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else
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onenand_flags &= ~ONENAND_FLAG_VHF;
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if (onenand_flags & ONENAND_FLAG_VHF)
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2011-02-07 16:46:58 +08:00
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latency = 8;
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2012-06-05 12:41:48 +08:00
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else if (onenand_flags & ONENAND_FLAG_HF)
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2009-05-29 04:23:52 +08:00
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latency = 6;
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else if (gpmc_clk_ns >= 25) /* 40 MHz*/
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latency = 3;
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else
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latency = 4;
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2012-06-05 12:41:48 +08:00
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/* Set synchronous read timings */
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2012-11-09 20:35:17 +08:00
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memset(&dev_t, 0, sizeof(dev_t));
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2009-05-29 04:23:52 +08:00
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2013-02-22 02:42:22 +08:00
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if (onenand_flags & ONENAND_FLAG_SYNCREAD)
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onenand_sync.sync_read = true;
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2012-06-05 12:41:48 +08:00
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if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {
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2013-02-22 03:46:22 +08:00
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onenand_sync.sync_write = true;
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2013-02-22 02:42:22 +08:00
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onenand_sync.burst_write = true;
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2009-05-29 04:23:52 +08:00
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} else {
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2012-11-09 20:35:17 +08:00
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dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
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dev_t.t_wpl = t_wpl * 1000;
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dev_t.t_wph = t_wph * 1000;
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dev_t.t_aavdh = t_aavdh * 1000;
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2009-05-29 04:23:52 +08:00
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}
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2012-11-09 20:35:17 +08:00
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dev_t.ce_xdelay = true;
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dev_t.avd_xdelay = true;
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dev_t.oe_xdelay = true;
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dev_t.we_xdelay = true;
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dev_t.clk = min_gpmc_clk_period;
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dev_t.t_bacc = dev_t.clk;
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dev_t.t_ces = t_ces * 1000;
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dev_t.t_avds = t_avds * 1000;
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dev_t.t_avdh = t_avdh * 1000;
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dev_t.t_ach = t_ach * 1000;
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dev_t.cyc_iaa = (latency + 1);
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dev_t.t_cez_r = t_cez * 1000;
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dev_t.t_cez_w = dev_t.t_cez_r;
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dev_t.cyc_aavdh_oe = 1;
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dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
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2013-02-22 03:46:22 +08:00
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gpmc_calc_timings(t, &onenand_sync, &dev_t);
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2012-06-05 12:41:48 +08:00
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}
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static int omap2_onenand_setup_async(void __iomem *onenand_base)
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{
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struct gpmc_timings t;
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int ret;
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ARM: OMAP2: gpmc-onenand: fix sync mode setup with DT
With DT-based boot, the GPMC OneNAND sync mode setup does not work
correctly. During the async mode setup, sync flags gets incorrectly
set in the onenand_async data and the system crashes during the async
setup. Also, the sync mode never gets set in gpmc_onenand_data->flags, so
even without the crash, the actual sync mode setup would never be called.
The patch fixes this by adjusting the gpmc_onenand_data->flags when the
data is read from the DT. Also while doing this we force the onenand_async
to be always async.
The patch enables to use the following DTS chunk (that should correspond
the arch/arm/mach-omap2/board-rm680.c board file setup) with Nokia N950,
which currently crashes with 3.12-rc1. The crash output can be also
found below.
&gpmc {
ranges = <0 0 0x04000000 0x20000000>;
onenand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x20000000>;
gpmc,sync-read;
gpmc,sync-write;
gpmc,burst-length = <16>;
gpmc,burst-read;
gpmc,burst-wrap;
gpmc,burst-write;
gpmc,device-width = <2>;
gpmc,mux-add-data = <2>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <87>;
gpmc,cs-wr-off-ns = <87>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <10>;
gpmc,adv-wr-off-ns = <10>;
gpmc,oe-on-ns = <15>;
gpmc,oe-off-ns = <87>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <87>;
gpmc,rd-cycle-ns = <112>;
gpmc,wr-cycle-ns = <112>;
gpmc,access-ns = <81>;
gpmc,page-burst-access-ns = <15>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <5>;
gpmc,wr-data-mux-bus-ns = <30>;
gpmc,wr-access-ns = <81>;
gpmc,sync-clk-ps = <15000>;
};
};
[ 1.467559] GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.474822] GPMC CS0: cs_rd_off : 1 ticks, 5 ns (was 24 ticks) 5 ns
[ 1.482116] GPMC CS0: cs_wr_off : 14 ticks, 71 ns (was 24 ticks) 71 ns
[ 1.489349] GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.496582] GPMC CS0: adv_rd_off: 3 ticks, 15 ns (was 3 ticks) 15 ns
[ 1.503845] GPMC CS0: adv_wr_off: 3 ticks, 15 ns (was 3 ticks) 15 ns
[ 1.511077] GPMC CS0: oe_on : 3 ticks, 15 ns (was 4 ticks) 15 ns
[ 1.518310] GPMC CS0: oe_off : 1 ticks, 5 ns (was 24 ticks) 5 ns
[ 1.525543] GPMC CS0: we_on : 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.532806] GPMC CS0: we_off : 8 ticks, 40 ns (was 24 ticks) 40 ns
[ 1.540039] GPMC CS0: rd_cycle : 4 ticks, 20 ns (was 29 ticks) 20 ns
[ 1.547302] GPMC CS0: wr_cycle : 4 ticks, 20 ns (was 29 ticks) 20 ns
[ 1.554504] GPMC CS0: access : 0 ticks, 0 ns (was 23 ticks) 0 ns
[ 1.561767] GPMC CS0: page_burst_access: 0 ticks, 0 ns (was 3 ticks) 0 ns
[ 1.569641] GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.577270] GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.585144] GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.592834] GPMC CS0: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.600463] GPMC CS0: wr_data_mux_bus: 5 ticks, 25 ns (was 8 ticks) 25 ns
[ 1.608154] GPMC CS0: wr_access : 0 ticks, 0 ns (was 23 ticks) 0 ns
[ 1.615386] GPMC CS0 CLK period is 5 ns (div 1)
[ 1.625122] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf009e442
[ 1.633178] Internal error: : 1008 [#1] ARM
[ 1.637573] Modules linked in:
[ 1.640777] CPU: 0 PID: 1 Comm: swapper Not tainted 3.12.0-rc1-n9xx-los.git-5318619-00006-g4baa700-dirty #26
[ 1.651123] task: ef04c000 ti: ef050000 task.ti: ef050000
[ 1.656799] PC is at gpmc_onenand_setup+0x98/0x1e0
[ 1.661865] LR is at gpmc_cs_set_timings+0x494/0x5a4
[ 1.667083] pc : [<c002e040>] lr : [<c001f384>] psr: 60000113
[ 1.667083] sp : ef051d10 ip : ef051ce0 fp : ef051d94
[ 1.679138] r10: c0caaf60 r9 : ef050000 r8 : ef18b32c
[ 1.684631] r7 : f0080000 r6 : c0caaf60 r5 : 00000000 r4 : f009e400
[ 1.691497] r3 : f009e442 r2 : 80050000 r1 : 00000014 r0 : 00000000
[ 1.698333] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
[ 1.706024] Control: 10c5387d Table: af290019 DAC: 00000015
[ 1.712066] Process swapper (pid: 1, stack limit = 0xef050240)
[ 1.718200] Stack: (0xef051d10 to 0xef052000)
[ 1.722778] 1d00: 00004000 00001402 00000000 00000005
[ 1.731384] 1d20: 00000047 00000000 0000000f 0000000f 00000000 00000028 0000000f 00000005
[ 1.739990] 1d40: 00000000 00000000 00000014 00000014 00000000 00000000 00000000 00000000
[ 1.748596] 1d60: 00000000 00000019 00000000 00000000 ef18b000 ef099c50 c0c8cb30 00000000
[ 1.757171] 1d80: c0488074 c048f868 ef051dcc ef051d98 c024447c c002dfb4 00000000 c048f868
[ 1.765777] 1da0: 00000000 00000000 c010e4a4 c0dbbb7c c0c8cb40 00000000 c0ca2500 c0488074
[ 1.774383] 1dc0: ef051ddc ef051dd0 c01fd508 c0244370 ef051dfc ef051de0 c01fc204 c01fd4f4
[ 1.782989] 1de0: c0c8cb40 c0ca2500 c0c8cb74 00000000 ef051e1c ef051e00 c01fc3b0 c01fc104
[ 1.791595] 1e00: ef0983bc 00000000 c0ca2500 c01fc31c ef051e44 ef051e20 c01fa794 c01fc328
[ 1.800201] 1e20: ef03634c ef0983b0 ef27d534 c0ca2500 ef27d500 c0c9a2f8 ef051e54 ef051e48
[ 1.808807] 1e40: c01fbcfc c01fa744 ef051e84 ef051e58 c01fb838 c01fbce4 c0411df8 c0caa040
[ 1.817413] 1e60: ef051e84 c0ca2500 00000006 c0caa040 00000066 c0488074 ef051e9c ef051e88
[ 1.825988] 1e80: c01fca30 c01fb768 c04975b8 00000006 ef051eac ef051ea0 c01fd728 c01fc9bc
[ 1.834594] 1ea0: ef051ebc ef051eb0 c048808c c01fd6e4 ef051f4c ef051ec0 c0008888 c0488080
[ 1.843200] 1ec0: 0000006f c046bae8 00000000 00000000 ef051efc ef051ee0 ef051f04 ef051ee8
[ 1.851806] 1ee0: c046d400 c0181218 c046d410 c18da8d5 c036a8e4 00000066 ef051f4c ef051f08
[ 1.860412] 1f00: c004b9a8 c046d41c c048f840 00000006 00000006 c046b488 00000000 c043ec08
[ 1.869018] 1f20: ef051f4c c04975b8 00000006 c0caa040 00000066 c046d410 c048f85c c048f868
[ 1.877593] 1f40: ef051f94 ef051f50 c046db8c c00087a0 00000006 00000006 c046d410 ffffffff
[ 1.886199] 1f60: ffffffff ffffffff ffffffff 00000000 c0348fd0 00000000 00000000 00000000
[ 1.894805] 1f80: 00000000 00000000 ef051fac ef051f98 c0348fe0 c046daa8 00000000 00000000
[ 1.903411] 1fa0: 00000000 ef051fb0 c000e7f8 c0348fdc 00000000 00000000 00000000 00000000
[ 1.912017] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 1.920623] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 ffffffff ffffffff
[ 1.929199] Backtrace:
[ 1.931793] [<c002dfa8>] (gpmc_onenand_setup+0x0/0x1e0) from [<c024447c>] (omap2_onenand_probe+0x118/0x49c)
[ 1.942047] [<c0244364>] (omap2_onenand_probe+0x0/0x49c) from [<c01fd508>] (platform_drv_probe+0x20/0x24)
[ 1.952117] r8:c0488074 r7:c0ca2500 r6:00000000 r5:c0c8cb40 r4:c0dbbb7c
[ 1.959197] [<c01fd4e8>] (platform_drv_probe+0x0/0x24) from [<c01fc204>] (driver_probe_device+0x10c/0x224)
[ 1.969360] [<c01fc0f8>] (driver_probe_device+0x0/0x224) from [<c01fc3b0>] (__driver_attach+0x94/0x98)
[ 1.979125] r7:00000000 r6:c0c8cb74 r5:c0ca2500 r4:c0c8cb40
[ 1.985107] [<c01fc31c>] (__driver_attach+0x0/0x98) from [<c01fa794>] (bus_for_each_dev+0x5c/0x90)
[ 1.994506] r6:c01fc31c r5:c0ca2500 r4:00000000 r3:ef0983bc
[ 2.000488] [<c01fa738>] (bus_for_each_dev+0x0/0x90) from [<c01fbcfc>] (driver_attach+0x24/0x28)
[ 2.009735] r6:c0c9a2f8 r5:ef27d500 r4:c0ca2500
[ 2.014587] [<c01fbcd8>] (driver_attach+0x0/0x28) from [<c01fb838>] (bus_add_driver+0xdc/0x260)
[ 2.023742] [<c01fb75c>] (bus_add_driver+0x0/0x260) from [<c01fca30>] (driver_register+0x80/0xfc)
[ 2.033081] r8:c0488074 r7:00000066 r6:c0caa040 r5:00000006 r4:c0ca2500
[ 2.040161] [<c01fc9b0>] (driver_register+0x0/0xfc) from [<c01fd728>] (__platform_driver_register+0x50/0x64)
[ 2.050476] r5:00000006 r4:c04975b8
[ 2.054260] [<c01fd6d8>] (__platform_driver_register+0x0/0x64) from [<c048808c>] (omap2_onenand_driver_init+0x18/0x20)
[ 2.065490] [<c0488074>] (omap2_onenand_driver_init+0x0/0x20) from [<c0008888>] (do_one_initcall+0xf4/0x150)
[ 2.075836] [<c0008794>] (do_one_initcall+0x0/0x150) from [<c046db8c>] (kernel_init_freeable+0xf0/0x1b4)
[ 2.085815] [<c046da9c>] (kernel_init_freeable+0x0/0x1b4) from [<c0348fe0>] (kernel_init+0x10/0xec)
[ 2.095336] [<c0348fd0>] (kernel_init+0x0/0xec) from [<c000e7f8>] (ret_from_fork+0x14/0x3c)
[ 2.104125] r4:00000000 r3:00000000
[ 2.107879] Code: ebffc3ae e2505000 ba00002e e2843042 (e1d320b0)
[ 2.114318] ---[ end trace b8ee3e3e5e002451 ]---
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-09-21 04:01:06 +08:00
|
|
|
if (gpmc_onenand_data->of_node) {
|
2013-02-26 01:37:58 +08:00
|
|
|
gpmc_read_settings_dt(gpmc_onenand_data->of_node,
|
|
|
|
&onenand_async);
|
ARM: OMAP2: gpmc-onenand: fix sync mode setup with DT
With DT-based boot, the GPMC OneNAND sync mode setup does not work
correctly. During the async mode setup, sync flags gets incorrectly
set in the onenand_async data and the system crashes during the async
setup. Also, the sync mode never gets set in gpmc_onenand_data->flags, so
even without the crash, the actual sync mode setup would never be called.
The patch fixes this by adjusting the gpmc_onenand_data->flags when the
data is read from the DT. Also while doing this we force the onenand_async
to be always async.
The patch enables to use the following DTS chunk (that should correspond
the arch/arm/mach-omap2/board-rm680.c board file setup) with Nokia N950,
which currently crashes with 3.12-rc1. The crash output can be also
found below.
&gpmc {
ranges = <0 0 0x04000000 0x20000000>;
onenand@0,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x20000000>;
gpmc,sync-read;
gpmc,sync-write;
gpmc,burst-length = <16>;
gpmc,burst-read;
gpmc,burst-wrap;
gpmc,burst-write;
gpmc,device-width = <2>;
gpmc,mux-add-data = <2>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <87>;
gpmc,cs-wr-off-ns = <87>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <10>;
gpmc,adv-wr-off-ns = <10>;
gpmc,oe-on-ns = <15>;
gpmc,oe-off-ns = <87>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <87>;
gpmc,rd-cycle-ns = <112>;
gpmc,wr-cycle-ns = <112>;
gpmc,access-ns = <81>;
gpmc,page-burst-access-ns = <15>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,wait-monitoring-ns = <0>;
gpmc,clk-activation-ns = <5>;
gpmc,wr-data-mux-bus-ns = <30>;
gpmc,wr-access-ns = <81>;
gpmc,sync-clk-ps = <15000>;
};
};
[ 1.467559] GPMC CS0: cs_on : 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.474822] GPMC CS0: cs_rd_off : 1 ticks, 5 ns (was 24 ticks) 5 ns
[ 1.482116] GPMC CS0: cs_wr_off : 14 ticks, 71 ns (was 24 ticks) 71 ns
[ 1.489349] GPMC CS0: adv_on : 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.496582] GPMC CS0: adv_rd_off: 3 ticks, 15 ns (was 3 ticks) 15 ns
[ 1.503845] GPMC CS0: adv_wr_off: 3 ticks, 15 ns (was 3 ticks) 15 ns
[ 1.511077] GPMC CS0: oe_on : 3 ticks, 15 ns (was 4 ticks) 15 ns
[ 1.518310] GPMC CS0: oe_off : 1 ticks, 5 ns (was 24 ticks) 5 ns
[ 1.525543] GPMC CS0: we_on : 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.532806] GPMC CS0: we_off : 8 ticks, 40 ns (was 24 ticks) 40 ns
[ 1.540039] GPMC CS0: rd_cycle : 4 ticks, 20 ns (was 29 ticks) 20 ns
[ 1.547302] GPMC CS0: wr_cycle : 4 ticks, 20 ns (was 29 ticks) 20 ns
[ 1.554504] GPMC CS0: access : 0 ticks, 0 ns (was 23 ticks) 0 ns
[ 1.561767] GPMC CS0: page_burst_access: 0 ticks, 0 ns (was 3 ticks) 0 ns
[ 1.569641] GPMC CS0: bus_turnaround: 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.577270] GPMC CS0: cycle2cycle_delay: 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.585144] GPMC CS0: wait_monitoring: 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.592834] GPMC CS0: clk_activation: 0 ticks, 0 ns (was 0 ticks) 0 ns
[ 1.600463] GPMC CS0: wr_data_mux_bus: 5 ticks, 25 ns (was 8 ticks) 25 ns
[ 1.608154] GPMC CS0: wr_access : 0 ticks, 0 ns (was 23 ticks) 0 ns
[ 1.615386] GPMC CS0 CLK period is 5 ns (div 1)
[ 1.625122] Unhandled fault: external abort on non-linefetch (0x1008) at 0xf009e442
[ 1.633178] Internal error: : 1008 [#1] ARM
[ 1.637573] Modules linked in:
[ 1.640777] CPU: 0 PID: 1 Comm: swapper Not tainted 3.12.0-rc1-n9xx-los.git-5318619-00006-g4baa700-dirty #26
[ 1.651123] task: ef04c000 ti: ef050000 task.ti: ef050000
[ 1.656799] PC is at gpmc_onenand_setup+0x98/0x1e0
[ 1.661865] LR is at gpmc_cs_set_timings+0x494/0x5a4
[ 1.667083] pc : [<c002e040>] lr : [<c001f384>] psr: 60000113
[ 1.667083] sp : ef051d10 ip : ef051ce0 fp : ef051d94
[ 1.679138] r10: c0caaf60 r9 : ef050000 r8 : ef18b32c
[ 1.684631] r7 : f0080000 r6 : c0caaf60 r5 : 00000000 r4 : f009e400
[ 1.691497] r3 : f009e442 r2 : 80050000 r1 : 00000014 r0 : 00000000
[ 1.698333] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
[ 1.706024] Control: 10c5387d Table: af290019 DAC: 00000015
[ 1.712066] Process swapper (pid: 1, stack limit = 0xef050240)
[ 1.718200] Stack: (0xef051d10 to 0xef052000)
[ 1.722778] 1d00: 00004000 00001402 00000000 00000005
[ 1.731384] 1d20: 00000047 00000000 0000000f 0000000f 00000000 00000028 0000000f 00000005
[ 1.739990] 1d40: 00000000 00000000 00000014 00000014 00000000 00000000 00000000 00000000
[ 1.748596] 1d60: 00000000 00000019 00000000 00000000 ef18b000 ef099c50 c0c8cb30 00000000
[ 1.757171] 1d80: c0488074 c048f868 ef051dcc ef051d98 c024447c c002dfb4 00000000 c048f868
[ 1.765777] 1da0: 00000000 00000000 c010e4a4 c0dbbb7c c0c8cb40 00000000 c0ca2500 c0488074
[ 1.774383] 1dc0: ef051ddc ef051dd0 c01fd508 c0244370 ef051dfc ef051de0 c01fc204 c01fd4f4
[ 1.782989] 1de0: c0c8cb40 c0ca2500 c0c8cb74 00000000 ef051e1c ef051e00 c01fc3b0 c01fc104
[ 1.791595] 1e00: ef0983bc 00000000 c0ca2500 c01fc31c ef051e44 ef051e20 c01fa794 c01fc328
[ 1.800201] 1e20: ef03634c ef0983b0 ef27d534 c0ca2500 ef27d500 c0c9a2f8 ef051e54 ef051e48
[ 1.808807] 1e40: c01fbcfc c01fa744 ef051e84 ef051e58 c01fb838 c01fbce4 c0411df8 c0caa040
[ 1.817413] 1e60: ef051e84 c0ca2500 00000006 c0caa040 00000066 c0488074 ef051e9c ef051e88
[ 1.825988] 1e80: c01fca30 c01fb768 c04975b8 00000006 ef051eac ef051ea0 c01fd728 c01fc9bc
[ 1.834594] 1ea0: ef051ebc ef051eb0 c048808c c01fd6e4 ef051f4c ef051ec0 c0008888 c0488080
[ 1.843200] 1ec0: 0000006f c046bae8 00000000 00000000 ef051efc ef051ee0 ef051f04 ef051ee8
[ 1.851806] 1ee0: c046d400 c0181218 c046d410 c18da8d5 c036a8e4 00000066 ef051f4c ef051f08
[ 1.860412] 1f00: c004b9a8 c046d41c c048f840 00000006 00000006 c046b488 00000000 c043ec08
[ 1.869018] 1f20: ef051f4c c04975b8 00000006 c0caa040 00000066 c046d410 c048f85c c048f868
[ 1.877593] 1f40: ef051f94 ef051f50 c046db8c c00087a0 00000006 00000006 c046d410 ffffffff
[ 1.886199] 1f60: ffffffff ffffffff ffffffff 00000000 c0348fd0 00000000 00000000 00000000
[ 1.894805] 1f80: 00000000 00000000 ef051fac ef051f98 c0348fe0 c046daa8 00000000 00000000
[ 1.903411] 1fa0: 00000000 ef051fb0 c000e7f8 c0348fdc 00000000 00000000 00000000 00000000
[ 1.912017] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 1.920623] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 ffffffff ffffffff
[ 1.929199] Backtrace:
[ 1.931793] [<c002dfa8>] (gpmc_onenand_setup+0x0/0x1e0) from [<c024447c>] (omap2_onenand_probe+0x118/0x49c)
[ 1.942047] [<c0244364>] (omap2_onenand_probe+0x0/0x49c) from [<c01fd508>] (platform_drv_probe+0x20/0x24)
[ 1.952117] r8:c0488074 r7:c0ca2500 r6:00000000 r5:c0c8cb40 r4:c0dbbb7c
[ 1.959197] [<c01fd4e8>] (platform_drv_probe+0x0/0x24) from [<c01fc204>] (driver_probe_device+0x10c/0x224)
[ 1.969360] [<c01fc0f8>] (driver_probe_device+0x0/0x224) from [<c01fc3b0>] (__driver_attach+0x94/0x98)
[ 1.979125] r7:00000000 r6:c0c8cb74 r5:c0ca2500 r4:c0c8cb40
[ 1.985107] [<c01fc31c>] (__driver_attach+0x0/0x98) from [<c01fa794>] (bus_for_each_dev+0x5c/0x90)
[ 1.994506] r6:c01fc31c r5:c0ca2500 r4:00000000 r3:ef0983bc
[ 2.000488] [<c01fa738>] (bus_for_each_dev+0x0/0x90) from [<c01fbcfc>] (driver_attach+0x24/0x28)
[ 2.009735] r6:c0c9a2f8 r5:ef27d500 r4:c0ca2500
[ 2.014587] [<c01fbcd8>] (driver_attach+0x0/0x28) from [<c01fb838>] (bus_add_driver+0xdc/0x260)
[ 2.023742] [<c01fb75c>] (bus_add_driver+0x0/0x260) from [<c01fca30>] (driver_register+0x80/0xfc)
[ 2.033081] r8:c0488074 r7:00000066 r6:c0caa040 r5:00000006 r4:c0ca2500
[ 2.040161] [<c01fc9b0>] (driver_register+0x0/0xfc) from [<c01fd728>] (__platform_driver_register+0x50/0x64)
[ 2.050476] r5:00000006 r4:c04975b8
[ 2.054260] [<c01fd6d8>] (__platform_driver_register+0x0/0x64) from [<c048808c>] (omap2_onenand_driver_init+0x18/0x20)
[ 2.065490] [<c0488074>] (omap2_onenand_driver_init+0x0/0x20) from [<c0008888>] (do_one_initcall+0xf4/0x150)
[ 2.075836] [<c0008794>] (do_one_initcall+0x0/0x150) from [<c046db8c>] (kernel_init_freeable+0xf0/0x1b4)
[ 2.085815] [<c046da9c>] (kernel_init_freeable+0x0/0x1b4) from [<c0348fe0>] (kernel_init+0x10/0xec)
[ 2.095336] [<c0348fd0>] (kernel_init+0x0/0xec) from [<c000e7f8>] (ret_from_fork+0x14/0x3c)
[ 2.104125] r4:00000000 r3:00000000
[ 2.107879] Code: ebffc3ae e2505000 ba00002e e2843042 (e1d320b0)
[ 2.114318] ---[ end trace b8ee3e3e5e002451 ]---
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-09-21 04:01:06 +08:00
|
|
|
if (onenand_async.sync_read || onenand_async.sync_write) {
|
|
|
|
if (onenand_async.sync_write)
|
|
|
|
gpmc_onenand_data->flags |=
|
|
|
|
ONENAND_SYNC_READWRITE;
|
|
|
|
else
|
|
|
|
gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
|
|
|
|
onenand_async.sync_read = false;
|
|
|
|
onenand_async.sync_write = false;
|
|
|
|
}
|
|
|
|
}
|
2013-02-26 01:37:58 +08:00
|
|
|
|
2012-06-05 12:41:48 +08:00
|
|
|
omap2_onenand_set_async_mode(onenand_base);
|
|
|
|
|
2013-02-22 05:20:53 +08:00
|
|
|
omap2_onenand_calc_async_timings(&t);
|
2012-06-05 12:41:48 +08:00
|
|
|
|
2013-02-22 02:42:22 +08:00
|
|
|
ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
|
ARM: OMAP: use consistent error checking
Consistently check errors using the usual method used in the kernel
for much of its history. For instance:
int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
int div;
div = gpmc_calc_divider(t->sync_clk);
if (div < 0)
return div;
static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
{
...
return gpmc_cs_set_timings(cs, t);
.....
ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
if (IS_ERR_VALUE(ret))
return ret;
So, gpmc_cs_set_timings() thinks any negative return value is an error,
but where we check that in higher levels, only a limited range are
errors...
There is only _one_ use of IS_ERR_VALUE() in arch/arm which is really
appropriate, and that is in arch/arm/include/asm/syscall.h:
static inline long syscall_get_error(struct task_struct *task,
struct pt_regs *regs)
{
unsigned long error = regs->ARM_r0;
return IS_ERR_VALUE(error) ? error : 0;
}
because this function really does have to differentiate between error
return values and addresses which look like negative numbers (eg, from
mmap()).
So, here's a patch to remove them from OMAP, except for the above.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-03-14 04:44:21 +08:00
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if (ret < 0)
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2012-06-05 12:41:48 +08:00
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return ret;
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omap2_onenand_set_async_mode(onenand_base);
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return 0;
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}
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static int omap2_onenand_setup_sync(void __iomem *onenand_base, int *freq_ptr)
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{
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int ret, freq = *freq_ptr;
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struct gpmc_timings t;
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if (!freq) {
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/* Very first call freq is not known */
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2012-06-29 02:41:29 +08:00
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freq = omap2_onenand_get_freq(gpmc_onenand_data, onenand_base);
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2012-06-05 12:41:48 +08:00
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set_onenand_cfg(onenand_base);
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}
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2013-02-26 01:37:58 +08:00
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if (gpmc_onenand_data->of_node) {
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gpmc_read_settings_dt(gpmc_onenand_data->of_node,
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&onenand_sync);
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} else {
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/*
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* FIXME: Appears to be legacy code from initial ONENAND commit.
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* Unclear what boards this is for and if this can be removed.
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*/
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if (!cpu_is_omap34xx())
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onenand_sync.wait_on_read = true;
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}
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2013-02-22 02:42:22 +08:00
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2013-02-22 05:20:53 +08:00
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omap2_onenand_calc_sync_timings(&t, gpmc_onenand_data->flags, freq);
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2009-05-29 04:23:52 +08:00
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2013-02-22 02:42:22 +08:00
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ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_sync);
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if (ret < 0)
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return ret;
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ret = gpmc_cs_set_timings(gpmc_onenand_data->cs, &t);
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ARM: OMAP: use consistent error checking
Consistently check errors using the usual method used in the kernel
for much of its history. For instance:
int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
{
int div;
div = gpmc_calc_divider(t->sync_clk);
if (div < 0)
return div;
static int gpmc_set_async_mode(int cs, struct gpmc_timings *t)
{
...
return gpmc_cs_set_timings(cs, t);
.....
ret = gpmc_set_async_mode(gpmc_onenand_data->cs, &t);
if (IS_ERR_VALUE(ret))
return ret;
So, gpmc_cs_set_timings() thinks any negative return value is an error,
but where we check that in higher levels, only a limited range are
errors...
There is only _one_ use of IS_ERR_VALUE() in arch/arm which is really
appropriate, and that is in arch/arm/include/asm/syscall.h:
static inline long syscall_get_error(struct task_struct *task,
struct pt_regs *regs)
{
unsigned long error = regs->ARM_r0;
return IS_ERR_VALUE(error) ? error : 0;
}
because this function really does have to differentiate between error
return values and addresses which look like negative numbers (eg, from
mmap()).
So, here's a patch to remove them from OMAP, except for the above.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-03-14 04:44:21 +08:00
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if (ret < 0)
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2012-06-05 12:41:48 +08:00
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return ret;
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set_onenand_cfg(onenand_base);
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2009-05-29 04:23:52 +08:00
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2011-02-07 16:46:59 +08:00
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*freq_ptr = freq;
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2009-05-29 04:23:52 +08:00
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return 0;
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}
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2011-02-07 16:46:59 +08:00
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static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
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2009-05-29 04:23:52 +08:00
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{
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struct device *dev = &gpmc_onenand_device.dev;
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2012-06-05 12:41:48 +08:00
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unsigned l = ONENAND_SYNC_READ | ONENAND_SYNC_READWRITE;
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int ret;
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2009-05-29 04:23:52 +08:00
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2012-06-05 12:41:48 +08:00
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ret = omap2_onenand_setup_async(onenand_base);
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if (ret) {
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dev_err(dev, "unable to set to async mode\n");
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return ret;
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2009-05-29 04:23:52 +08:00
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}
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2012-06-05 12:41:48 +08:00
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if (!(gpmc_onenand_data->flags & l))
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return 0;
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ret = omap2_onenand_setup_sync(onenand_base, freq_ptr);
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if (ret)
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dev_err(dev, "unable to set to sync mode\n");
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return ret;
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2009-05-29 04:23:52 +08:00
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}
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2013-01-25 20:23:10 +08:00
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void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
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2009-05-29 04:23:52 +08:00
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{
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2012-08-31 03:53:23 +08:00
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int err;
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2013-02-13 03:22:22 +08:00
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struct device *dev = &gpmc_onenand_device.dev;
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2012-08-31 03:53:23 +08:00
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2009-05-29 04:23:52 +08:00
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gpmc_onenand_data = _onenand_data;
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gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
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gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
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if (cpu_is_omap24xx() &&
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(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
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2013-02-13 03:22:23 +08:00
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dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
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2009-05-29 04:23:52 +08:00
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gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
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gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
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}
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2012-10-05 14:09:54 +08:00
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if (cpu_is_omap34xx())
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gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
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else
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gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
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2012-08-31 03:53:23 +08:00
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err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
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(unsigned long *)&gpmc_onenand_resource.start);
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if (err < 0) {
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2013-02-13 03:22:22 +08:00
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dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
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gpmc_onenand_data->cs, err);
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2012-08-31 03:53:23 +08:00
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return;
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}
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gpmc_onenand_resource.end = gpmc_onenand_resource.start +
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ONENAND_IO_SIZE - 1;
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2009-05-29 04:23:52 +08:00
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if (platform_device_register(&gpmc_onenand_device) < 0) {
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2013-02-13 03:22:22 +08:00
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dev_err(dev, "Unable to register OneNAND device\n");
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2012-08-31 03:53:23 +08:00
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gpmc_cs_free(gpmc_onenand_data->cs);
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2009-05-29 04:23:52 +08:00
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return;
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}
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}
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