2014-03-17 08:02:46 +08:00
|
|
|
* Renesas VMSA-Compatible IOMMU
|
|
|
|
|
|
|
|
|
|
The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
|
|
|
|
|
It provides address translation for bus masters outside of the CPU, each
|
|
|
|
|
connected to the IPMMU through a port called micro-TLB.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Required Properties:
|
|
|
|
|
|
2016-02-29 22:33:09 +08:00
|
|
|
- compatible: Must contain SoC-specific and generic entry below in case
|
|
|
|
|
the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
|
2015-11-17 11:53:20 +08:00
|
|
|
|
|
|
|
|
- "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
|
2018-01-24 23:42:00 +08:00
|
|
|
- "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
|
2018-10-05 00:25:47 +08:00
|
|
|
- "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU.
|
2018-01-24 23:42:00 +08:00
|
|
|
- "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
|
2015-11-17 11:53:20 +08:00
|
|
|
- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
|
|
|
|
|
- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
|
|
|
|
|
- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
|
|
|
|
|
- "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.
|
2016-02-29 22:33:09 +08:00
|
|
|
- "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.
|
2017-12-21 00:48:00 +08:00
|
|
|
- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
|
2018-06-14 18:48:24 +08:00
|
|
|
- "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU.
|
2017-12-21 00:48:01 +08:00
|
|
|
- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
|
2018-06-14 18:48:26 +08:00
|
|
|
- "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU.
|
|
|
|
|
- "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU.
|
2017-12-21 00:48:01 +08:00
|
|
|
- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
|
2018-01-24 23:42:00 +08:00
|
|
|
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
|
|
|
|
|
IPMMU.
|
2015-11-17 11:53:20 +08:00
|
|
|
|
2014-03-17 08:02:46 +08:00
|
|
|
- reg: Base address and size of the IPMMU registers.
|
|
|
|
|
- interrupts: Specifiers for the MMU fault interrupts. For instances that
|
|
|
|
|
support secure mode two interrupts must be specified, for non-secure and
|
|
|
|
|
secure mode, in that order. For instances that don't support secure mode a
|
2016-02-29 22:33:09 +08:00
|
|
|
single interrupt must be specified. Not required for cache IPMMUs.
|
2014-03-17 08:02:46 +08:00
|
|
|
|
|
|
|
|
- #iommu-cells: Must be 1.
|
|
|
|
|
|
2016-02-29 22:33:09 +08:00
|
|
|
Optional properties:
|
|
|
|
|
|
|
|
|
|
- renesas,ipmmu-main: reference to the main IPMMU instance in two cells.
|
|
|
|
|
The first cell is a phandle to the main IPMMU and the second cell is
|
|
|
|
|
the interrupt bit number associated with the particular cache IPMMU device.
|
|
|
|
|
The interrupt bit number needs to match the main IPMMU IMSSTR register.
|
|
|
|
|
Only used by cache IPMMU instances.
|
|
|
|
|
|
|
|
|
|
|
2014-03-17 08:02:46 +08:00
|
|
|
Each bus master connected to an IPMMU must reference the IPMMU in its device
|
|
|
|
|
node with the following property:
|
|
|
|
|
|
|
|
|
|
- iommus: A reference to the IPMMU in two cells. The first cell is a phandle
|
|
|
|
|
to the IPMMU and the second cell the number of the micro-TLB that the
|
|
|
|
|
device is connected to.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
|
|
|
|
|
|
|
|
|
|
ipmmu_mx: mmu@fe951000 {
|
2015-11-17 11:53:20 +08:00
|
|
|
compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
|
2014-03-17 08:02:46 +08:00
|
|
|
reg = <0 0xfe951000 0 0x1000>;
|
|
|
|
|
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
#iommu-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-04 20:33:08 +08:00
|
|
|
vsp@fe928000 {
|
2014-03-17 08:02:46 +08:00
|
|
|
...
|
|
|
|
|
iommus = <&ipmmu_mx 13>;
|
|
|
|
|
...
|
|
|
|
|
};
|
