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linux/arch/arm/boot/dts/socfpga_arria10.dtsi

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arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
/*
* Copyright Altera Corporation (C) 2014. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
ARM: socfpga: dts: add enable-method property for cpu nodes Add the enable-method property for the cpu node on socfpga.dtsi and socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable the secondary core. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-23 12:00:10 +08:00
enable-method = "altr,socfpga-a10-smp";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};
intc: intc@ffffd000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xffffd000 0x1000>,
<0xffffc100 0x100>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
device_type = "soc";
interrupt-parent = <&intc>;
ranges;
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
pdma: pdma@ffda1000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xffda1000 0x1000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
<0 84 IRQ_TYPE_LEVEL_HIGH>,
<0 85 IRQ_TYPE_LEVEL_HIGH>,
<0 86 IRQ_TYPE_LEVEL_HIGH>,
<0 87 IRQ_TYPE_LEVEL_HIGH>,
<0 88 IRQ_TYPE_LEVEL_HIGH>,
<0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
};
clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
cb_intosc_ls_clk: cb_intosc_ls_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
f2s_free_clk: f2s_free_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
};
main_pll: main_pll {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
compatible = "altr,socfpga-a10-pll-clock";
clocks = <&osc1>, <&cb_intosc_ls_clk>,
<&f2s_free_clk>;
reg = <0x40>;
main_mpu_base_clk: main_mpu_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
div-reg = <0x140 0 11>;
};
main_noc_base_clk: main_noc_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
div-reg = <0x144 0 11>;
};
main_emaca_clk: main_emaca_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x68>;
};
main_emacb_clk: main_emacb_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x6C>;
};
main_emac_ptp_clk: main_emac_ptp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x70>;
};
main_gpio_db_clk: main_gpio_db_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x74>;
};
main_sdmmc_clk: main_sdmmc_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk"
;
clocks = <&main_pll>;
reg = <0x78>;
};
main_s2f_usr0_clk: main_s2f_usr0_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x7C>;
};
main_s2f_usr1_clk: main_s2f_usr1_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x80>;
};
main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x84>;
};
main_periph_ref_clk: main_periph_ref_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x9C>;
};
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
periph_pll: periph_pll {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
compatible = "altr,socfpga-a10-pll-clock";
clocks = <&osc1>, <&cb_intosc_ls_clk>,
<&f2s_free_clk>, <&main_periph_ref_clk>;
reg = <0xC0>;
peri_mpu_base_clk: peri_mpu_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
div-reg = <0x140 16 11>;
};
peri_noc_base_clk: peri_noc_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
div-reg = <0x144 16 11>;
};
peri_emaca_clk: peri_emaca_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xE8>;
};
peri_emacb_clk: peri_emacb_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xEC>;
};
peri_emac_ptp_clk: peri_emac_ptp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF0>;
};
peri_gpio_db_clk: peri_gpio_db_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF4>;
};
peri_sdmmc_clk: peri_sdmmc_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF8>;
};
peri_s2f_usr0_clk: peri_s2f_usr0_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xFC>;
};
peri_s2f_usr1_clk: peri_s2f_usr1_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0x100>;
};
peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0x104>;
};
};
mpu_free_clk: mpu_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
reg = <0x60>;
};
noc_free_clk: noc_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
reg = <0x64>;
};
s2f_user1_free_clk: s2f_user1_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
reg = <0x104>;
};
sdmmc_free_clk: sdmmc_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
fixed-divider = <4>;
reg = <0xF8>;
};
l4_sys_free_clk: l4_sys_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&noc_free_clk>;
fixed-divider = <4>;
};
l4_main_clk: l4_main_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
div-reg = <0xA8 0 2>;
clk-gate = <0x48 1>;
};
l4_mp_clk: l4_mp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
div-reg = <0xA8 8 2>;
clk-gate = <0x48 2>;
};
l4_sp_clk: l4_sp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
div-reg = <0xA8 16 2>;
clk-gate = <0x48 3>;
};
mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&mpu_free_clk>;
fixed-divider = <4>;
clk-gate = <0x48 0>;
};
sdmmc_clk: sdmmc_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&sdmmc_free_clk>;
clk-gate = <0xC8 5>;
};
qspi_clk: qspi_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_main_clk>;
clk-gate = <0xC8 11>;
};
nand_clk: nand_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_mp_clk>;
clk-gate = <0xC8 10>;
};
spi_m_clk: spi_m_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_main_clk>;
clk-gate = <0xC8 9>;
};
usb_clk: usb_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_mp_clk>;
clk-gate = <0xC8 8>;
};
s2f_usr1_clk: s2f_usr1_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&peri_s2f_usr1_clk>;
clk-gate = <0xC8 6>;
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
};
};
gmac0: ethernet@ff800000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
reg = <0xff800000 0x2000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
ARM: socfpga: dts: Add multicast bins and unicast filter entries Add multicast-filter-bins and perfect-filter-entries configuration properties to the socfpga devicetree for the Arria 10 socfpga. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-22 03:15:40 +08:00
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
status = "disabled";
};
gmac1: ethernet@ff802000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
reg = <0xff802000 0x2000>;
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
ARM: socfpga: dts: Add multicast bins and unicast filter entries Add multicast-filter-bins and perfect-filter-entries configuration properties to the socfpga devicetree for the Arria 10 socfpga. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-22 03:15:40 +08:00
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga stmmac. These devicetree properties will be used to configure certain features of the stmmac on the socfpga. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-22 03:19:24 +08:00
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
status = "disabled";
};
gmac2: ethernet@ff804000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
reg = <0xff804000 0x2000>;
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
ARM: socfpga: dts: Add multicast bins and unicast filter entries Add multicast-filter-bins and perfect-filter-entries configuration properties to the socfpga devicetree for the Arria 10 socfpga. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-22 03:15:40 +08:00
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties Add tx-fifo-depth and rx-fifo-depth devicetree properties for socfpga stmmac. These devicetree properties will be used to configure certain features of the stmmac on the socfpga. Signed-off-by: Vince Bridgers <vbridger@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-04-22 03:19:24 +08:00
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
status = "disabled";
};
gpio0: gpio@ffc02900 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02900 0x100>;
status = "disabled";
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio1: gpio@ffc02a00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02a00 0x100>;
status = "disabled";
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio2: gpio@ffc02b00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02b00 0x100>;
status = "disabled";
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
};
};
i2c0: i2c@ffc02200 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02200 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c1: i2c@ffc02300 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02300 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c2: i2c@ffc02400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02400 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c3: i2c@ffc02500 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02500 0x100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c4: i2c@ffc02600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xffc02600 0x100>;
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
L2: l2-cache@fffff000 {
compatible = "arm,pl310-cache";
reg = <0xfffff000 0x1000>;
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
};
mmc: dwmmc0@ff808000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "altr,socfpga-dw-mshc";
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
clock-names = "biu", "ciu";
ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10 Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 12:05:21 +08:00
status = "disabled";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
ocram: sram@ffe00000 {
compatible = "mmio-sram";
reg = <0xffe00000 0x40000>;
};
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x100>;
};
ARM: socfpga: dts: add the a9-scu node for arria10 Add a dts node for the A9 SCU on the Arria10 platform. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-14 22:49:14 +08:00
scu: snoop-control-unit@ffffc000 {
compatible = "arm,cortex-a9-scu";
reg = <0xffffc000 0x100>;
};
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
sysmgr: sysmgr@ffd06000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd06000 0x300>;
ARM: socfpga: dts: add cpu1-start-addr for Arria 10 Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:41:17 +08:00
cpu1-start-addr = <0xffd06230>;
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
/* Local timer */
timer@ffffc600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xffffc600 0x100>;
interrupts = <1 13 0xf04>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&mpu_periph_clk>;
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
timer0: timer0@ffc02700 {
compatible = "snps,dw-apb-timer";
interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffc02700 0x100>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&l4_sp_clk>;
clock-names = "timer";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
timer1: timer1@ffc02800 {
compatible = "snps,dw-apb-timer";
interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffc02800 0x100>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&l4_sp_clk>;
clock-names = "timer";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd00000 0x100>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd01000 0x100>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
uart0: serial0@ffc02000 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02000 0x100>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10 Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 12:05:21 +08:00
status = "disabled";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
uart1: serial1@ffc02100 {
compatible = "snps,dw-apb-uart";
reg = <0xffc02100 0x100>;
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&l4_sp_clk>;
ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10 Add status = "disabled" in the base DTSI for Arria10. The SDMMC and uart nodes should be enabled in the appropriate board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 12:05:21 +08:00
status = "disabled";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
};
usbphy0: usbphy@0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "okay";
};
usb0: usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0xffff>;
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&usb_clk>;
clock-names = "otg";
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
};
usb1: usb@ffb40000 {
compatible = "snps,dwc2";
reg = <0xffb40000 0xffff>;
interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
};
watchdog0: watchdog@ffd00200 {
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&l4_sys_free_clk>;
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
status = "disabled";
};
watchdog1: watchdog@ffd00300 {
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
ARM: socfpga: dts: add clocks to the Arria10 platform Add all the clock nodes for the Arria10 platform. At the same time, update the peripherals with their respective clocks property. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add the l4_sys_free_clk node
2015-04-03 00:43:20 +08:00
clocks = <&l4_sys_free_clk>;
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
status = "disabled";
};
};
};