2013-07-12 21:50:57 +08:00
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/*
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* Copyright (c) 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Keith Packard <keithp@keithp.com>
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* Mika Kuoppala <mika.kuoppala@intel.com>
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*
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*/
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#include <generated/utsrelease.h>
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#include "i915_drv.h"
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static const char *ring_str(int ring)
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{
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switch (ring) {
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case RCS: return "render";
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case VCS: return "bsd";
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case BCS: return "blt";
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case VECS: return "vebox";
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2014-04-17 10:37:37 +08:00
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case VCS2: return "bsd2";
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2013-07-12 21:50:57 +08:00
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default: return "";
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}
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}
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static const char *pin_flag(int pinned)
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{
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if (pinned > 0)
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return " P";
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else if (pinned < 0)
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return " p";
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else
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return "";
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}
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static const char *tiling_flag(int tiling)
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{
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switch (tiling) {
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default:
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case I915_TILING_NONE: return "";
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case I915_TILING_X: return " X";
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case I915_TILING_Y: return " Y";
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}
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}
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static const char *dirty_flag(int dirty)
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{
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return dirty ? " dirty" : "";
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}
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static const char *purgeable_flag(int purgeable)
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{
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return purgeable ? " purgeable" : "";
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}
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static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
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{
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if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
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e->err = -ENOSPC;
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return false;
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}
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if (e->bytes == e->size - 1 || e->err)
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return false;
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return true;
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}
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static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
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unsigned len)
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{
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if (e->pos + len <= e->start) {
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e->pos += len;
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return false;
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}
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/* First vsnprintf needs to fit in its entirety for memmove */
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if (len >= e->size) {
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e->err = -EIO;
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return false;
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}
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return true;
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}
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static void __i915_error_advance(struct drm_i915_error_state_buf *e,
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unsigned len)
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{
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/* If this is first printf in this window, adjust it so that
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* start position matches start of the buffer
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*/
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if (e->pos < e->start) {
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const size_t off = e->start - e->pos;
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/* Should not happen but be paranoid */
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if (off > len || e->bytes) {
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e->err = -EIO;
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return;
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}
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memmove(e->buf, e->buf + off, len - off);
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e->bytes = len - off;
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e->pos = e->start;
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return;
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}
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e->bytes += len;
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e->pos += len;
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}
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static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
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const char *f, va_list args)
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{
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unsigned len;
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if (!__i915_error_ok(e))
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return;
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/* Seek the first printf which is hits start position */
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if (e->pos < e->start) {
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2013-09-20 17:20:59 +08:00
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va_list tmp;
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va_copy(tmp, args);
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2014-02-07 23:40:50 +08:00
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len = vsnprintf(NULL, 0, f, tmp);
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va_end(tmp);
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if (!__i915_error_seek(e, len))
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2013-07-12 21:50:57 +08:00
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return;
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}
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len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
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if (len >= e->size - e->bytes)
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len = e->size - e->bytes - 1;
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__i915_error_advance(e, len);
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}
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static void i915_error_puts(struct drm_i915_error_state_buf *e,
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const char *str)
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{
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unsigned len;
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if (!__i915_error_ok(e))
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return;
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len = strlen(str);
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/* Seek the first printf which is hits start position */
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if (e->pos < e->start) {
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if (!__i915_error_seek(e, len))
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return;
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}
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if (len >= e->size - e->bytes)
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len = e->size - e->bytes - 1;
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memcpy(e->buf + e->bytes, str, len);
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__i915_error_advance(e, len);
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}
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#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
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#define err_puts(e, s) i915_error_puts(e, s)
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static void print_error_buffers(struct drm_i915_error_state_buf *m,
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const char *name,
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struct drm_i915_error_buffer *err,
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int count)
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{
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2015-04-27 20:41:17 +08:00
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int i;
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2014-08-13 03:05:47 +08:00
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err_printf(m, " %s [%d]:\n", name, count);
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2013-07-12 21:50:57 +08:00
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while (count--) {
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2015-07-30 00:23:56 +08:00
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err_printf(m, " %08x_%08x %8u %02x %02x [ ",
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upper_32_bits(err->gtt_offset),
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lower_32_bits(err->gtt_offset),
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2013-07-12 21:50:57 +08:00
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err->size,
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err->read_domains,
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2015-04-27 20:41:17 +08:00
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err->write_domain);
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2016-03-16 19:00:39 +08:00
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for (i = 0; i < I915_NUM_ENGINES; i++)
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2015-04-27 20:41:17 +08:00
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err_printf(m, "%02x ", err->rseqno[i]);
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err_printf(m, "] %02x", err->wseqno);
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2013-07-12 21:50:57 +08:00
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err_puts(m, pin_flag(err->pinned));
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err_puts(m, tiling_flag(err->tiling));
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err_puts(m, dirty_flag(err->dirty));
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err_puts(m, purgeable_flag(err->purgeable));
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drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl
By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending upon the capabilities of the chipset). This has
a number of uses, with zero-copy downloads to the GPU and efficient
readback making the intermixed streaming of CPU and GPU operations
fairly efficient. This ability has many widespread implications from
faster rendering of client-side software rasterisers (chromium),
mitigation of stalls due to read back (firefox) and to faster pipelining
of texture data (such as pixel buffer objects in GL or data blobs in CL).
v2: Compile with CONFIG_MMU_NOTIFIER
v3: We can sleep while performing invalidate-range, which we can utilise
to drop our page references prior to the kernel manipulating the vma
(for either discard or cloning) and so protect normal users.
v4: Only run the invalidate notifier if the range intercepts the bo.
v5: Prevent userspace from attempting to GTT mmap non-page aligned buffers
v6: Recheck after reacquire mutex for lost mmu.
v7: Fix implicit padding of ioctl struct by rounding to next 64bit boundary.
v8: Fix rebasing error after forwarding porting the back port.
v9: Limit the userptr to page aligned entries. We now expect userspace
to handle all the offset-in-page adjustments itself.
v10: Prevent vma from being copied across fork to avoid issues with cow.
v11: Drop vma behaviour changes -- locking is nigh on impossible.
Use a worker to load user pages to avoid lock inversions.
v12: Use get_task_mm()/mmput() for correct refcounting of mm.
v13: Use a worker to release the mmu_notifier to avoid lock inversion
v14: Decouple mmu_notifier from struct_mutex using a custom mmu_notifer
with its own locking and tree of objects for each mm/mmu_notifier.
v15: Prevent overlapping userptr objects, and invalidate all objects
within the mmu_notifier range
v16: Fix a typo for iterating over multiple objects in the range and
rearrange error path to destroy the mmu_notifier locklessly.
Also close a race between invalidate_range and the get_pages_worker.
v17: Close a race between get_pages_worker/invalidate_range and fresh
allocations of the same userptr range - and notice that
struct_mutex was presumed to be held when during creation it wasn't.
v18: Sigh. Fix the refactor of st_set_pages() to allocate enough memory
for the struct sg_table and to clear it before reporting an error.
v19: Always error out on read-only userptr requests as we don't have the
hardware infrastructure to support them at the moment.
v20: Refuse to implement read-only support until we have the required
infrastructure - but reserve the bit in flags for future use.
v21: use_mm() is not required for get_user_pages(). It is only meant to
be used to fix up the kernel thread's current->mm for use with
copy_user().
v22: Use sg_alloc_table_from_pages for that chunky feeling
v23: Export a function for sanity checking dma-buf rather than encode
userptr details elsewhere, and clean up comments based on
suggestions by Bradley.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: "Gong, Zhipeng" <zhipeng.gong@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Cc: "Volkin, Bradley D" <bradley.d.volkin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com>
[danvet: Frob ioctl allocation to pick the next one - will cause a bit
of fuss with create2 apparently, but such are the rules.]
[danvet2: oops, forgot to git add after manual patch application]
[danvet3: Appease sparse.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-05-16 21:22:37 +08:00
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err_puts(m, err->userptr ? " userptr" : "");
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2013-07-12 21:50:57 +08:00
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err_puts(m, err->ring != -1 ? " " : "");
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err_puts(m, ring_str(err->ring));
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2014-08-22 21:41:39 +08:00
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err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
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2013-07-12 21:50:57 +08:00
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if (err->name)
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err_printf(m, " (name: %d)", err->name);
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if (err->fence_reg != I915_FENCE_REG_NONE)
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err_printf(m, " (fence: %d)", err->fence_reg);
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err_puts(m, "\n");
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err++;
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}
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}
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2013-09-06 21:03:28 +08:00
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static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
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{
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switch (a) {
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case HANGCHECK_IDLE:
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return "idle";
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case HANGCHECK_WAIT:
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return "wait";
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case HANGCHECK_ACTIVE:
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return "active";
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case HANGCHECK_KICK:
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return "kick";
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case HANGCHECK_HUNG:
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return "hung";
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}
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return "unknown";
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}
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2013-07-12 21:50:57 +08:00
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static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
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struct drm_device *dev,
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2014-11-18 20:27:07 +08:00
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struct drm_i915_error_state *error,
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int ring_idx)
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2013-07-12 21:50:57 +08:00
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{
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2014-11-18 20:27:07 +08:00
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struct drm_i915_error_ring *ring = &error->ring[ring_idx];
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2014-01-30 16:19:38 +08:00
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if (!ring->valid)
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2014-01-27 21:52:34 +08:00
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return;
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2014-11-18 20:27:07 +08:00
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err_printf(m, "%s command stream:\n", ring_str(ring_idx));
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2015-04-07 23:20:47 +08:00
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err_printf(m, " START: 0x%08x\n", ring->start);
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err_printf(m, " HEAD: 0x%08x\n", ring->head);
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err_printf(m, " TAIL: 0x%08x\n", ring->tail);
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err_printf(m, " CTL: 0x%08x\n", ring->ctl);
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err_printf(m, " HWS: 0x%08x\n", ring->hws);
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2014-03-21 20:05:47 +08:00
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err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
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2014-01-30 16:19:38 +08:00
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err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir);
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err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr);
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err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone);
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2013-12-11 03:44:43 +08:00
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if (INTEL_INFO(dev)->gen >= 4) {
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2014-03-21 20:05:47 +08:00
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err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
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2014-01-30 16:19:38 +08:00
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err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate);
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err_printf(m, " INSTPS: 0x%08x\n", ring->instps);
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2013-12-11 03:44:43 +08:00
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}
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2014-01-30 16:19:38 +08:00
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err_printf(m, " INSTPM: 0x%08x\n", ring->instpm);
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2014-04-02 07:31:07 +08:00
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err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
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lower_32_bits(ring->faddr));
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2013-07-12 21:50:57 +08:00
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if (INTEL_INFO(dev)->gen >= 6) {
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2014-01-30 16:19:38 +08:00
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err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi);
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err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg);
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2013-07-12 21:50:57 +08:00
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err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n",
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2014-01-30 16:19:38 +08:00
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ring->semaphore_mboxes[0],
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ring->semaphore_seqno[0]);
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2013-07-12 21:50:57 +08:00
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err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n",
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2014-01-30 16:19:38 +08:00
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ring->semaphore_mboxes[1],
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ring->semaphore_seqno[1]);
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2013-08-13 07:53:04 +08:00
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if (HAS_VEBOX(dev)) {
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err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n",
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2014-01-30 16:19:38 +08:00
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ring->semaphore_mboxes[2],
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ring->semaphore_seqno[2]);
|
2013-08-13 07:53:04 +08:00
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
2014-01-30 16:19:40 +08:00
|
|
|
if (USES_PPGTT(dev)) {
|
|
|
|
err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
err_printf(m, " PDP%d: 0x%016llx\n",
|
|
|
|
i, ring->vm_info.pdp[i]);
|
|
|
|
} else {
|
|
|
|
err_printf(m, " PP_DIR_BASE: 0x%08x\n",
|
|
|
|
ring->vm_info.pp_dir_base);
|
|
|
|
}
|
|
|
|
}
|
2014-01-30 16:19:38 +08:00
|
|
|
err_printf(m, " seqno: 0x%08x\n", ring->seqno);
|
|
|
|
err_printf(m, " waiting: %s\n", yesno(ring->waiting));
|
|
|
|
err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head);
|
|
|
|
err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail);
|
2013-09-06 21:03:28 +08:00
|
|
|
err_printf(m, " hangcheck: %s [%d]\n",
|
2014-01-30 16:19:38 +08:00
|
|
|
hangcheck_action_to_str(ring->hangcheck_action),
|
|
|
|
ring->hangcheck_score);
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
|
|
|
|
{
|
|
|
|
va_list args;
|
|
|
|
|
|
|
|
va_start(args, f);
|
|
|
|
i915_error_vprintf(e, f, args);
|
|
|
|
va_end(args);
|
|
|
|
}
|
|
|
|
|
2014-02-25 23:11:24 +08:00
|
|
|
static void print_error_obj(struct drm_i915_error_state_buf *m,
|
|
|
|
struct drm_i915_error_object *obj)
|
|
|
|
{
|
|
|
|
int page, offset, elt;
|
|
|
|
|
|
|
|
for (page = offset = 0; page < obj->page_count; page++) {
|
|
|
|
for (elt = 0; elt < PAGE_SIZE/4; elt++) {
|
|
|
|
err_printf(m, "%08x : %08x\n", offset,
|
|
|
|
obj->pages[page][elt]);
|
|
|
|
offset += 4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
|
|
|
|
const struct i915_error_state_file_priv *error_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = error_priv->dev;
|
2014-03-31 19:27:21 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-12 21:50:57 +08:00
|
|
|
struct drm_i915_error_state *error = error_priv->error;
|
2014-07-01 00:53:41 +08:00
|
|
|
struct drm_i915_error_object *obj;
|
2014-02-25 23:11:24 +08:00
|
|
|
int i, j, offset, elt;
|
|
|
|
int max_hangcheck_score;
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
if (!error) {
|
|
|
|
err_printf(m, "no error state collected\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2014-02-25 23:11:25 +08:00
|
|
|
err_printf(m, "%s\n", error->error_msg);
|
2013-07-12 21:50:57 +08:00
|
|
|
err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
|
|
|
|
error->time.tv_usec);
|
|
|
|
err_printf(m, "Kernel: " UTS_RELEASE "\n");
|
2014-02-25 23:11:24 +08:00
|
|
|
max_hangcheck_score = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
|
|
|
|
if (error->ring[i].hangcheck_score > max_hangcheck_score)
|
|
|
|
max_hangcheck_score = error->ring[i].hangcheck_score;
|
|
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
|
|
|
|
if (error->ring[i].hangcheck_score == max_hangcheck_score &&
|
|
|
|
error->ring[i].pid != -1) {
|
|
|
|
err_printf(m, "Active process (on ring %s): %s [%d]\n",
|
|
|
|
ring_str(i),
|
|
|
|
error->ring[i].comm,
|
|
|
|
error->ring[i].pid);
|
|
|
|
}
|
|
|
|
}
|
2014-02-25 23:11:27 +08:00
|
|
|
err_printf(m, "Reset count: %u\n", error->reset_count);
|
2014-02-25 23:11:28 +08:00
|
|
|
err_printf(m, "Suspend count: %u\n", error->suspend_count);
|
2013-10-04 19:53:40 +08:00
|
|
|
err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
|
2016-01-29 01:18:41 +08:00
|
|
|
err_printf(m, "PCI Revision: 0x%02x\n", dev->pdev->revision);
|
|
|
|
err_printf(m, "PCI Subsystem: %04x:%04x\n",
|
|
|
|
dev->pdev->subsystem_vendor,
|
|
|
|
dev->pdev->subsystem_device);
|
2015-08-08 03:24:15 +08:00
|
|
|
err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
|
2015-10-29 21:21:19 +08:00
|
|
|
|
|
|
|
if (HAS_CSR(dev)) {
|
|
|
|
struct intel_csr *csr = &dev_priv->csr;
|
|
|
|
|
|
|
|
err_printf(m, "DMC loaded: %s\n",
|
|
|
|
yesno(csr->dmc_payload != NULL));
|
|
|
|
err_printf(m, "DMC fw version: %d.%d\n",
|
|
|
|
CSR_VERSION_MAJOR(csr->version),
|
|
|
|
CSR_VERSION_MINOR(csr->version));
|
|
|
|
}
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
err_printf(m, "EIR: 0x%08x\n", error->eir);
|
|
|
|
err_printf(m, "IER: 0x%08x\n", error->ier);
|
2014-08-06 01:07:13 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
err_printf(m, "GTIER gt %d: 0x%08x\n", i,
|
|
|
|
error->gtier[i]);
|
|
|
|
} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
|
|
|
|
err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
|
2013-07-12 21:50:57 +08:00
|
|
|
err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
|
|
|
|
err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
|
|
|
|
err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
|
|
|
|
err_printf(m, "CCID: 0x%08x\n", error->ccid);
|
2013-09-26 00:34:55 +08:00
|
|
|
err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++)
|
|
|
|
err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
|
|
|
|
err_printf(m, " INSTDONE_%d: 0x%08x\n", i,
|
|
|
|
error->extra_instdone[i]);
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
|
|
|
err_printf(m, "ERROR: 0x%08x\n", error->error);
|
2015-03-24 20:54:19 +08:00
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 8)
|
|
|
|
err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
|
|
|
|
error->fault_data1, error->fault_data0);
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen == 7)
|
|
|
|
err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
|
|
|
|
|
2014-11-18 20:27:07 +08:00
|
|
|
for (i = 0; i < ARRAY_SIZE(error->ring); i++)
|
|
|
|
i915_ring_error_state(m, dev, error, i);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-08-13 03:05:47 +08:00
|
|
|
for (i = 0; i < error->vm_count; i++) {
|
|
|
|
err_printf(m, "vm[%d]\n", i);
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
print_error_buffers(m, "Active",
|
2014-08-13 03:05:47 +08:00
|
|
|
error->active_bo[i],
|
|
|
|
error->active_bo_count[i]);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
print_error_buffers(m, "Pinned",
|
2014-08-13 03:05:47 +08:00
|
|
|
error->pinned_bo[i],
|
|
|
|
error->pinned_bo_count[i]);
|
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
|
2014-02-25 23:11:24 +08:00
|
|
|
obj = error->ring[i].batchbuffer;
|
|
|
|
if (obj) {
|
2016-03-16 19:00:38 +08:00
|
|
|
err_puts(m, dev_priv->engine[i].name);
|
2014-02-25 23:11:24 +08:00
|
|
|
if (error->ring[i].pid != -1)
|
|
|
|
err_printf(m, " (submitted by %s [%d])",
|
|
|
|
error->ring[i].comm,
|
|
|
|
error->ring[i].pid);
|
2015-07-30 00:23:56 +08:00
|
|
|
err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
|
|
|
|
upper_32_bits(obj->gtt_offset),
|
|
|
|
lower_32_bits(obj->gtt_offset));
|
2014-02-25 23:11:24 +08:00
|
|
|
print_error_obj(m, obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
obj = error->ring[i].wa_batchbuffer;
|
|
|
|
if (obj) {
|
|
|
|
err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
|
2016-03-16 19:00:38 +08:00
|
|
|
dev_priv->engine[i].name,
|
2015-07-30 00:23:56 +08:00
|
|
|
lower_32_bits(obj->gtt_offset));
|
2014-02-25 23:11:24 +08:00
|
|
|
print_error_obj(m, obj);
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (error->ring[i].num_requests) {
|
|
|
|
err_printf(m, "%s --- %d requests\n",
|
2016-03-16 19:00:38 +08:00
|
|
|
dev_priv->engine[i].name,
|
2013-07-12 21:50:57 +08:00
|
|
|
error->ring[i].num_requests);
|
|
|
|
for (j = 0; j < error->ring[i].num_requests; j++) {
|
|
|
|
err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n",
|
|
|
|
error->ring[i].requests[j].seqno,
|
|
|
|
error->ring[i].requests[j].jiffies,
|
|
|
|
error->ring[i].requests[j].tail);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((obj = error->ring[i].ringbuffer)) {
|
|
|
|
err_printf(m, "%s --- ringbuffer = 0x%08x\n",
|
2016-03-16 19:00:38 +08:00
|
|
|
dev_priv->engine[i].name,
|
2015-07-30 00:23:56 +08:00
|
|
|
lower_32_bits(obj->gtt_offset));
|
2014-02-25 23:11:24 +08:00
|
|
|
print_error_obj(m, obj);
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
2014-01-30 16:19:38 +08:00
|
|
|
if ((obj = error->ring[i].hws_page)) {
|
2015-09-16 01:03:01 +08:00
|
|
|
u64 hws_offset = obj->gtt_offset;
|
|
|
|
u32 *hws_page = &obj->pages[0][0];
|
|
|
|
|
|
|
|
if (i915.enable_execlists) {
|
|
|
|
hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
|
|
|
|
hws_page = &obj->pages[LRC_PPHWSP_PN][0];
|
|
|
|
}
|
drm/i915: Integrate GuC-based command submission
GuC-based submission is mostly the same as execlist mode, up to
intel_logical_ring_advance_and_submit(), where the context being
dispatched would be added to the execlist queue; at this point
we submit the context to the GuC backend instead.
There are, however, a few other changes also required, notably:
1. Contexts must be pinned at GGTT addresses accessible by the GuC
i.e. NOT in the range [0..WOPCM_SIZE), so we have to add the
PIN_OFFSET_BIAS flag to the relevant GGTT-pinning calls.
2. The GuC's TLB must be invalidated after a context is pinned at
a new GGTT address.
3. GuC firmware uses the one page before Ring Context as shared data.
Therefore, whenever driver wants to get base address of LRC, we
will offset one page for it. LRC_PPHWSP_PN is defined as the page
number of LRCA.
4. In the work queue used to pass requests to the GuC, the GuC
firmware requires the ring-tail-offset to be represented as an
11-bit value, expressed in QWords. Therefore, the ringbuffer
size must be reduced to the representable range (4 pages).
v2:
Defer adding #defines until needed [Chris Wilson]
Rationalise type declarations [Chris Wilson]
v4:
Squashed kerneldoc patch into here [Daniel Vetter]
v5:
Update request->tail in code common to both GuC and execlist modes.
Add a private version of lr_context_update(), as sharing the
execlist version leads to race conditions when the CPU and
the GuC both update TAIL in the context image.
Conversion of error-captured HWS page to string must account
for offset from start of object to actual HWS (LRC_PPHWSP_PN).
Issue: VIZ-4884
Signed-off-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-12 22:43:43 +08:00
|
|
|
err_printf(m, "%s --- HW Status = 0x%08llx\n",
|
2016-03-16 19:00:38 +08:00
|
|
|
dev_priv->engine[i].name, hws_offset);
|
2014-01-24 06:40:36 +08:00
|
|
|
offset = 0;
|
|
|
|
for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
|
|
|
|
err_printf(m, "[%04x] %08x %08x %08x %08x\n",
|
|
|
|
offset,
|
2015-09-16 01:03:01 +08:00
|
|
|
hws_page[elt],
|
|
|
|
hws_page[elt+1],
|
|
|
|
hws_page[elt+2],
|
|
|
|
hws_page[elt+3]);
|
2014-01-24 06:40:36 +08:00
|
|
|
offset += 16;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-03-01 19:24:36 +08:00
|
|
|
obj = error->ring[i].wa_ctx;
|
|
|
|
if (obj) {
|
|
|
|
u64 wa_ctx_offset = obj->gtt_offset;
|
|
|
|
u32 *wa_ctx_page = &obj->pages[0][0];
|
2016-03-16 19:00:38 +08:00
|
|
|
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
|
2016-03-16 19:00:36 +08:00
|
|
|
u32 wa_ctx_size = (engine->wa_ctx.indirect_ctx.size +
|
|
|
|
engine->wa_ctx.per_ctx.size);
|
2016-03-01 19:24:36 +08:00
|
|
|
|
|
|
|
err_printf(m, "%s --- WA ctx batch buffer = 0x%08llx\n",
|
2016-03-16 19:00:38 +08:00
|
|
|
dev_priv->engine[i].name, wa_ctx_offset);
|
2016-03-01 19:24:36 +08:00
|
|
|
offset = 0;
|
|
|
|
for (elt = 0; elt < wa_ctx_size; elt += 4) {
|
|
|
|
err_printf(m, "[%04x] %08x %08x %08x %08x\n",
|
|
|
|
offset,
|
|
|
|
wa_ctx_page[elt + 0],
|
|
|
|
wa_ctx_page[elt + 1],
|
|
|
|
wa_ctx_page[elt + 2],
|
|
|
|
wa_ctx_page[elt + 3]);
|
|
|
|
offset += 16;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-01-27 21:52:34 +08:00
|
|
|
if ((obj = error->ring[i].ctx)) {
|
2013-07-12 21:50:57 +08:00
|
|
|
err_printf(m, "%s --- HW Context = 0x%08x\n",
|
2016-03-16 19:00:38 +08:00
|
|
|
dev_priv->engine[i].name,
|
2015-07-30 00:23:56 +08:00
|
|
|
lower_32_bits(obj->gtt_offset));
|
2014-04-06 05:55:53 +08:00
|
|
|
print_error_obj(m, obj);
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-01 00:53:41 +08:00
|
|
|
if ((obj = error->semaphore_obj)) {
|
2015-07-30 00:23:56 +08:00
|
|
|
err_printf(m, "Semaphore page = 0x%08x\n",
|
|
|
|
lower_32_bits(obj->gtt_offset));
|
2014-07-01 00:53:41 +08:00
|
|
|
for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
|
|
|
|
err_printf(m, "[%04x] %08x %08x %08x %08x\n",
|
|
|
|
elt * 4,
|
|
|
|
obj->pages[0][elt],
|
|
|
|
obj->pages[0][elt+1],
|
|
|
|
obj->pages[0][elt+2],
|
|
|
|
obj->pages[0][elt+3]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
if (error->overlay)
|
|
|
|
intel_overlay_print_error_state(m, error->overlay);
|
|
|
|
|
|
|
|
if (error->display)
|
|
|
|
intel_display_print_error_state(m, dev, error->display);
|
|
|
|
|
|
|
|
out:
|
|
|
|
if (m->bytes == 0 && m->err)
|
|
|
|
return m->err;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
|
2014-08-22 21:41:39 +08:00
|
|
|
struct drm_i915_private *i915,
|
2013-07-12 21:50:57 +08:00
|
|
|
size_t count, loff_t pos)
|
|
|
|
{
|
|
|
|
memset(ebuf, 0, sizeof(*ebuf));
|
2014-08-22 21:41:39 +08:00
|
|
|
ebuf->i915 = i915;
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
/* We need to have enough room to store any i915_error_state printf
|
|
|
|
* so that we can move it to start position.
|
|
|
|
*/
|
|
|
|
ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
|
|
|
|
ebuf->buf = kmalloc(ebuf->size,
|
|
|
|
GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
|
|
|
|
|
|
|
|
if (ebuf->buf == NULL) {
|
|
|
|
ebuf->size = PAGE_SIZE;
|
|
|
|
ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ebuf->buf == NULL) {
|
|
|
|
ebuf->size = 128;
|
|
|
|
ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ebuf->buf == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
ebuf->start = pos;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i915_error_object_free(struct drm_i915_error_object *obj)
|
|
|
|
{
|
|
|
|
int page;
|
|
|
|
|
|
|
|
if (obj == NULL)
|
|
|
|
return;
|
|
|
|
|
|
|
|
for (page = 0; page < obj->page_count; page++)
|
|
|
|
kfree(obj->pages[page]);
|
|
|
|
|
|
|
|
kfree(obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i915_error_state_free(struct kref *error_ref)
|
|
|
|
{
|
|
|
|
struct drm_i915_error_state *error = container_of(error_ref,
|
|
|
|
typeof(*error), ref);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
|
|
|
|
i915_error_object_free(error->ring[i].batchbuffer);
|
2015-05-04 22:44:11 +08:00
|
|
|
i915_error_object_free(error->ring[i].wa_batchbuffer);
|
2013-07-12 21:50:57 +08:00
|
|
|
i915_error_object_free(error->ring[i].ringbuffer);
|
2014-01-30 16:19:38 +08:00
|
|
|
i915_error_object_free(error->ring[i].hws_page);
|
2013-07-12 21:50:57 +08:00
|
|
|
i915_error_object_free(error->ring[i].ctx);
|
|
|
|
kfree(error->ring[i].requests);
|
2016-03-01 19:24:36 +08:00
|
|
|
i915_error_object_free(error->ring[i].wa_ctx);
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
2014-07-01 00:53:41 +08:00
|
|
|
i915_error_object_free(error->semaphore_obj);
|
2015-03-20 17:41:03 +08:00
|
|
|
|
|
|
|
for (i = 0; i < error->vm_count; i++)
|
|
|
|
kfree(error->active_bo[i]);
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
kfree(error->active_bo);
|
2015-03-20 17:41:03 +08:00
|
|
|
kfree(error->active_bo_count);
|
|
|
|
kfree(error->pinned_bo);
|
|
|
|
kfree(error->pinned_bo_count);
|
2013-07-12 21:50:57 +08:00
|
|
|
kfree(error->overlay);
|
|
|
|
kfree(error->display);
|
|
|
|
kfree(error);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct drm_i915_error_object *
|
2014-08-13 03:05:49 +08:00
|
|
|
i915_error_object_create(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_i915_gem_object *src,
|
|
|
|
struct i915_address_space *vm)
|
2013-07-12 21:50:57 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_error_object *dst;
|
2014-10-24 19:42:33 +08:00
|
|
|
struct i915_vma *vma = NULL;
|
2014-08-13 03:05:49 +08:00
|
|
|
int num_pages;
|
2014-08-13 03:05:48 +08:00
|
|
|
bool use_ggtt;
|
|
|
|
int i = 0;
|
2015-07-30 00:23:56 +08:00
|
|
|
u64 reloc_offset;
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
if (src == NULL || src->pages == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
2014-08-13 03:05:49 +08:00
|
|
|
num_pages = src->base.size >> PAGE_SHIFT;
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
|
|
|
|
if (dst == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
2014-08-13 03:05:50 +08:00
|
|
|
if (i915_gem_obj_bound(src, vm))
|
|
|
|
dst->gtt_offset = i915_gem_obj_offset(src, vm);
|
|
|
|
else
|
|
|
|
dst->gtt_offset = -1;
|
2014-08-13 03:05:48 +08:00
|
|
|
|
|
|
|
reloc_offset = dst->gtt_offset;
|
2014-10-24 19:42:33 +08:00
|
|
|
if (i915_is_ggtt(vm))
|
|
|
|
vma = i915_gem_obj_to_ggtt(src);
|
2014-08-13 03:05:48 +08:00
|
|
|
use_ggtt = (src->cache_level == I915_CACHE_NONE &&
|
2014-10-24 19:42:33 +08:00
|
|
|
vma && (vma->bound & GLOBAL_BIND) &&
|
2016-03-18 16:42:57 +08:00
|
|
|
reloc_offset + num_pages * PAGE_SIZE <= dev_priv->ggtt.mappable_end);
|
2014-08-13 03:05:48 +08:00
|
|
|
|
|
|
|
/* Cannot access stolen address directly, try to use the aperture */
|
|
|
|
if (src->stolen) {
|
|
|
|
use_ggtt = true;
|
|
|
|
|
2014-10-24 19:42:33 +08:00
|
|
|
if (!(vma && vma->bound & GLOBAL_BIND))
|
2014-08-13 03:05:48 +08:00
|
|
|
goto unwind;
|
|
|
|
|
|
|
|
reloc_offset = i915_gem_obj_ggtt_offset(src);
|
2016-03-18 16:42:57 +08:00
|
|
|
if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->ggtt.mappable_end)
|
2014-08-13 03:05:48 +08:00
|
|
|
goto unwind;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Cannot access snooped pages through the aperture */
|
|
|
|
if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
|
|
|
|
goto unwind;
|
|
|
|
|
|
|
|
dst->page_count = num_pages;
|
|
|
|
while (num_pages--) {
|
2013-07-12 21:50:57 +08:00
|
|
|
unsigned long flags;
|
|
|
|
void *d;
|
|
|
|
|
|
|
|
d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
|
|
|
|
if (d == NULL)
|
|
|
|
goto unwind;
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
2014-08-13 03:05:48 +08:00
|
|
|
if (use_ggtt) {
|
2013-07-12 21:50:57 +08:00
|
|
|
void __iomem *s;
|
|
|
|
|
|
|
|
/* Simply ignore tiling or any overlapping fence.
|
|
|
|
* It's part of the error state, and this hopefully
|
|
|
|
* captures what the GPU read.
|
|
|
|
*/
|
|
|
|
|
2016-03-18 16:42:57 +08:00
|
|
|
s = io_mapping_map_atomic_wc(dev_priv->ggtt.mappable,
|
2013-07-12 21:50:57 +08:00
|
|
|
reloc_offset);
|
|
|
|
memcpy_fromio(d, s, PAGE_SIZE);
|
|
|
|
io_mapping_unmap_atomic(s);
|
|
|
|
} else {
|
|
|
|
struct page *page;
|
|
|
|
void *s;
|
|
|
|
|
|
|
|
page = i915_gem_object_get_page(src, i);
|
|
|
|
|
|
|
|
drm_clflush_pages(&page, 1);
|
|
|
|
|
|
|
|
s = kmap_atomic(page);
|
|
|
|
memcpy(d, s, PAGE_SIZE);
|
|
|
|
kunmap_atomic(s);
|
|
|
|
|
|
|
|
drm_clflush_pages(&page, 1);
|
|
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
|
|
|
2014-08-13 03:05:48 +08:00
|
|
|
dst->pages[i++] = d;
|
2013-07-12 21:50:57 +08:00
|
|
|
reloc_offset += PAGE_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return dst;
|
|
|
|
|
|
|
|
unwind:
|
|
|
|
while (i--)
|
|
|
|
kfree(dst->pages[i]);
|
|
|
|
kfree(dst);
|
|
|
|
return NULL;
|
|
|
|
}
|
2013-12-07 06:10:52 +08:00
|
|
|
#define i915_error_ggtt_object_create(dev_priv, src) \
|
2016-03-18 16:42:57 +08:00
|
|
|
i915_error_object_create((dev_priv), (src), &(dev_priv)->ggtt.base)
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
static void capture_bo(struct drm_i915_error_buffer *err,
|
2014-08-13 03:05:47 +08:00
|
|
|
struct i915_vma *vma)
|
2013-07-12 21:50:57 +08:00
|
|
|
{
|
2014-08-13 03:05:47 +08:00
|
|
|
struct drm_i915_gem_object *obj = vma->obj;
|
2015-04-27 20:41:17 +08:00
|
|
|
int i;
|
2014-08-13 03:05:47 +08:00
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
err->size = obj->base.size;
|
|
|
|
err->name = obj->base.name;
|
2016-03-16 19:00:39 +08:00
|
|
|
for (i = 0; i < I915_NUM_ENGINES; i++)
|
2015-04-27 20:41:17 +08:00
|
|
|
err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
|
2014-11-25 02:49:26 +08:00
|
|
|
err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
|
2014-08-13 03:05:47 +08:00
|
|
|
err->gtt_offset = vma->node.start;
|
2013-07-12 21:50:57 +08:00
|
|
|
err->read_domains = obj->base.read_domains;
|
|
|
|
err->write_domain = obj->base.write_domain;
|
|
|
|
err->fence_reg = obj->fence_reg;
|
|
|
|
err->pinned = 0;
|
2013-12-07 06:10:55 +08:00
|
|
|
if (i915_gem_obj_is_pinned(obj))
|
2013-07-12 21:50:57 +08:00
|
|
|
err->pinned = 1;
|
|
|
|
err->tiling = obj->tiling_mode;
|
|
|
|
err->dirty = obj->dirty;
|
|
|
|
err->purgeable = obj->madv != I915_MADV_WILLNEED;
|
drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl
By exporting the ability to map user address and inserting PTEs
representing their backing pages into the GTT, we can exploit UMA in order
to utilize normal application data as a texture source or even as a
render target (depending upon the capabilities of the chipset). This has
a number of uses, with zero-copy downloads to the GPU and efficient
readback making the intermixed streaming of CPU and GPU operations
fairly efficient. This ability has many widespread implications from
faster rendering of client-side software rasterisers (chromium),
mitigation of stalls due to read back (firefox) and to faster pipelining
of texture data (such as pixel buffer objects in GL or data blobs in CL).
v2: Compile with CONFIG_MMU_NOTIFIER
v3: We can sleep while performing invalidate-range, which we can utilise
to drop our page references prior to the kernel manipulating the vma
(for either discard or cloning) and so protect normal users.
v4: Only run the invalidate notifier if the range intercepts the bo.
v5: Prevent userspace from attempting to GTT mmap non-page aligned buffers
v6: Recheck after reacquire mutex for lost mmu.
v7: Fix implicit padding of ioctl struct by rounding to next 64bit boundary.
v8: Fix rebasing error after forwarding porting the back port.
v9: Limit the userptr to page aligned entries. We now expect userspace
to handle all the offset-in-page adjustments itself.
v10: Prevent vma from being copied across fork to avoid issues with cow.
v11: Drop vma behaviour changes -- locking is nigh on impossible.
Use a worker to load user pages to avoid lock inversions.
v12: Use get_task_mm()/mmput() for correct refcounting of mm.
v13: Use a worker to release the mmu_notifier to avoid lock inversion
v14: Decouple mmu_notifier from struct_mutex using a custom mmu_notifer
with its own locking and tree of objects for each mm/mmu_notifier.
v15: Prevent overlapping userptr objects, and invalidate all objects
within the mmu_notifier range
v16: Fix a typo for iterating over multiple objects in the range and
rearrange error path to destroy the mmu_notifier locklessly.
Also close a race between invalidate_range and the get_pages_worker.
v17: Close a race between get_pages_worker/invalidate_range and fresh
allocations of the same userptr range - and notice that
struct_mutex was presumed to be held when during creation it wasn't.
v18: Sigh. Fix the refactor of st_set_pages() to allocate enough memory
for the struct sg_table and to clear it before reporting an error.
v19: Always error out on read-only userptr requests as we don't have the
hardware infrastructure to support them at the moment.
v20: Refuse to implement read-only support until we have the required
infrastructure - but reserve the bit in flags for future use.
v21: use_mm() is not required for get_user_pages(). It is only meant to
be used to fix up the kernel thread's current->mm for use with
copy_user().
v22: Use sg_alloc_table_from_pages for that chunky feeling
v23: Export a function for sanity checking dma-buf rather than encode
userptr details elsewhere, and clean up comments based on
suggestions by Bradley.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: "Gong, Zhipeng" <zhipeng.gong@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Cc: "Volkin, Bradley D" <bradley.d.volkin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com>
[danvet: Frob ioctl allocation to pick the next one - will cause a bit
of fuss with create2 apparently, but such are the rules.]
[danvet2: oops, forgot to git add after manual patch application]
[danvet3: Appease sparse.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-05-16 21:22:37 +08:00
|
|
|
err->userptr = obj->userptr.mm != NULL;
|
2015-04-27 20:41:17 +08:00
|
|
|
err->ring = obj->last_write_req ?
|
2016-03-16 19:00:39 +08:00
|
|
|
i915_gem_request_get_engine(obj->last_write_req)->id : -1;
|
2013-07-12 21:50:57 +08:00
|
|
|
err->cache_level = obj->cache_level;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 capture_active_bo(struct drm_i915_error_buffer *err,
|
|
|
|
int count, struct list_head *head)
|
|
|
|
{
|
2013-08-01 08:00:14 +08:00
|
|
|
struct i915_vma *vma;
|
2013-07-12 21:50:57 +08:00
|
|
|
int i = 0;
|
|
|
|
|
2016-02-26 19:03:19 +08:00
|
|
|
list_for_each_entry(vma, head, vm_link) {
|
2014-08-13 03:05:47 +08:00
|
|
|
capture_bo(err++, vma);
|
2013-07-12 21:50:57 +08:00
|
|
|
if (++i == count)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
|
2014-08-13 03:05:47 +08:00
|
|
|
int count, struct list_head *head,
|
|
|
|
struct i915_address_space *vm)
|
2013-07-12 21:50:57 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
2014-08-13 03:05:47 +08:00
|
|
|
struct drm_i915_error_buffer * const first = err;
|
|
|
|
struct drm_i915_error_buffer * const last = err + count;
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
list_for_each_entry(obj, head, global_list) {
|
2014-08-13 03:05:47 +08:00
|
|
|
struct i915_vma *vma;
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-08-13 03:05:47 +08:00
|
|
|
if (err == last)
|
2013-07-12 21:50:57 +08:00
|
|
|
break;
|
2014-08-13 03:05:47 +08:00
|
|
|
|
2016-02-26 19:03:19 +08:00
|
|
|
list_for_each_entry(vma, &obj->vma_list, obj_link)
|
2014-12-11 01:27:58 +08:00
|
|
|
if (vma->vm == vm && vma->pin_count > 0)
|
2014-08-13 03:05:47 +08:00
|
|
|
capture_bo(err++, vma);
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
2014-08-13 03:05:47 +08:00
|
|
|
return err - first;
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
2014-02-04 20:18:55 +08:00
|
|
|
/* Generate a semi-unique error code. The code is not meant to have meaning, The
|
|
|
|
* code's only purpose is to try to prevent false duplicated bug reports by
|
|
|
|
* grossly estimating a GPU error state.
|
|
|
|
*
|
|
|
|
* TODO Ideally, hashing the batchbuffer would be a very nice way to determine
|
|
|
|
* the hang if we could strip the GTT offset information from it.
|
|
|
|
*
|
|
|
|
* It's only a small step better than a random number in its current form.
|
|
|
|
*/
|
|
|
|
static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
|
2014-02-25 23:11:25 +08:00
|
|
|
struct drm_i915_error_state *error,
|
|
|
|
int *ring_id)
|
2014-02-04 20:18:55 +08:00
|
|
|
{
|
|
|
|
uint32_t error_code = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* IPEHR would be an ideal way to detect errors, as it's the gross
|
|
|
|
* measure of "the command that hung." However, has some very common
|
|
|
|
* synchronization commands which almost always appear in the case
|
|
|
|
* strictly a client bug. Use instdone to differentiate those some.
|
|
|
|
*/
|
2016-03-16 19:00:39 +08:00
|
|
|
for (i = 0; i < I915_NUM_ENGINES; i++) {
|
2014-02-25 23:11:25 +08:00
|
|
|
if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
|
|
|
|
if (ring_id)
|
|
|
|
*ring_id = i;
|
|
|
|
|
2014-02-04 20:18:55 +08:00
|
|
|
return error->ring[i].ipehr ^ error->ring[i].instdone;
|
2014-02-25 23:11:25 +08:00
|
|
|
}
|
|
|
|
}
|
2014-02-04 20:18:55 +08:00
|
|
|
|
|
|
|
return error_code;
|
|
|
|
}
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
static void i915_gem_record_fences(struct drm_device *dev,
|
|
|
|
struct drm_i915_error_state *error)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int i;
|
|
|
|
|
2014-12-04 22:48:10 +08:00
|
|
|
if (IS_GEN3(dev) || IS_GEN2(dev)) {
|
|
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++)
|
2015-09-21 23:05:14 +08:00
|
|
|
error->fence[i] = I915_READ(FENCE_REG(i));
|
|
|
|
} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
|
|
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++)
|
|
|
|
error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
|
|
|
|
} else if (INTEL_INFO(dev)->gen >= 6) {
|
|
|
|
for (i = 0; i < dev_priv->num_fence_regs; i++)
|
|
|
|
error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
|
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
2014-07-01 00:53:40 +08:00
|
|
|
|
2014-07-01 00:53:41 +08:00
|
|
|
static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_i915_error_state *error,
|
2016-03-16 19:00:37 +08:00
|
|
|
struct intel_engine_cs *engine,
|
2014-07-01 00:53:41 +08:00
|
|
|
struct drm_i915_error_ring *ering)
|
|
|
|
{
|
drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to do that
is at intel_ring_sync_index as below:
/*
* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
v2: Skip when from == to (Damien).
v3: avoid computing idx when from == to (Damien).
use ring == to instead of ring->id == to->id (Damien).
use continue instead of return (Rodrigo).
v4: avoid all unecessary computation (Damien).
reduce idx to loop scope (Damien).
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-18 17:19:40 +08:00
|
|
|
struct intel_engine_cs *to;
|
2014-07-01 00:53:41 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!i915_semaphore_is_enabled(dev_priv->dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!error->semaphore_obj)
|
|
|
|
error->semaphore_obj =
|
2014-11-20 01:38:39 +08:00
|
|
|
i915_error_ggtt_object_create(dev_priv,
|
|
|
|
dev_priv->semaphore_obj);
|
2014-07-01 00:53:41 +08:00
|
|
|
|
2016-03-16 19:00:39 +08:00
|
|
|
for_each_engine(to, dev_priv, i) {
|
drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to do that
is at intel_ring_sync_index as below:
/*
* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
v2: Skip when from == to (Damien).
v3: avoid computing idx when from == to (Damien).
use ring == to instead of ring->id == to->id (Damien).
use continue instead of return (Rodrigo).
v4: avoid all unecessary computation (Damien).
reduce idx to loop scope (Damien).
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-18 17:19:40 +08:00
|
|
|
int idx;
|
|
|
|
u16 signal_offset;
|
|
|
|
u32 *tmp;
|
2014-07-01 00:53:41 +08:00
|
|
|
|
2016-03-16 19:00:37 +08:00
|
|
|
if (engine == to)
|
drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to do that
is at intel_ring_sync_index as below:
/*
* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
v2: Skip when from == to (Damien).
v3: avoid computing idx when from == to (Damien).
use ring == to instead of ring->id == to->id (Damien).
use continue instead of return (Rodrigo).
v4: avoid all unecessary computation (Damien).
reduce idx to loop scope (Damien).
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-18 17:19:40 +08:00
|
|
|
continue;
|
|
|
|
|
2016-03-16 19:00:37 +08:00
|
|
|
signal_offset = (GEN8_SIGNAL_OFFSET(engine, i) & (PAGE_SIZE - 1))
|
2014-08-01 19:51:30 +08:00
|
|
|
/ 4;
|
drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to do that
is at intel_ring_sync_index as below:
/*
* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
v2: Skip when from == to (Damien).
v3: avoid computing idx when from == to (Damien).
use ring == to instead of ring->id == to->id (Damien).
use continue instead of return (Rodrigo).
v4: avoid all unecessary computation (Damien).
reduce idx to loop scope (Damien).
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-18 17:19:40 +08:00
|
|
|
tmp = error->semaphore_obj->pages[0];
|
2016-03-16 19:00:37 +08:00
|
|
|
idx = intel_ring_sync_index(engine, to);
|
drm/i915: Fix possible overflow when recording semaphore states.
semaphore _sync_seqno, _seqno and _mbox are smaller than number of rings.
This optimization is to remove the ring itself from the list and the logic to do that
is at intel_ring_sync_index as below:
/*
* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
*/
v2: Skip when from == to (Damien).
v3: avoid computing idx when from == to (Damien).
use ring == to instead of ring->id == to->id (Damien).
use continue instead of return (Rodrigo).
v4: avoid all unecessary computation (Damien).
reduce idx to loop scope (Damien).
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-07-18 17:19:40 +08:00
|
|
|
|
|
|
|
ering->semaphore_mboxes[idx] = tmp[signal_offset];
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->semaphore_seqno[idx] = engine->semaphore.sync_seqno[idx];
|
2014-07-01 00:53:41 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-07-01 00:53:40 +08:00
|
|
|
static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
|
2016-03-16 19:00:37 +08:00
|
|
|
struct intel_engine_cs *engine,
|
2014-07-01 00:53:40 +08:00
|
|
|
struct drm_i915_error_ring *ering)
|
|
|
|
{
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
|
|
|
|
ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
|
|
|
|
ering->semaphore_seqno[0] = engine->semaphore.sync_seqno[0];
|
|
|
|
ering->semaphore_seqno[1] = engine->semaphore.sync_seqno[1];
|
2014-07-01 00:53:40 +08:00
|
|
|
|
|
|
|
if (HAS_VEBOX(dev_priv->dev)) {
|
|
|
|
ering->semaphore_mboxes[2] =
|
2016-03-16 19:00:37 +08:00
|
|
|
I915_READ(RING_SYNC_2(engine->mmio_base));
|
|
|
|
ering->semaphore_seqno[2] = engine->semaphore.sync_seqno[2];
|
2014-07-01 00:53:40 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
static void i915_record_ring_state(struct drm_device *dev,
|
2014-07-01 00:53:41 +08:00
|
|
|
struct drm_i915_error_state *error,
|
2016-03-16 19:00:37 +08:00
|
|
|
struct intel_engine_cs *engine,
|
2014-01-30 16:19:38 +08:00
|
|
|
struct drm_i915_error_ring *ering)
|
2013-07-12 21:50:57 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
|
|
|
|
ering->fault_reg = I915_READ(RING_FAULT_REG(engine));
|
2014-07-01 00:53:41 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 8)
|
2016-03-16 19:00:37 +08:00
|
|
|
gen8_record_semaphore_state(dev_priv, error, engine,
|
|
|
|
ering);
|
2014-07-01 00:53:41 +08:00
|
|
|
else
|
2016-03-16 19:00:37 +08:00
|
|
|
gen6_record_semaphore_state(dev_priv, engine, ering);
|
2013-08-13 07:53:04 +08:00
|
|
|
}
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
|
|
|
|
ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
|
|
|
|
ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
|
|
|
|
ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base));
|
|
|
|
ering->instps = I915_READ(RING_INSTPS(engine->mmio_base));
|
|
|
|
ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
|
2014-04-02 07:31:07 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
|
|
|
|
ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
|
2014-04-02 07:31:07 +08:00
|
|
|
}
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
|
2013-07-12 21:50:57 +08:00
|
|
|
} else {
|
2014-01-30 16:19:38 +08:00
|
|
|
ering->faddr = I915_READ(DMA_FADD_I8XX);
|
|
|
|
ering->ipeir = I915_READ(IPEIR);
|
|
|
|
ering->ipehr = I915_READ(IPEHR);
|
2015-10-01 04:00:43 +08:00
|
|
|
ering->instdone = I915_READ(GEN2_INSTDONE);
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->waiting = waitqueue_active(&engine->irq_queue);
|
|
|
|
ering->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
|
|
|
|
ering->seqno = engine->get_seqno(engine, false);
|
|
|
|
ering->acthd = intel_ring_get_active_head(engine);
|
|
|
|
ering->start = I915_READ_START(engine);
|
|
|
|
ering->head = I915_READ_HEAD(engine);
|
|
|
|
ering->tail = I915_READ_TAIL(engine);
|
|
|
|
ering->ctl = I915_READ_CTL(engine);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-01-24 06:40:36 +08:00
|
|
|
if (I915_NEED_GFX_HWS(dev)) {
|
drm/i915: Type safe register read/write
Make I915_READ and I915_WRITE more type safe by wrapping the register
offset in a struct. This should eliminate most of the fumbles we've had
with misplaced parens.
This only takes care of normal mmio registers. We could extend the idea
to other register types and define each with its own struct. That way
you wouldn't be able to accidentally pass the wrong thing to a specific
register access function.
The gpio_reg setup is probably the ugliest thing left. But I figure I'd
just leave it for now, and wait for some divine inspiration to strike
before making it nice.
As for the generated code, it's actually a bit better sometimes. Eg.
looking at i915_irq_handler(), we can see the following change:
lea 0x70024(%rdx,%rax,1),%r9d
mov $0x1,%edx
- movslq %r9d,%r9
- mov %r9,%rsi
- mov %r9,-0x58(%rbp)
- callq *0xd8(%rbx)
+ mov %r9d,%esi
+ mov %r9d,-0x48(%rbp)
callq *0xd8(%rbx)
So previously gcc thought the register offset might be signed and
decided to sign extend it, just in case. The rest appears to be
mostly just minor shuffling of instructions.
v2: i915_mmio_reg_{offset,equal,valid}() helpers added
s/_REG/_MMIO/ in the register defines
mo more switch statements left to worry about
ring_emit stuff got sorted in a prep patch
cmd parser, lrc context and w/a batch buildup also in prep patch
vgpu stuff cleaned up and moved to a prep patch
all other unrelated changes split out
v3: Rebased due to BXT DSI/BLC, MOCS, etc.
v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-18 21:33:26 +08:00
|
|
|
i915_reg_t mmio;
|
2014-01-24 06:40:36 +08:00
|
|
|
|
|
|
|
if (IS_GEN7(dev)) {
|
2016-03-16 19:00:37 +08:00
|
|
|
switch (engine->id) {
|
2014-01-24 06:40:36 +08:00
|
|
|
default:
|
|
|
|
case RCS:
|
|
|
|
mmio = RENDER_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
case BCS:
|
|
|
|
mmio = BLT_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
case VCS:
|
|
|
|
mmio = BSD_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
case VECS:
|
|
|
|
mmio = VEBOX_HWS_PGA_GEN7;
|
|
|
|
break;
|
|
|
|
}
|
2016-03-16 19:00:37 +08:00
|
|
|
} else if (IS_GEN6(engine->dev)) {
|
|
|
|
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
|
2014-01-24 06:40:36 +08:00
|
|
|
} else {
|
|
|
|
/* XXX: gen8 returns to sanity */
|
2016-03-16 19:00:37 +08:00
|
|
|
mmio = RING_HWS_PGA(engine->mmio_base);
|
2014-01-24 06:40:36 +08:00
|
|
|
}
|
|
|
|
|
2014-01-30 16:19:38 +08:00
|
|
|
ering->hws = I915_READ(mmio);
|
2014-01-24 06:40:36 +08:00
|
|
|
}
|
|
|
|
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->hangcheck_score = engine->hangcheck.score;
|
|
|
|
ering->hangcheck_action = engine->hangcheck.action;
|
2014-01-30 16:19:40 +08:00
|
|
|
|
|
|
|
if (USES_PPGTT(dev)) {
|
|
|
|
int i;
|
|
|
|
|
2016-03-16 19:00:37 +08:00
|
|
|
ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
|
2014-01-30 16:19:40 +08:00
|
|
|
|
2014-12-03 20:55:27 +08:00
|
|
|
if (IS_GEN6(dev))
|
|
|
|
ering->vm_info.pp_dir_base =
|
2016-03-16 19:00:37 +08:00
|
|
|
I915_READ(RING_PP_DIR_BASE_READ(engine));
|
2014-12-03 20:55:27 +08:00
|
|
|
else if (IS_GEN7(dev))
|
|
|
|
ering->vm_info.pp_dir_base =
|
2016-03-16 19:00:37 +08:00
|
|
|
I915_READ(RING_PP_DIR_BASE(engine));
|
2014-12-03 20:55:27 +08:00
|
|
|
else if (INTEL_INFO(dev)->gen >= 8)
|
2014-01-30 16:19:40 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
ering->vm_info.pdp[i] =
|
2016-03-16 19:00:37 +08:00
|
|
|
I915_READ(GEN8_RING_PDP_UDW(engine, i));
|
2014-01-30 16:19:40 +08:00
|
|
|
ering->vm_info.pdp[i] <<= 32;
|
|
|
|
ering->vm_info.pdp[i] |=
|
2016-03-16 19:00:37 +08:00
|
|
|
I915_READ(GEN8_RING_PDP_LDW(engine, i));
|
2014-01-30 16:19:40 +08:00
|
|
|
}
|
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2016-03-16 19:00:37 +08:00
|
|
|
static void i915_gem_record_active_context(struct intel_engine_cs *engine,
|
2013-07-12 21:50:57 +08:00
|
|
|
struct drm_i915_error_state *error,
|
|
|
|
struct drm_i915_error_ring *ering)
|
|
|
|
{
|
2016-03-16 19:00:37 +08:00
|
|
|
struct drm_i915_private *dev_priv = engine->dev->dev_private;
|
2013-07-12 21:50:57 +08:00
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
|
|
|
|
/* Currently render ring is the only HW context user */
|
2016-03-16 19:00:37 +08:00
|
|
|
if (engine->id != RCS || !error->ccid)
|
2013-07-12 21:50:57 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
2014-07-02 02:17:41 +08:00
|
|
|
if (!i915_gem_obj_ggtt_bound(obj))
|
|
|
|
continue;
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
|
2014-04-06 05:55:53 +08:00
|
|
|
ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
|
2013-07-12 21:50:57 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i915_gem_record_rings(struct drm_device *dev,
|
|
|
|
struct drm_i915_error_state *error)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_gem_request *request;
|
|
|
|
int i, count;
|
|
|
|
|
2016-03-16 19:00:39 +08:00
|
|
|
for (i = 0; i < I915_NUM_ENGINES; i++) {
|
2016-03-16 19:00:38 +08:00
|
|
|
struct intel_engine_cs *engine = &dev_priv->engine[i];
|
2014-07-25 00:04:43 +08:00
|
|
|
struct intel_ringbuffer *rbuf;
|
2014-01-27 21:52:34 +08:00
|
|
|
|
2014-06-10 19:09:29 +08:00
|
|
|
error->ring[i].pid = -1;
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
if (engine->dev == NULL)
|
2014-01-27 21:52:34 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
error->ring[i].valid = true;
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
i915_record_ring_state(dev, error, engine, &error->ring[i]);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
request = i915_gem_find_active_request(engine);
|
2014-02-25 23:11:24 +08:00
|
|
|
if (request) {
|
2014-08-06 21:04:53 +08:00
|
|
|
struct i915_address_space *vm;
|
|
|
|
|
|
|
|
vm = request->ctx && request->ctx->ppgtt ?
|
|
|
|
&request->ctx->ppgtt->base :
|
2016-03-18 16:42:57 +08:00
|
|
|
&dev_priv->ggtt.base;
|
2014-08-06 21:04:53 +08:00
|
|
|
|
2014-02-25 23:11:24 +08:00
|
|
|
/* We need to copy these to an anonymous buffer
|
|
|
|
* as the simplest method to avoid being overwritten
|
|
|
|
* by userspace.
|
|
|
|
*/
|
|
|
|
error->ring[i].batchbuffer =
|
|
|
|
i915_error_object_create(dev_priv,
|
|
|
|
request->batch_obj,
|
2014-08-06 21:04:53 +08:00
|
|
|
vm);
|
2014-02-25 23:11:24 +08:00
|
|
|
|
2014-08-13 03:05:49 +08:00
|
|
|
if (HAS_BROKEN_CS_TLB(dev_priv->dev))
|
2014-02-25 23:11:24 +08:00
|
|
|
error->ring[i].wa_batchbuffer =
|
|
|
|
i915_error_ggtt_object_create(dev_priv,
|
2016-03-16 19:00:36 +08:00
|
|
|
engine->scratch.obj);
|
2014-02-25 23:11:24 +08:00
|
|
|
|
2015-02-12 16:26:02 +08:00
|
|
|
if (request->pid) {
|
2014-02-25 23:11:24 +08:00
|
|
|
struct task_struct *task;
|
|
|
|
|
|
|
|
rcu_read_lock();
|
2015-02-12 16:26:02 +08:00
|
|
|
task = pid_task(request->pid, PIDTYPE_PID);
|
2014-02-25 23:11:24 +08:00
|
|
|
if (task) {
|
|
|
|
strcpy(error->ring[i].comm, task->comm);
|
|
|
|
error->ring[i].pid = task->pid;
|
|
|
|
}
|
|
|
|
rcu_read_unlock();
|
|
|
|
}
|
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-07-25 00:04:43 +08:00
|
|
|
if (i915.enable_execlists) {
|
|
|
|
/* TODO: This is only a small fix to keep basic error
|
|
|
|
* capture working, but we need to add more information
|
|
|
|
* for it to be useful (e.g. dump the context being
|
|
|
|
* executed).
|
|
|
|
*/
|
|
|
|
if (request)
|
2016-03-16 19:00:36 +08:00
|
|
|
rbuf = request->ctx->engine[engine->id].ringbuf;
|
2014-07-25 00:04:43 +08:00
|
|
|
else
|
2016-03-16 19:00:36 +08:00
|
|
|
rbuf = dev_priv->kernel_context->engine[engine->id].ringbuf;
|
2014-07-25 00:04:43 +08:00
|
|
|
} else
|
2016-03-16 19:00:36 +08:00
|
|
|
rbuf = engine->buffer;
|
2014-07-25 00:04:43 +08:00
|
|
|
|
|
|
|
error->ring[i].cpu_ring_head = rbuf->head;
|
|
|
|
error->ring[i].cpu_ring_tail = rbuf->tail;
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
error->ring[i].ringbuffer =
|
2014-07-25 00:04:43 +08:00
|
|
|
i915_error_ggtt_object_create(dev_priv, rbuf->obj);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-08-13 03:05:49 +08:00
|
|
|
error->ring[i].hws_page =
|
2016-03-16 19:00:36 +08:00
|
|
|
i915_error_ggtt_object_create(dev_priv,
|
|
|
|
engine->status_page.obj);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
if (engine->wa_ctx.obj) {
|
2016-03-01 19:24:36 +08:00
|
|
|
error->ring[i].wa_ctx =
|
|
|
|
i915_error_ggtt_object_create(dev_priv,
|
2016-03-16 19:00:36 +08:00
|
|
|
engine->wa_ctx.obj);
|
2016-03-01 19:24:36 +08:00
|
|
|
}
|
|
|
|
|
2016-03-16 19:00:36 +08:00
|
|
|
i915_gem_record_active_context(engine, error, &error->ring[i]);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
count = 0;
|
2016-03-16 19:00:36 +08:00
|
|
|
list_for_each_entry(request, &engine->request_list, list)
|
2013-07-12 21:50:57 +08:00
|
|
|
count++;
|
|
|
|
|
|
|
|
error->ring[i].num_requests = count;
|
|
|
|
error->ring[i].requests =
|
2013-09-21 06:35:38 +08:00
|
|
|
kcalloc(count, sizeof(*error->ring[i].requests),
|
2013-07-12 21:50:57 +08:00
|
|
|
GFP_ATOMIC);
|
|
|
|
if (error->ring[i].requests == NULL) {
|
|
|
|
error->ring[i].num_requests = 0;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
count = 0;
|
2016-03-16 19:00:36 +08:00
|
|
|
list_for_each_entry(request, &engine->request_list, list) {
|
2013-07-12 21:50:57 +08:00
|
|
|
struct drm_i915_error_request *erq;
|
|
|
|
|
2015-10-20 00:51:57 +08:00
|
|
|
if (count >= error->ring[i].num_requests) {
|
|
|
|
/*
|
|
|
|
* If the ring request list was changed in
|
|
|
|
* between the point where the error request
|
|
|
|
* list was created and dimensioned and this
|
|
|
|
* point then just exit early to avoid crashes.
|
|
|
|
*
|
|
|
|
* We don't need to communicate that the
|
|
|
|
* request list changed state during error
|
|
|
|
* state capture and that the error state is
|
|
|
|
* slightly incorrect as a consequence since we
|
|
|
|
* are typically only interested in the request
|
|
|
|
* list state at the point of error state
|
|
|
|
* capture, not in any changes happening during
|
|
|
|
* the capture.
|
|
|
|
*/
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
erq = &error->ring[i].requests[count++];
|
|
|
|
erq->seqno = request->seqno;
|
|
|
|
erq->jiffies = request->emitted_jiffies;
|
2015-01-15 21:10:37 +08:00
|
|
|
erq->tail = request->postfix;
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-08-01 08:00:15 +08:00
|
|
|
/* FIXME: Since pin count/bound list is global, we duplicate what we capture per
|
|
|
|
* VM.
|
|
|
|
*/
|
|
|
|
static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_i915_error_state *error,
|
|
|
|
struct i915_address_space *vm,
|
|
|
|
const int ndx)
|
2013-07-12 21:50:57 +08:00
|
|
|
{
|
2013-08-01 08:00:15 +08:00
|
|
|
struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
|
2013-07-12 21:50:57 +08:00
|
|
|
struct drm_i915_gem_object *obj;
|
2013-08-01 08:00:15 +08:00
|
|
|
struct i915_vma *vma;
|
2013-07-12 21:50:57 +08:00
|
|
|
int i;
|
|
|
|
|
|
|
|
i = 0;
|
2016-02-26 19:03:19 +08:00
|
|
|
list_for_each_entry(vma, &vm->active_list, vm_link)
|
2013-07-12 21:50:57 +08:00
|
|
|
i++;
|
2013-08-01 08:00:15 +08:00
|
|
|
error->active_bo_count[ndx] = i;
|
2014-08-13 03:05:47 +08:00
|
|
|
|
|
|
|
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
2016-02-26 19:03:19 +08:00
|
|
|
list_for_each_entry(vma, &obj->vma_list, obj_link)
|
2014-12-11 01:27:58 +08:00
|
|
|
if (vma->vm == vm && vma->pin_count > 0)
|
2014-08-13 03:05:47 +08:00
|
|
|
i++;
|
|
|
|
}
|
2013-08-01 08:00:15 +08:00
|
|
|
error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
if (i) {
|
2013-09-21 06:35:38 +08:00
|
|
|
active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
|
2013-08-01 08:00:15 +08:00
|
|
|
if (active_bo)
|
|
|
|
pinned_bo = active_bo + error->active_bo_count[ndx];
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
2013-08-01 08:00:15 +08:00
|
|
|
if (active_bo)
|
|
|
|
error->active_bo_count[ndx] =
|
|
|
|
capture_active_bo(active_bo,
|
|
|
|
error->active_bo_count[ndx],
|
2013-07-17 07:50:08 +08:00
|
|
|
&vm->active_list);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2013-08-01 08:00:15 +08:00
|
|
|
if (pinned_bo)
|
|
|
|
error->pinned_bo_count[ndx] =
|
|
|
|
capture_pinned_bo(pinned_bo,
|
|
|
|
error->pinned_bo_count[ndx],
|
2014-08-13 03:05:47 +08:00
|
|
|
&dev_priv->mm.bound_list, vm);
|
2013-08-01 08:00:15 +08:00
|
|
|
error->active_bo[ndx] = active_bo;
|
|
|
|
error->pinned_bo[ndx] = pinned_bo;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_i915_error_state *error)
|
|
|
|
{
|
|
|
|
struct i915_address_space *vm;
|
|
|
|
int cnt = 0, i = 0;
|
|
|
|
|
|
|
|
list_for_each_entry(vm, &dev_priv->vm_list, global_link)
|
|
|
|
cnt++;
|
|
|
|
|
|
|
|
error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
|
|
|
|
error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
|
|
|
|
error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
|
|
|
|
GFP_ATOMIC);
|
|
|
|
error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
|
|
|
|
GFP_ATOMIC);
|
|
|
|
|
2014-08-13 03:05:47 +08:00
|
|
|
if (error->active_bo == NULL ||
|
|
|
|
error->pinned_bo == NULL ||
|
|
|
|
error->active_bo_count == NULL ||
|
|
|
|
error->pinned_bo_count == NULL) {
|
|
|
|
kfree(error->active_bo);
|
|
|
|
kfree(error->active_bo_count);
|
|
|
|
kfree(error->pinned_bo);
|
|
|
|
kfree(error->pinned_bo_count);
|
|
|
|
|
|
|
|
error->active_bo = NULL;
|
|
|
|
error->active_bo_count = NULL;
|
|
|
|
error->pinned_bo = NULL;
|
|
|
|
error->pinned_bo_count = NULL;
|
|
|
|
} else {
|
|
|
|
list_for_each_entry(vm, &dev_priv->vm_list, global_link)
|
|
|
|
i915_gem_capture_vm(dev_priv, error, vm, i++);
|
|
|
|
|
|
|
|
error->vm_count = cnt;
|
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
2014-01-30 16:19:35 +08:00
|
|
|
/* Capture all registers which don't fit into another category. */
|
|
|
|
static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_i915_error_state *error)
|
2013-07-12 21:50:57 +08:00
|
|
|
{
|
2014-01-30 16:19:35 +08:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2014-08-06 01:07:13 +08:00
|
|
|
int i;
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-01-30 16:19:36 +08:00
|
|
|
/* General organization
|
|
|
|
* 1. Registers specific to a single generation
|
|
|
|
* 2. Registers which belong to multiple generations
|
|
|
|
* 3. Feature specific registers.
|
|
|
|
* 4. Everything else
|
|
|
|
* Please try to follow the order.
|
|
|
|
*/
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-01-30 16:19:36 +08:00
|
|
|
/* 1: Registers specific to a single generation */
|
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
2014-08-06 01:07:13 +08:00
|
|
|
error->gtier[0] = I915_READ(GTIER);
|
2014-08-02 00:12:27 +08:00
|
|
|
error->ier = I915_READ(VLV_IER);
|
2015-10-22 20:34:57 +08:00
|
|
|
error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
|
2014-01-30 16:19:36 +08:00
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-01-30 16:19:36 +08:00
|
|
|
if (IS_GEN7(dev))
|
|
|
|
error->err_int = I915_READ(GEN7_ERR_INT);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2015-03-24 20:54:19 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
|
|
|
error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
|
|
|
|
error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
|
|
|
|
}
|
|
|
|
|
2014-01-30 16:19:39 +08:00
|
|
|
if (IS_GEN6(dev)) {
|
2015-10-22 20:34:57 +08:00
|
|
|
error->forcewake = I915_READ_FW(FORCEWAKE);
|
2014-01-30 16:19:39 +08:00
|
|
|
error->gab_ctl = I915_READ(GAB_CTL);
|
|
|
|
error->gfx_mode = I915_READ(GFX_MODE);
|
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
|
2014-01-30 16:19:36 +08:00
|
|
|
/* 2: Registers which belong to multiple generations */
|
|
|
|
if (INTEL_INFO(dev)->gen >= 7)
|
2015-10-22 20:34:57 +08:00
|
|
|
error->forcewake = I915_READ_FW(FORCEWAKE_MT);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
2014-01-30 16:19:36 +08:00
|
|
|
error->derrmr = I915_READ(DERRMR);
|
2013-07-12 21:50:57 +08:00
|
|
|
error->error = I915_READ(ERROR_GEN6);
|
|
|
|
error->done_reg = I915_READ(DONE_REG);
|
|
|
|
}
|
|
|
|
|
2014-01-30 16:19:36 +08:00
|
|
|
/* 3: Feature specific registers */
|
2014-01-30 16:19:39 +08:00
|
|
|
if (IS_GEN6(dev) || IS_GEN7(dev)) {
|
|
|
|
error->gam_ecochk = I915_READ(GAM_ECOCHK);
|
|
|
|
error->gac_eco = I915_READ(GAC_ECO_BITS);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 4: Everything else */
|
2014-01-30 16:19:36 +08:00
|
|
|
if (HAS_HW_CONTEXTS(dev))
|
|
|
|
error->ccid = I915_READ(CCID);
|
|
|
|
|
2014-08-06 01:07:13 +08:00
|
|
|
if (INTEL_INFO(dev)->gen >= 8) {
|
|
|
|
error->ier = I915_READ(GEN8_DE_MISC_IER);
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
error->gtier[i] = I915_READ(GEN8_GT_IER(i));
|
|
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
2014-08-02 00:12:27 +08:00
|
|
|
error->ier = I915_READ(DEIER);
|
2014-08-06 01:07:13 +08:00
|
|
|
error->gtier[0] = I915_READ(GTIER);
|
2014-08-02 00:12:27 +08:00
|
|
|
} else if (IS_GEN2(dev)) {
|
|
|
|
error->ier = I915_READ16(IER);
|
|
|
|
} else if (!IS_VALLEYVIEW(dev)) {
|
|
|
|
error->ier = I915_READ(IER);
|
2014-01-30 16:19:36 +08:00
|
|
|
}
|
|
|
|
error->eir = I915_READ(EIR);
|
|
|
|
error->pgtbl_er = I915_READ(PGTBL_ER);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
i915_get_extra_instdone(dev, error->extra_instdone);
|
2014-01-30 16:19:35 +08:00
|
|
|
}
|
|
|
|
|
2014-02-25 23:11:25 +08:00
|
|
|
static void i915_error_capture_msg(struct drm_device *dev,
|
2014-02-25 23:11:26 +08:00
|
|
|
struct drm_i915_error_state *error,
|
2016-03-19 04:07:55 +08:00
|
|
|
u32 engine_mask,
|
2014-02-25 23:11:26 +08:00
|
|
|
const char *error_msg)
|
2014-02-25 23:11:25 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 ecode;
|
2014-02-25 23:11:26 +08:00
|
|
|
int ring_id = -1, len;
|
2014-02-25 23:11:25 +08:00
|
|
|
|
|
|
|
ecode = i915_error_generate_code(dev_priv, error, &ring_id);
|
|
|
|
|
2014-02-25 23:11:26 +08:00
|
|
|
len = scnprintf(error->error_msg, sizeof(error->error_msg),
|
2014-11-06 19:03:46 +08:00
|
|
|
"GPU HANG: ecode %d:%d:0x%08x",
|
|
|
|
INTEL_INFO(dev)->gen, ring_id, ecode);
|
2014-02-25 23:11:26 +08:00
|
|
|
|
|
|
|
if (ring_id != -1 && error->ring[ring_id].pid != -1)
|
|
|
|
len += scnprintf(error->error_msg + len,
|
|
|
|
sizeof(error->error_msg) - len,
|
|
|
|
", in %s [%d]",
|
|
|
|
error->ring[ring_id].comm,
|
|
|
|
error->ring[ring_id].pid);
|
|
|
|
|
|
|
|
scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
|
|
|
|
", reason: %s, action: %s",
|
|
|
|
error_msg,
|
2016-03-19 04:07:55 +08:00
|
|
|
engine_mask ? "reset" : "continue");
|
2014-02-25 23:11:25 +08:00
|
|
|
}
|
|
|
|
|
2014-02-25 23:11:27 +08:00
|
|
|
static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_i915_error_state *error)
|
|
|
|
{
|
2015-08-08 03:24:15 +08:00
|
|
|
error->iommu = -1;
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
|
|
error->iommu = intel_iommu_gfx_mapped;
|
|
|
|
#endif
|
2014-02-25 23:11:27 +08:00
|
|
|
error->reset_count = i915_reset_count(&dev_priv->gpu_error);
|
2014-02-25 23:11:28 +08:00
|
|
|
error->suspend_count = dev_priv->suspend_count;
|
2014-02-25 23:11:27 +08:00
|
|
|
}
|
|
|
|
|
2014-01-30 16:19:35 +08:00
|
|
|
/**
|
|
|
|
* i915_capture_error_state - capture an error record for later analysis
|
|
|
|
* @dev: drm device
|
|
|
|
*
|
|
|
|
* Should be called when an error is detected (either a hang or an error
|
|
|
|
* interrupt) to capture error state from the time of the error. Fills
|
|
|
|
* out a structure which becomes available in debugfs for user level tools
|
|
|
|
* to pick up.
|
|
|
|
*/
|
2016-03-19 04:07:55 +08:00
|
|
|
void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
|
2014-02-25 23:11:26 +08:00
|
|
|
const char *error_msg)
|
2014-01-30 16:19:35 +08:00
|
|
|
{
|
2014-01-30 22:38:15 +08:00
|
|
|
static bool warned;
|
2014-01-30 16:19:35 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_error_state *error;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
/* Account for pipe specific data like PIPE*STAT */
|
|
|
|
error = kzalloc(sizeof(*error), GFP_ATOMIC);
|
|
|
|
if (!error) {
|
|
|
|
DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-02-04 20:18:55 +08:00
|
|
|
kref_init(&error->ref);
|
|
|
|
|
2014-02-25 23:11:27 +08:00
|
|
|
i915_capture_gen_state(dev_priv, error);
|
2014-02-04 20:18:55 +08:00
|
|
|
i915_capture_reg_state(dev_priv, error);
|
|
|
|
i915_gem_capture_buffers(dev_priv, error);
|
|
|
|
i915_gem_record_fences(dev, error);
|
|
|
|
i915_gem_record_rings(dev, error);
|
2014-01-30 16:19:35 +08:00
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
do_gettimeofday(&error->time);
|
|
|
|
|
|
|
|
error->overlay = intel_overlay_capture_error_state(dev);
|
|
|
|
error->display = intel_display_capture_error_state(dev);
|
|
|
|
|
2016-03-19 04:07:55 +08:00
|
|
|
i915_error_capture_msg(dev, error, engine_mask, error_msg);
|
2014-02-25 23:11:25 +08:00
|
|
|
DRM_INFO("%s\n", error->error_msg);
|
|
|
|
|
2013-07-12 21:50:57 +08:00
|
|
|
spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
|
|
|
|
if (dev_priv->gpu_error.first_error == NULL) {
|
|
|
|
dev_priv->gpu_error.first_error = error;
|
|
|
|
error = NULL;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
|
|
|
|
|
2014-02-25 23:11:25 +08:00
|
|
|
if (error) {
|
2013-07-12 21:50:57 +08:00
|
|
|
i915_error_state_free(&error->ref);
|
2014-02-25 23:11:25 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!warned) {
|
|
|
|
DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
|
|
|
|
DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
|
|
|
|
DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
|
|
|
|
DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
|
|
|
|
DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index);
|
|
|
|
warned = true;
|
|
|
|
}
|
2013-07-12 21:50:57 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void i915_error_state_get(struct drm_device *dev,
|
|
|
|
struct i915_error_state_file_priv *error_priv)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-09-15 20:55:24 +08:00
|
|
|
spin_lock_irq(&dev_priv->gpu_error.lock);
|
2013-07-12 21:50:57 +08:00
|
|
|
error_priv->error = dev_priv->gpu_error.first_error;
|
|
|
|
if (error_priv->error)
|
|
|
|
kref_get(&error_priv->error->ref);
|
2014-09-15 20:55:24 +08:00
|
|
|
spin_unlock_irq(&dev_priv->gpu_error.lock);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
|
|
|
|
{
|
|
|
|
if (error_priv->error)
|
|
|
|
kref_put(&error_priv->error->ref, i915_error_state_free);
|
|
|
|
}
|
|
|
|
|
|
|
|
void i915_destroy_error_state(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_i915_error_state *error;
|
|
|
|
|
2014-09-15 20:55:24 +08:00
|
|
|
spin_lock_irq(&dev_priv->gpu_error.lock);
|
2013-07-12 21:50:57 +08:00
|
|
|
error = dev_priv->gpu_error.first_error;
|
|
|
|
dev_priv->gpu_error.first_error = NULL;
|
2014-09-15 20:55:24 +08:00
|
|
|
spin_unlock_irq(&dev_priv->gpu_error.lock);
|
2013-07-12 21:50:57 +08:00
|
|
|
|
|
|
|
if (error)
|
|
|
|
kref_put(&error->ref, i915_error_state_free);
|
|
|
|
}
|
|
|
|
|
2014-08-22 21:41:39 +08:00
|
|
|
const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
|
2013-07-12 21:50:57 +08:00
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case I915_CACHE_NONE: return " uncached";
|
2014-08-22 21:41:39 +08:00
|
|
|
case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
|
2013-08-06 20:17:02 +08:00
|
|
|
case I915_CACHE_L3_LLC: return " L3+LLC";
|
2013-09-25 17:23:19 +08:00
|
|
|
case I915_CACHE_WT: return " WT";
|
2013-07-12 21:50:57 +08:00
|
|
|
default: return "";
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* NB: please notice the memset */
|
|
|
|
void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
|
|
|
|
|
2014-12-03 20:55:28 +08:00
|
|
|
if (IS_GEN2(dev) || IS_GEN3(dev))
|
2015-10-01 04:00:43 +08:00
|
|
|
instdone[0] = I915_READ(GEN2_INSTDONE);
|
2014-12-03 20:55:28 +08:00
|
|
|
else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
|
2015-10-01 04:00:42 +08:00
|
|
|
instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
|
2015-10-01 04:00:44 +08:00
|
|
|
instdone[1] = I915_READ(GEN4_INSTDONE1);
|
2014-12-03 20:55:28 +08:00
|
|
|
} else if (INTEL_INFO(dev)->gen >= 7) {
|
2015-10-01 04:00:42 +08:00
|
|
|
instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
|
2013-07-12 21:50:57 +08:00
|
|
|
instdone[1] = I915_READ(GEN7_SC_INSTDONE);
|
|
|
|
instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
|
|
|
|
instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
|
|
|
|
}
|
|
|
|
}
|