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79 lines
2.6 KiB
Plaintext
79 lines
2.6 KiB
Plaintext
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Broadcom AVS mail box and interrupt register bindings
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=====================================================
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A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
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references the mailbox register used to communicate with the AVS CPU[1]. The
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second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
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the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
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command sent to it by a driver. Interrupting the AVS CPU is mandatory for
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commands to be processed.
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The interface also requires a reference to the AVS host interrupt controller,
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so a driver can react to interrupts generated by the AVS CPU whenever a command
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has been processed. See [2] for more information on the brcm,l2-intc node.
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[1] The AVS CPU is an independent co-processor that runs proprietary
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firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
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Adaptive Voltage Scaling.
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[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
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Node brcm,avs-cpu-data-mem
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--------------------------
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Required properties:
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- compatible: must include: brcm,avs-cpu-data-mem and
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should include: one of brcm,bcm7271-avs-cpu-data-mem or
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brcm,bcm7268-avs-cpu-data-mem
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- reg: Specifies base physical address and size of the registers.
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- interrupts: The interrupt that the AVS CPU will use to interrupt the host
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when a command completed.
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- interrupt-parent: The interrupt controller the above interrupt is routed
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through.
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- interrupt-names: The name of the interrupt used to interrupt the host.
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Optional properties:
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- None
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Node brcm,avs-cpu-l2-intr
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-------------------------
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Required properties:
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- compatible: must include: brcm,avs-cpu-l2-intr and
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should include: one of brcm,bcm7271-avs-cpu-l2-intr or
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brcm,bcm7268-avs-cpu-l2-intr
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- reg: Specifies base physical address and size of the registers.
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Optional properties:
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- None
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Example
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=======
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avs_host_l2_intc: interrupt-controller@f04d1200 {
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#interrupt-cells = <1>;
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compatible = "brcm,l2-intc";
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interrupt-parent = <&intc>;
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reg = <0xf04d1200 0x48>;
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interrupt-controller;
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interrupts = <0x0 0x19 0x0>;
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interrupt-names = "avs";
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};
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avs-cpu-data-mem@f04c4000 {
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compatible = "brcm,bcm7271-avs-cpu-data-mem",
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"brcm,avs-cpu-data-mem";
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reg = <0xf04c4000 0x60>;
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interrupts = <0x1a>;
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interrupt-parent = <&avs_host_l2_intc>;
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interrupt-names = "sw_intr";
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};
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avs-cpu-l2-intr@f04d1100 {
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compatible = "brcm,bcm7271-avs-cpu-l2-intr",
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"brcm,avs-cpu-l2-intr";
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reg = <0xf04d1100 0x10>;
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};
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