2008-08-19 16:08:40 +08:00
|
|
|
/*
|
2010-12-22 12:05:14 +08:00
|
|
|
* OMAP2/3/4 powerdomain control
|
2008-08-19 16:08:40 +08:00
|
|
|
*
|
2010-12-22 12:05:16 +08:00
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|
* Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
|
2011-03-08 10:28:15 +08:00
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|
* Copyright (C) 2007-2011 Nokia Corporation
|
2008-08-19 16:08:40 +08:00
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*
|
2010-12-22 12:05:16 +08:00
|
|
|
* Paul Walmsley
|
2008-08-19 16:08:40 +08:00
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|
*
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|
* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
|
2010-12-22 11:01:20 +08:00
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|
*
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|
* XXX This should be moved to the mach-omap2/ directory at the earliest
|
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|
* opportunity.
|
2008-08-19 16:08:40 +08:00
|
|
|
*/
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|
2010-12-22 12:05:16 +08:00
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|
#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
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#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
|
2008-08-19 16:08:40 +08:00
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#include <linux/types.h>
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#include <linux/list.h>
|
2013-01-26 15:58:16 +08:00
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|
#include <linux/spinlock.h>
|
2008-08-19 16:08:40 +08:00
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/* Powerdomain basic power states */
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#define PWRDM_POWER_OFF 0x0
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#define PWRDM_POWER_RET 0x1
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#define PWRDM_POWER_INACTIVE 0x2
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#define PWRDM_POWER_ON 0x3
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|
2009-12-09 07:33:12 +08:00
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#define PWRDM_MAX_PWRSTS 4
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2008-08-19 16:08:40 +08:00
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/* Powerdomain allowable state bitfields */
|
2010-05-19 10:24:01 +08:00
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#define PWRSTS_ON (1 << PWRDM_POWER_ON)
|
2011-03-08 10:28:15 +08:00
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#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
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#define PWRSTS_RET (1 << PWRDM_POWER_RET)
|
2010-09-28 04:02:56 +08:00
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#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
|
2008-08-19 16:08:40 +08:00
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|
2011-03-08 10:28:15 +08:00
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#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
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#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
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#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
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#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
|
2014-06-06 14:21:51 +08:00
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#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
|
2008-08-19 16:08:40 +08:00
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2013-01-26 15:58:17 +08:00
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/*
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* Powerdomain flags (struct powerdomain.flags)
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*
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* PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
|
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*
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* PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
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* bank 1 position. This is true for OMAP3430
|
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*
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* PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
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* to a lower sleep state without waking up the powerdomain
|
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*/
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#define PWRDM_HAS_HDWR_SAR BIT(0)
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#define PWRDM_HAS_MPU_QUIRK BIT(1)
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#define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2)
|
[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 08:09:37 +08:00
|
|
|
|
2008-08-19 16:08:40 +08:00
|
|
|
/*
|
2010-01-27 11:12:52 +08:00
|
|
|
* Number of memory banks that are power-controllable. On OMAP4430, the
|
|
|
|
* maximum is 5.
|
2008-08-19 16:08:40 +08:00
|
|
|
*/
|
2010-01-27 11:12:52 +08:00
|
|
|
#define PWRDM_MAX_MEM_BANKS 5
|
2008-08-19 16:08:40 +08:00
|
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|
2008-08-19 16:08:44 +08:00
|
|
|
/*
|
|
|
|
* Maximum number of clockdomains that can be associated with a powerdomain.
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 14:47:27 +08:00
|
|
|
* PER powerdomain on AM33XX is the worst case
|
2008-08-19 16:08:44 +08:00
|
|
|
*/
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 14:47:27 +08:00
|
|
|
#define PWRDM_MAX_CLKDMS 11
|
2008-08-19 16:08:44 +08:00
|
|
|
|
2008-08-19 16:08:40 +08:00
|
|
|
/* XXX A completely arbitrary number. What is reasonable here? */
|
|
|
|
#define PWRDM_TRANSITION_BAILOUT 100000
|
|
|
|
|
2008-08-19 16:08:44 +08:00
|
|
|
struct clockdomain;
|
2008-08-19 16:08:40 +08:00
|
|
|
struct powerdomain;
|
2014-05-12 09:41:50 +08:00
|
|
|
struct voltagedomain;
|
2008-08-19 16:08:40 +08:00
|
|
|
|
2010-01-27 11:13:02 +08:00
|
|
|
/**
|
|
|
|
* struct powerdomain - OMAP powerdomain
|
|
|
|
* @name: Powerdomain name
|
2011-03-23 22:22:23 +08:00
|
|
|
* @voltdm: voltagedomain containing this powerdomain
|
2010-01-27 11:13:02 +08:00
|
|
|
* @prcm_offs: the address offset from CM_BASE/PRM_BASE
|
2010-12-22 12:05:14 +08:00
|
|
|
* @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
|
2010-01-27 11:13:02 +08:00
|
|
|
* @pwrsts: Possible powerdomain power states
|
|
|
|
* @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
|
|
|
|
* @flags: Powerdomain flags
|
|
|
|
* @banks: Number of software-controllable memory banks in this powerdomain
|
|
|
|
* @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
|
|
|
|
* @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
|
|
|
|
* @pwrdm_clkdms: Clockdomains in this powerdomain
|
|
|
|
* @node: list_head linking all powerdomains
|
2011-03-17 07:13:15 +08:00
|
|
|
* @voltdm_node: list_head linking all powerdomains in a voltagedomain
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 14:47:27 +08:00
|
|
|
* @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
|
|
|
|
* @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
|
|
|
|
* @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
|
|
|
|
* in @pwrstctrl_offs
|
|
|
|
* @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
|
|
|
|
* @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
|
|
|
|
* @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
|
|
|
|
* @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
|
|
|
|
* in @pwrstctrl_offs
|
2010-01-27 11:13:02 +08:00
|
|
|
* @state:
|
|
|
|
* @state_counter:
|
|
|
|
* @timer:
|
|
|
|
* @state_timer:
|
2013-01-26 15:58:16 +08:00
|
|
|
* @_lock: spinlock used to serialize powerdomain and some clockdomain ops
|
|
|
|
* @_lock_flags: stored flags when @_lock is taken
|
2010-12-22 12:05:14 +08:00
|
|
|
*
|
|
|
|
* @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
|
2010-01-27 11:13:02 +08:00
|
|
|
*/
|
2008-08-19 16:08:40 +08:00
|
|
|
struct powerdomain {
|
|
|
|
const char *name;
|
2011-03-23 22:22:23 +08:00
|
|
|
union {
|
|
|
|
const char *name;
|
|
|
|
struct voltagedomain *ptr;
|
|
|
|
} voltdm;
|
2010-01-27 11:13:01 +08:00
|
|
|
const s16 prcm_offs;
|
2008-08-19 16:08:40 +08:00
|
|
|
const u8 pwrsts;
|
|
|
|
const u8 pwrsts_logic_ret;
|
[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 08:09:37 +08:00
|
|
|
const u8 flags;
|
2008-08-19 16:08:40 +08:00
|
|
|
const u8 banks;
|
|
|
|
const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
|
|
|
|
const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
|
2010-12-22 12:05:14 +08:00
|
|
|
const u8 prcm_partition;
|
2008-08-19 16:08:44 +08:00
|
|
|
struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
|
2008-08-19 16:08:40 +08:00
|
|
|
struct list_head node;
|
2011-03-17 07:13:15 +08:00
|
|
|
struct list_head voltdm_node;
|
2008-10-15 22:48:43 +08:00
|
|
|
int state;
|
2009-12-09 07:33:12 +08:00
|
|
|
unsigned state_counter[PWRDM_MAX_PWRSTS];
|
2010-02-25 03:05:50 +08:00
|
|
|
unsigned ret_logic_off_counter;
|
|
|
|
unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
|
2013-01-26 15:58:16 +08:00
|
|
|
spinlock_t _lock;
|
|
|
|
unsigned long _lock_flags;
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 14:47:27 +08:00
|
|
|
const u8 pwrstctrl_offs;
|
|
|
|
const u8 pwrstst_offs;
|
|
|
|
const u32 logicretstate_mask;
|
|
|
|
const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
|
|
|
|
const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
|
|
|
|
const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
|
|
|
|
const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
|
|
|
|
|
2008-10-15 23:13:48 +08:00
|
|
|
#ifdef CONFIG_PM_DEBUG
|
|
|
|
s64 timer;
|
2009-12-09 07:33:12 +08:00
|
|
|
s64 state_timer[PWRDM_MAX_PWRSTS];
|
2008-10-15 23:13:48 +08:00
|
|
|
#endif
|
2018-05-16 23:17:00 +08:00
|
|
|
u32 context;
|
2008-08-19 16:08:40 +08:00
|
|
|
};
|
|
|
|
|
2010-12-22 11:01:18 +08:00
|
|
|
/**
|
2011-03-31 09:57:33 +08:00
|
|
|
* struct pwrdm_ops - Arch specific function implementations
|
2010-12-22 11:01:18 +08:00
|
|
|
* @pwrdm_set_next_pwrst: Set the target power state for a pd
|
|
|
|
* @pwrdm_read_next_pwrst: Read the target power state set for a pd
|
|
|
|
* @pwrdm_read_pwrst: Read the current power state of a pd
|
|
|
|
* @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
|
|
|
|
* @pwrdm_set_logic_retst: Set the logic state in RET for a pd
|
|
|
|
* @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
|
|
|
|
* @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
|
|
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* @pwrdm_read_logic_pwrst: Read the current logic state of a pd
|
|
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* @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
|
|
|
|
* @pwrdm_read_logic_retst: Read the logic state in RET for a pd
|
|
|
|
* @pwrdm_read_mem_pwrst: Read the current memory state of a pd
|
|
|
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* @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
|
|
|
|
* @pwrdm_read_mem_retst: Read the memory state in RET for a pd
|
|
|
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* @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
|
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* @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
|
|
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* @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
|
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* @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
|
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* @pwrdm_wait_transition: Wait for a pd state transition to complete
|
2013-06-17 21:16:22 +08:00
|
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* @pwrdm_has_voltdm: Check if a voltdm association is needed
|
2013-01-30 04:45:09 +08:00
|
|
|
*
|
|
|
|
* Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
|
|
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|
* chips, a powerdomain's power state is not allowed to directly
|
|
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|
* transition from one low-power state (e.g., CSWR) to another
|
|
|
|
* low-power state (e.g., OFF) without first waking up the
|
|
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|
* powerdomain. This wastes energy. So OMAP4 chips support the
|
|
|
|
* ability to transition a powerdomain power state directly from one
|
|
|
|
* low-power state to another. The function pointed to by
|
|
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* @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
|
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* hardware powerdomain state machine to enable this feature.
|
2010-12-22 11:01:18 +08:00
|
|
|
*/
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struct pwrdm_ops {
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int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
|
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int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
|
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int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
|
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int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
|
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int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
|
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int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
|
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int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
|
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|
|
int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
|
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int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
|
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int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
|
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int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
|
|
|
|
int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
|
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|
|
int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
|
|
|
|
int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
|
|
|
|
int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
|
|
|
|
int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
|
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|
|
int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
|
|
|
|
int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
|
2013-06-17 21:16:22 +08:00
|
|
|
int (*pwrdm_has_voltdm)(void);
|
2018-05-16 23:17:00 +08:00
|
|
|
void (*pwrdm_save_context)(struct powerdomain *pwrdm);
|
|
|
|
void (*pwrdm_restore_context)(struct powerdomain *pwrdm);
|
2010-12-22 11:01:18 +08:00
|
|
|
};
|
2008-08-19 16:08:40 +08:00
|
|
|
|
2011-09-15 06:01:21 +08:00
|
|
|
int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
|
|
|
|
int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
|
|
|
|
int pwrdm_complete_init(void);
|
2008-08-19 16:08:40 +08:00
|
|
|
|
|
|
|
struct powerdomain *pwrdm_lookup(const char *name);
|
|
|
|
|
2008-10-15 23:13:47 +08:00
|
|
|
int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
|
|
|
|
void *user);
|
2009-10-01 15:01:55 +08:00
|
|
|
int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
|
|
|
|
void *user);
|
2008-08-19 16:08:40 +08:00
|
|
|
|
2008-08-19 16:08:44 +08:00
|
|
|
int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
|
|
|
|
|
2008-08-19 16:08:40 +08:00
|
|
|
int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
|
|
|
|
|
2014-06-06 14:04:20 +08:00
|
|
|
u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
|
|
|
|
bool is_logic_state, u8 req_state);
|
|
|
|
|
2008-08-19 16:08:40 +08:00
|
|
|
int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
|
|
|
|
int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
|
2009-01-28 10:12:50 +08:00
|
|
|
int pwrdm_read_pwrst(struct powerdomain *pwrdm);
|
2008-08-19 16:08:40 +08:00
|
|
|
int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
|
|
|
|
int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
|
|
|
|
|
|
|
|
int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
|
|
|
|
int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
|
|
|
|
int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
|
|
|
|
|
|
|
|
int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
|
|
|
|
int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
|
2010-02-25 03:05:49 +08:00
|
|
|
int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
|
2008-08-19 16:08:40 +08:00
|
|
|
int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
|
|
|
|
int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
|
2010-02-25 03:05:49 +08:00
|
|
|
int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
|
2008-08-19 16:08:40 +08:00
|
|
|
|
[ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) support
OMAP3430ES2+ introduces a new feature: optional powerdomain context
hardware save-and-restore (SAR). Currently, this feature only applies
to USBHOST and USBTLL module context when the USBHOST or CORE
powerdomains enter a low-power sleep state[1]. This feature avoids
re-enumeration of USB devices when the powerdomains return from idle,
which is potentially time-consuming.
This patch adds support for enabling and disabling hardware
save-and-restore to the powerdomain code. Three new functions are
added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and
pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is
added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with
SAR support.
Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an
earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com>
for clarifying the purpose of these bits.
1. For the USBHOST controller module, context loss occurs when the
USBHOST powerdomain enters off-idle. For USBTLL, context loss
occurs either if CORE enters off-idle, or if the CORE logic is
configured to turn off when CORE enters retention-idle (OSWR).
34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-06-26 08:09:37 +08:00
|
|
|
int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
|
|
|
|
int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
|
|
|
|
bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
|
|
|
|
|
2013-01-26 15:58:16 +08:00
|
|
|
int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
|
2008-10-15 22:48:43 +08:00
|
|
|
int pwrdm_state_switch(struct powerdomain *pwrdm);
|
2012-05-12 07:00:24 +08:00
|
|
|
int pwrdm_pre_transition(struct powerdomain *pwrdm);
|
|
|
|
int pwrdm_post_transition(struct powerdomain *pwrdm);
|
2011-06-09 21:56:23 +08:00
|
|
|
int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
|
2011-03-08 10:28:15 +08:00
|
|
|
bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
|
2008-10-15 22:48:43 +08:00
|
|
|
|
2013-01-30 04:45:09 +08:00
|
|
|
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
|
|
|
|
|
2011-09-15 01:34:21 +08:00
|
|
|
extern void omap242x_powerdomains_init(void);
|
|
|
|
extern void omap243x_powerdomains_init(void);
|
2010-12-22 11:01:20 +08:00
|
|
|
extern void omap3xxx_powerdomains_init(void);
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 14:47:27 +08:00
|
|
|
extern void am33xx_powerdomains_init(void);
|
2010-12-22 11:01:20 +08:00
|
|
|
extern void omap44xx_powerdomains_init(void);
|
2013-05-30 00:38:09 +08:00
|
|
|
extern void omap54xx_powerdomains_init(void);
|
2013-07-09 15:32:13 +08:00
|
|
|
extern void dra7xx_powerdomains_init(void);
|
2013-10-12 18:15:54 +08:00
|
|
|
void am43xx_powerdomains_init(void);
|
2010-12-22 11:01:20 +08:00
|
|
|
|
2010-12-22 12:05:16 +08:00
|
|
|
extern struct pwrdm_ops omap2_pwrdm_operations;
|
|
|
|
extern struct pwrdm_ops omap3_pwrdm_operations;
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 14:47:27 +08:00
|
|
|
extern struct pwrdm_ops am33xx_pwrdm_operations;
|
2010-12-22 12:05:16 +08:00
|
|
|
extern struct pwrdm_ops omap4_pwrdm_operations;
|
|
|
|
|
|
|
|
/* Common Internal functions used across OMAP rev's */
|
|
|
|
extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
|
|
|
|
extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
|
|
|
|
extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
|
|
|
|
|
|
|
|
extern struct powerdomain wkup_omap2_pwrdm;
|
|
|
|
extern struct powerdomain gfx_omap2_pwrdm;
|
|
|
|
|
2013-01-26 15:58:16 +08:00
|
|
|
extern void pwrdm_lock(struct powerdomain *pwrdm);
|
|
|
|
extern void pwrdm_unlock(struct powerdomain *pwrdm);
|
2010-12-22 12:05:16 +08:00
|
|
|
|
2018-05-16 23:17:00 +08:00
|
|
|
extern void pwrdms_save_context(void);
|
|
|
|
extern void pwrdms_restore_context(void);
|
|
|
|
|
|
|
|
extern void pwrdms_lost_power(void);
|
2008-08-19 16:08:40 +08:00
|
|
|
#endif
|