mirror of https://gitee.com/openkylin/linux.git
103 lines
4.6 KiB
C
103 lines
4.6 KiB
C
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/*
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* STMP APBH Register Definitions
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*
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* Copyright (c) 2008 Freescale Semiconductor
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H
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#define _INCLUDE_ASM_ARCH_REGS_APBH_H
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#include <mach/stmp3xxx_regs.h>
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#ifndef REGS_APBH_BASE
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#define REGS_APBH_BASE (REGS_BASE + 0x00004000)
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#endif
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HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00)
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#define BP_APBH_CTRL0_SFTRST 31
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#define BM_APBH_CTRL0_SFTRST 0x80000000
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#define BP_APBH_CTRL0_CLKGATE 30
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#define BM_APBH_CTRL0_CLKGATE 0x40000000
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#define BP_APBH_CTRL0_RESET_CHANNEL 16
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#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
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#define BF_APBH_CTRL0_RESET_CHANNEL(v) \
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(((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL)
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HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10)
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#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 9
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#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00000200
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#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 8
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#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00000100
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#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ 7
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#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080
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#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ 1
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#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002
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#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
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#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
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#define BP_APBH_CTRL1_CH1_ERR_IRQ 17
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#define BM_APBH_CTRL1_CH1_ERR_IRQ 0x00020000
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HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20)
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HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70)
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HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70)
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#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0
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#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
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#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) ((u32) v)
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HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70)
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#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
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#define BP_APBH_CHn_CMD_XFER_COUNT 16
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#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
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(((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT)
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#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
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#define BP_APBH_CHn_CMD_CMDWORDS 12
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#define BF_APBH_CHn_CMD_CMDWORDS(v) \
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(((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS)
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#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
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#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
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#define BP_APBH_CHn_CMD_SEMAPHORE 6
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#define BF_APBH_CHn_CMD_SEMAPHORE(v) \
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(((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE)
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#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
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#define BP_APBH_CHn_CMD_NANDLOCK 4
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#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
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#define BF_APBH_CHn_CMD_NANDLOCK(v) \
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(((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK)
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#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
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#define BM_APBH_CHn_CMD_CHAIN 0x00000004
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#define BM_APBH_CHn_CMD_DMA_READ 0x00000003
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#define BP_APBH_CHn_CMD_DMA_READ 0
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#define BF_APBH_CHn_CMD_DMA_READ(v) \
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(((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
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#define BF_APBH_CHn_CMD_COMMAND(v) \
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(((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)
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#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
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#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1
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#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2
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#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3
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HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70)
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HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70)
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#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
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#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
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#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \
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(((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \
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BM_APBH_CHn_SEMA_INCREMENT_SEMA)
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#define BP_APBH_CHn_SEMA_PHORE 16
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#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
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HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70)
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HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70)
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HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0)
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#endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */
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