2019-06-03 13:44:50 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-03-05 19:49:29 +08:00
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_FUTEX_H
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#define __ASM_FUTEX_H
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#include <linux/futex.h>
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#include <linux/uaccess.h>
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2015-07-23 02:05:54 +08:00
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2012-03-05 19:49:29 +08:00
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#include <asm/errno.h>
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2019-04-08 21:23:17 +08:00
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#define FUTEX_MAX_LOOPS 128 /* What's the largest number you can think of? */
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2012-03-05 19:49:29 +08:00
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#define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \
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2016-07-01 21:58:21 +08:00
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do { \
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2019-04-08 21:23:17 +08:00
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unsigned int loops = FUTEX_MAX_LOOPS; \
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\
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2016-07-01 21:58:21 +08:00
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uaccess_enable(); \
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2012-03-05 19:49:29 +08:00
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asm volatile( \
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2015-05-29 20:31:10 +08:00
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" prfm pstl1strm, %2\n" \
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arm64: atomics: fix use of acquire + release for full barrier semantics
Linux requires a number of atomic operations to provide full barrier
semantics, that is no memory accesses after the operation can be
observed before any accesses up to and including the operation in
program order.
On arm64, these operations have been incorrectly implemented as follows:
// A, B, C are independent memory locations
<Access [A]>
// atomic_op (B)
1: ldaxr x0, [B] // Exclusive load with acquire
<op(B)>
stlxr w1, x0, [B] // Exclusive store with release
cbnz w1, 1b
<Access [C]>
The assumption here being that two half barriers are equivalent to a
full barrier, so the only permitted ordering would be A -> B -> C
(where B is the atomic operation involving both a load and a store).
Unfortunately, this is not the case by the letter of the architecture
and, in fact, the accesses to A and C are permitted to pass their
nearest half barrier resulting in orderings such as Bl -> A -> C -> Bs
or Bl -> C -> A -> Bs (where Bl is the load-acquire on B and Bs is the
store-release on B). This is a clear violation of the full barrier
requirement.
The simple way to fix this is to implement the same algorithm as ARMv7
using explicit barriers:
<Access [A]>
// atomic_op (B)
dmb ish // Full barrier
1: ldxr x0, [B] // Exclusive load
<op(B)>
stxr w1, x0, [B] // Exclusive store
cbnz w1, 1b
dmb ish // Full barrier
<Access [C]>
but this has the undesirable effect of introducing *two* full barrier
instructions. A better approach is actually the following, non-intuitive
sequence:
<Access [A]>
// atomic_op (B)
1: ldxr x0, [B] // Exclusive load
<op(B)>
stlxr w1, x0, [B] // Exclusive store with release
cbnz w1, 1b
dmb ish // Full barrier
<Access [C]>
The simple observations here are:
- The dmb ensures that no subsequent accesses (e.g. the access to C)
can enter or pass the atomic sequence.
- The dmb also ensures that no prior accesses (e.g. the access to A)
can pass the atomic sequence.
- Therefore, no prior access can pass a subsequent access, or
vice-versa (i.e. A is strictly ordered before C).
- The stlxr ensures that no prior access can pass the store component
of the atomic operation.
The only tricky part remaining is the ordering between the ldxr and the
access to A, since the absence of the first dmb means that we're now
permitting re-ordering between the ldxr and any prior accesses.
From an (arbitrary) observer's point of view, there are two scenarios:
1. We have observed the ldxr. This means that if we perform a store to
[B], the ldxr will still return older data. If we can observe the
ldxr, then we can potentially observe the permitted re-ordering
with the access to A, which is clearly an issue when compared to
the dmb variant of the code. Thankfully, the exclusive monitor will
save us here since it will be cleared as a result of the store and
the ldxr will retry. Notice that any use of a later memory
observation to imply observation of the ldxr will also imply
observation of the access to A, since the stlxr/dmb ensure strict
ordering.
2. We have not observed the ldxr. This means we can perform a store
and influence the later ldxr. However, that doesn't actually tell
us anything about the access to [A], so we've not lost anything
here either when compared to the dmb variant.
This patch implements this solution for our barriered atomic operations,
ensuring that we satisfy the full barrier requirements where they are
needed.
Cc: <stable@vger.kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-02-04 20:29:12 +08:00
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"1: ldxr %w1, %2\n" \
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2012-03-05 19:49:29 +08:00
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insn "\n" \
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2019-04-08 19:45:09 +08:00
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"2: stlxr %w0, %w3, %2\n" \
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2019-04-08 21:23:17 +08:00
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" cbz %w0, 3f\n" \
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" sub %w4, %w4, %w0\n" \
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" cbnz %w4, 1b\n" \
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" mov %w0, %w7\n" \
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2012-03-05 19:49:29 +08:00
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"3:\n" \
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2019-04-08 21:23:17 +08:00
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" dmb ish\n" \
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2012-03-05 19:49:29 +08:00
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" .pushsection .fixup,\"ax\"\n" \
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2013-11-07 03:31:24 +08:00
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" .align 2\n" \
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2019-04-08 21:23:17 +08:00
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"4: mov %w0, %w6\n" \
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2012-03-05 19:49:29 +08:00
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" b 3b\n" \
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" .popsection\n" \
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2016-01-01 22:02:12 +08:00
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_ASM_EXTABLE(1b, 4b) \
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_ASM_EXTABLE(2b, 4b) \
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2019-04-08 21:23:17 +08:00
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: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp), \
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"+r" (loops) \
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: "r" (oparg), "Ir" (-EFAULT), "Ir" (-EAGAIN) \
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2016-07-01 21:58:21 +08:00
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: "memory"); \
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uaccess_disable(); \
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} while (0)
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2012-03-05 19:49:29 +08:00
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static inline int
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2018-02-05 23:34:24 +08:00
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arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr)
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2012-03-05 19:49:29 +08:00
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{
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2019-04-17 15:21:21 +08:00
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int oldval = 0, ret, tmp;
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2018-02-05 23:34:24 +08:00
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u32 __user *uaddr = __uaccess_mask_ptr(_uaddr);
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2012-03-05 19:49:29 +08:00
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2020-02-16 23:17:27 +08:00
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if (!access_ok(_uaddr, sizeof(u32)))
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return -EFAULT;
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2012-03-05 19:49:29 +08:00
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switch (op) {
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case FUTEX_OP_SET:
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2019-04-08 21:23:17 +08:00
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__futex_atomic_op("mov %w3, %w5",
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2012-03-05 19:49:29 +08:00
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ADD:
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2019-04-08 21:23:17 +08:00
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__futex_atomic_op("add %w3, %w1, %w5",
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2012-03-05 19:49:29 +08:00
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_OR:
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2019-04-08 21:23:17 +08:00
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__futex_atomic_op("orr %w3, %w1, %w5",
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2012-03-05 19:49:29 +08:00
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ret, oldval, uaddr, tmp, oparg);
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break;
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case FUTEX_OP_ANDN:
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2019-04-08 21:23:17 +08:00
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__futex_atomic_op("and %w3, %w1, %w5",
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2012-03-05 19:49:29 +08:00
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ret, oldval, uaddr, tmp, ~oparg);
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break;
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case FUTEX_OP_XOR:
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2019-04-08 21:23:17 +08:00
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__futex_atomic_op("eor %w3, %w1, %w5",
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2012-03-05 19:49:29 +08:00
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ret, oldval, uaddr, tmp, oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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2017-08-24 15:31:05 +08:00
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if (!ret)
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*oval = oldval;
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2012-03-05 19:49:29 +08:00
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return ret;
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}
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static inline int
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2018-02-05 23:34:24 +08:00
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr,
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2012-03-05 19:49:29 +08:00
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u32 oldval, u32 newval)
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{
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int ret = 0;
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2019-04-08 21:23:17 +08:00
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unsigned int loops = FUTEX_MAX_LOOPS;
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2012-03-05 19:49:29 +08:00
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u32 val, tmp;
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2018-02-05 23:34:24 +08:00
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u32 __user *uaddr;
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2012-03-05 19:49:29 +08:00
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Remove 'type' argument from access_ok() function
Nobody has actually used the type (VERIFY_READ vs VERIFY_WRITE) argument
of the user address range verification function since we got rid of the
old racy i386-only code to walk page tables by hand.
It existed because the original 80386 would not honor the write protect
bit when in kernel mode, so you had to do COW by hand before doing any
user access. But we haven't supported that in a long time, and these
days the 'type' argument is a purely historical artifact.
A discussion about extending 'user_access_begin()' to do the range
checking resulted this patch, because there is no way we're going to
move the old VERIFY_xyz interface to that model. And it's best done at
the end of the merge window when I've done most of my merges, so let's
just get this done once and for all.
This patch was mostly done with a sed-script, with manual fix-ups for
the cases that weren't of the trivial 'access_ok(VERIFY_xyz' form.
There were a couple of notable cases:
- csky still had the old "verify_area()" name as an alias.
- the iter_iov code had magical hardcoded knowledge of the actual
values of VERIFY_{READ,WRITE} (not that they mattered, since nothing
really used it)
- microblaze used the type argument for a debug printout
but other than those oddities this should be a total no-op patch.
I tried to fix up all architectures, did fairly extensive grepping for
access_ok() uses, and the changes are trivial, but I may have missed
something. Any missed conversion should be trivially fixable, though.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2019-01-04 10:57:57 +08:00
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if (!access_ok(_uaddr, sizeof(u32)))
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2012-03-05 19:49:29 +08:00
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return -EFAULT;
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2018-02-05 23:34:24 +08:00
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uaddr = __uaccess_mask_ptr(_uaddr);
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2016-07-01 21:58:21 +08:00
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uaccess_enable();
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2012-03-05 19:49:29 +08:00
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asm volatile("// futex_atomic_cmpxchg_inatomic\n"
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2015-05-29 20:31:10 +08:00
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" prfm pstl1strm, %2\n"
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arm64: atomics: fix use of acquire + release for full barrier semantics
Linux requires a number of atomic operations to provide full barrier
semantics, that is no memory accesses after the operation can be
observed before any accesses up to and including the operation in
program order.
On arm64, these operations have been incorrectly implemented as follows:
// A, B, C are independent memory locations
<Access [A]>
// atomic_op (B)
1: ldaxr x0, [B] // Exclusive load with acquire
<op(B)>
stlxr w1, x0, [B] // Exclusive store with release
cbnz w1, 1b
<Access [C]>
The assumption here being that two half barriers are equivalent to a
full barrier, so the only permitted ordering would be A -> B -> C
(where B is the atomic operation involving both a load and a store).
Unfortunately, this is not the case by the letter of the architecture
and, in fact, the accesses to A and C are permitted to pass their
nearest half barrier resulting in orderings such as Bl -> A -> C -> Bs
or Bl -> C -> A -> Bs (where Bl is the load-acquire on B and Bs is the
store-release on B). This is a clear violation of the full barrier
requirement.
The simple way to fix this is to implement the same algorithm as ARMv7
using explicit barriers:
<Access [A]>
// atomic_op (B)
dmb ish // Full barrier
1: ldxr x0, [B] // Exclusive load
<op(B)>
stxr w1, x0, [B] // Exclusive store
cbnz w1, 1b
dmb ish // Full barrier
<Access [C]>
but this has the undesirable effect of introducing *two* full barrier
instructions. A better approach is actually the following, non-intuitive
sequence:
<Access [A]>
// atomic_op (B)
1: ldxr x0, [B] // Exclusive load
<op(B)>
stlxr w1, x0, [B] // Exclusive store with release
cbnz w1, 1b
dmb ish // Full barrier
<Access [C]>
The simple observations here are:
- The dmb ensures that no subsequent accesses (e.g. the access to C)
can enter or pass the atomic sequence.
- The dmb also ensures that no prior accesses (e.g. the access to A)
can pass the atomic sequence.
- Therefore, no prior access can pass a subsequent access, or
vice-versa (i.e. A is strictly ordered before C).
- The stlxr ensures that no prior access can pass the store component
of the atomic operation.
The only tricky part remaining is the ordering between the ldxr and the
access to A, since the absence of the first dmb means that we're now
permitting re-ordering between the ldxr and any prior accesses.
From an (arbitrary) observer's point of view, there are two scenarios:
1. We have observed the ldxr. This means that if we perform a store to
[B], the ldxr will still return older data. If we can observe the
ldxr, then we can potentially observe the permitted re-ordering
with the access to A, which is clearly an issue when compared to
the dmb variant of the code. Thankfully, the exclusive monitor will
save us here since it will be cleared as a result of the store and
the ldxr will retry. Notice that any use of a later memory
observation to imply observation of the ldxr will also imply
observation of the access to A, since the stlxr/dmb ensure strict
ordering.
2. We have not observed the ldxr. This means we can perform a store
and influence the later ldxr. However, that doesn't actually tell
us anything about the access to [A], so we've not lost anything
here either when compared to the dmb variant.
This patch implements this solution for our barriered atomic operations,
ensuring that we satisfy the full barrier requirements where they are
needed.
Cc: <stable@vger.kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2014-02-04 20:29:12 +08:00
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"1: ldxr %w1, %2\n"
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2019-04-08 21:23:17 +08:00
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" sub %w3, %w1, %w5\n"
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" cbnz %w3, 4f\n"
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"2: stlxr %w3, %w6, %2\n"
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" cbz %w3, 3f\n"
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" sub %w4, %w4, %w3\n"
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" cbnz %w4, 1b\n"
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" mov %w0, %w8\n"
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2012-03-05 19:49:29 +08:00
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"3:\n"
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2019-04-08 21:23:17 +08:00
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" dmb ish\n"
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"4:\n"
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2012-03-05 19:49:29 +08:00
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" .pushsection .fixup,\"ax\"\n"
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2019-04-08 21:23:17 +08:00
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"5: mov %w0, %w7\n"
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" b 4b\n"
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2012-03-05 19:49:29 +08:00
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" .popsection\n"
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2019-04-08 21:23:17 +08:00
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_ASM_EXTABLE(1b, 5b)
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_ASM_EXTABLE(2b, 5b)
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: "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp), "+r" (loops)
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: "r" (oldval), "r" (newval), "Ir" (-EFAULT), "Ir" (-EAGAIN)
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2014-02-04 20:29:13 +08:00
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: "memory");
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2016-07-01 21:58:21 +08:00
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uaccess_disable();
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2012-03-05 19:49:29 +08:00
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2019-04-10 18:49:11 +08:00
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if (!ret)
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*uval = val;
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2012-03-05 19:49:29 +08:00
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return ret;
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}
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#endif /* __ASM_FUTEX_H */
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