mirror of https://gitee.com/openkylin/linux.git
601 lines
13 KiB
C
601 lines
13 KiB
C
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/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7722.c
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*
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* SH7722 support for the clock framework
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*
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* Copyright (c) 2006-2007 Nomad Global Solutions Inc
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* Based on code for sh7343 by Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#define SH7722_PLL_FREQ (32000000/8)
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#define N (-1)
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#define NM (-2)
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#define ROUND_NEAREST 0
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#define ROUND_DOWN -1
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#define ROUND_UP +1
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static int adjust_algos[][3] = {
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{}, /* NO_CHANGE */
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{ NM, N, 1 }, /* N:1, N:1 */
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{ 3, 2, 2 }, /* 3:2:2 */
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{ 5, 2, 2 }, /* 5:2:2 */
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{ N, 1, 1 }, /* N:1:1 */
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{ N, 1 }, /* N:1 */
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{ N, 1 }, /* N:1 */
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{ 3, 2 },
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{ 4, 3 },
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{ 5, 4 },
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{ N, 1 }
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};
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static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2,
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int m1, int m2, int round_flag)
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{
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unsigned long rem, div;
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int the_one = 0;
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pr_debug( "Actual values: r1 = %ld\n", r1);
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pr_debug( "...............r2 = %ld\n", r2);
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if (m1 == m2) {
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r2 = r1;
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pr_debug( "setting equal rates: r2 now %ld\n", r2);
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} else if ((m2 == N && m1 == 1) ||
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(m2 == NM && m1 == N)) { /* N:1 or NM:N */
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pr_debug( "Setting rates as 1:N (N:N*M)\n");
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rem = r2 % r1;
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pr_debug( "...remainder = %ld\n", rem);
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if (rem) {
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div = r2 / r1;
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pr_debug( "...div = %ld\n", div);
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switch (round_flag) {
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case ROUND_NEAREST:
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the_one = rem >= r1/2 ? 1 : 0; break;
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case ROUND_UP:
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the_one = 1; break;
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case ROUND_DOWN:
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the_one = 0; break;
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}
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r2 = r1 * (div + the_one);
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pr_debug( "...setting r2 to %ld\n", r2);
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}
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} else if ((m2 == 1 && m1 == N) ||
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(m2 == N && m1 == NM)) { /* 1:N or N:NM */
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pr_debug( "Setting rates as N:1 (N*M:N)\n");
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rem = r1 % r2;
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pr_debug( "...remainder = %ld\n", rem);
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if (rem) {
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div = r1 / r2;
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pr_debug( "...div = %ld\n", div);
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switch (round_flag) {
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case ROUND_NEAREST:
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the_one = rem > r2/2 ? 1 : 0; break;
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case ROUND_UP:
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the_one = 0; break;
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case ROUND_DOWN:
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the_one = 1; break;
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}
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r2 = r1 / (div + the_one);
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pr_debug( "...setting r2 to %ld\n", r2);
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}
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} else { /* value:value */
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pr_debug( "Setting rates as %d:%d\n", m1, m2);
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div = r1 / m1;
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r2 = div * m2;
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pr_debug( "...div = %ld\n", div);
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pr_debug( "...setting r2 to %ld\n", r2);
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}
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return r2;
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}
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static void adjust_clocks(int originate, int *l, unsigned long v[],
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int n_in_line)
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{
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int x;
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pr_debug( "Go down from %d...\n", originate);
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/* go up recalculation clocks */
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for (x = originate; x>0; x -- )
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v[x-1] = adjust_pair_of_clocks(v[x], v[x-1],
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l[x], l[x-1],
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ROUND_UP);
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pr_debug( "Go up from %d...\n", originate);
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/* go down recalculation clocks */
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for (x = originate; x<n_in_line - 1; x ++ )
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v[x+1] = adjust_pair_of_clocks(v[x], v[x+1],
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l[x], l[x+1],
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ROUND_UP);
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}
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/*
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* SH7722 uses a common set of multipliers and divisors, so this
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* is quite simple..
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*/
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/*
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* Instead of having two separate multipliers/divisors set, like this:
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*
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* static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
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* static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
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*
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* I created the divisors2 array, which is used to calculate rate like
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* rate = parent * 2 / divisors2[ divisor ];
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*/
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static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
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static void master_clk_init(struct clk *clk)
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{
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clk_set_rate(clk, clk_get_rate(clk));
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}
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static void master_clk_recalc(struct clk *clk)
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{
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unsigned long frqcr = ctrl_inl(FRQCR);
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clk->rate = CONFIG_SH_PCLK_FREQ * (1 + (frqcr >> 24 & 0xF));
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}
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static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
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{
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int div = rate / SH7722_PLL_FREQ;
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int master_divs[] = { 2, 3, 4, 6, 8, 16 };
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int index;
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unsigned long frqcr;
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if (rate < SH7722_PLL_FREQ * 2)
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return -EINVAL;
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for (index = 1; index < ARRAY_SIZE(master_divs); index++)
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if (div >= master_divs[index - 1] && div < master_divs[index])
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break;
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if (index >= ARRAY_SIZE(master_divs))
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index = ARRAY_SIZE(master_divs);
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div = master_divs[index - 1];
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frqcr = ctrl_inl(FRQCR);
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frqcr &= ~(0xF << 24);
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frqcr |= ( (div-1) << 24);
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ctrl_outl(frqcr, FRQCR);
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return 0;
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}
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static struct clk_ops sh7722_master_clk_ops = {
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.init = master_clk_init,
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.recalc = master_clk_recalc,
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.set_rate = master_clk_setrate,
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};
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struct frqcr_context {
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unsigned mask;
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unsigned shift;
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};
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struct frqcr_context sh7722_get_clk_context(const char *name)
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{
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struct frqcr_context ctx = { 0, };
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if (!strcmp(name, "peripheral_clk")) {
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ctx.shift = 0;
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ctx.mask = 0xF;
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} else if (!strcmp(name, "sdram_clk")) {
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ctx.shift = 4;
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ctx.mask = 0xF;
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} else if (!strcmp(name, "bus_clk")) {
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ctx.shift = 8;
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ctx.mask = 0xF;
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} else if (!strcmp(name, "sh_clk")) {
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ctx.shift = 12;
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ctx.mask = 0xF;
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} else if (!strcmp(name, "umem_clk")) {
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ctx.shift = 16;
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ctx.mask = 0xF;
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} else if (!strcmp(name, "cpu_clk")) {
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ctx.shift = 20;
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ctx.mask = 7;
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}
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return ctx;
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}
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/**
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* sh7722_find_divisors - find divisor for setting rate
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*
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* All sh7722 clocks use the same set of multipliers/divisors. This function
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* chooses correct divisor to set the rate of clock with parent clock that
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* generates frequency of 'parent_rate'
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*
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* @parent_rate: rate of parent clock
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* @rate: requested rate to be set
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*/
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static int sh7722_find_divisors(unsigned long parent_rate, unsigned rate)
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{
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unsigned div2 = parent_rate * 2 / rate;
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int index;
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if (rate > parent_rate)
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return -EINVAL;
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for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
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if (div2 > divisors2[index] && div2 <= divisors2[index])
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break;
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}
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if (index >= ARRAY_SIZE(divisors2))
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index = ARRAY_SIZE(divisors2) - 1;
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return divisors2[index];
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}
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static void sh7722_frqcr_recalc(struct clk *clk)
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{
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struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
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unsigned long frqcr = ctrl_inl(FRQCR);
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int index;
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index = (frqcr >> ctx.shift) & ctx.mask;
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clk->rate = clk->parent->rate * 2 / divisors2[index];
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}
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static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
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int algo_id)
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{
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struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
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unsigned long parent_rate = clk->parent->rate;
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int div;
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unsigned long frqcr;
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int err = 0;
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/* pretty invalid */
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if (parent_rate < rate)
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return -EINVAL;
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/* look for multiplier/divisor pair */
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div = sh7722_find_divisors(parent_rate, rate);
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if (div<0)
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return div;
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/* calculate new value of clock rate */
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clk->rate = parent_rate * 2 / div;
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frqcr = ctrl_inl(FRQCR);
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/* FIXME: adjust as algo_id specifies */
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if (algo_id != NO_CHANGE) {
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int originator;
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char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" };
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char *algo_group_2[] = { "sh_clk", "bus_clk" };
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char *algo_group_3[] = { "sh_clk", "sdram_clk" };
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char *algo_group_4[] = { "bus_clk", "peripheral_clk" };
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char *algo_group_5[] = { "cpu_clk", "peripheral_clk" };
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char **algo_current = NULL;
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/* 3 is the maximum number of clocks in relation */
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struct clk *ck[3];
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unsigned long values[3]; /* the same comment as above */
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int part_length = -1;
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int i;
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/*
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* all the steps below only required if adjustion was
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* requested
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*/
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if (algo_id == IUS_N1_N1 ||
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algo_id == IUS_322 ||
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algo_id == IUS_522 ||
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algo_id == IUS_N11) {
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algo_current = algo_group_1;
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part_length = 3;
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}
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if (algo_id == SB_N1) {
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algo_current = algo_group_2;
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part_length = 2;
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}
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if (algo_id == SB3_N1 ||
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algo_id == SB3_32 ||
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algo_id == SB3_43 ||
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algo_id == SB3_54) {
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algo_current = algo_group_3;
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part_length = 2;
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}
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if (algo_id == BP_N1) {
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algo_current = algo_group_4;
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part_length = 2;
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}
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if (algo_id == IP_N1) {
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algo_current = algo_group_5;
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part_length = 2;
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}
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if (!algo_current)
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goto incorrect_algo_id;
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originator = -1;
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for (i = 0; i < part_length; i ++ ) {
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if (originator >= 0 && !strcmp(clk->name,
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algo_current[i]))
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originator = i;
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ck[i] = clk_get(NULL, algo_current[i]);
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values[i] = clk_get_rate(ck[i]);
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}
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if (originator >= 0)
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adjust_clocks(originator, adjust_algos[algo_id],
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values, part_length);
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for (i = 0; i < part_length; i ++ ) {
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struct frqcr_context part_ctx;
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int part_div;
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if (likely(!err)) {
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part_div = sh7722_find_divisors(parent_rate,
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rate);
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if (part_div > 0) {
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part_ctx = sh7722_get_clk_context(
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ck[i]->name);
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frqcr &= ~(part_ctx.mask <<
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part_ctx.shift);
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frqcr |= part_div << part_ctx.shift;
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} else
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err = part_div;
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}
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ck[i]->ops->recalc(ck[i]);
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clk_put(ck[i]);
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}
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}
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/* was there any error during recalculation ? If so, bail out.. */
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if (unlikely(err!=0))
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goto out_err;
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/* clear FRQCR bits */
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frqcr &= ~(ctx.mask << ctx.shift);
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frqcr |= div << ctx.shift;
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/* ...and perform actual change */
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ctrl_outl(frqcr, FRQCR);
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return 0;
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incorrect_algo_id:
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return -EINVAL;
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out_err:
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return err;
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}
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static struct clk_ops sh7722_frqcr_clk_ops = {
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.recalc = sh7722_frqcr_recalc,
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.set_rate = sh7722_frqcr_set_rate,
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};
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/*
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* clock ops methods for SIU A/B and IrDA clock
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*
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*/
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static int sh7722_siu_which(struct clk *clk)
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{
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if (!strcmp(clk->name, "siu_a_clk"))
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return 0;
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if (!strcmp(clk->name, "siu_b_clk"))
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return 1;
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if (!strcmp(clk->name, "irda_clk"))
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return 2;
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return -EINVAL;
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}
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static unsigned long sh7722_siu_regs[] = {
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[0] = SCLKACR,
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[1] = SCLKBCR,
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[2] = IrDACLKCR,
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};
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static int sh7722_siu_start_stop(struct clk *clk, int enable)
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{
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int siu = sh7722_siu_which(clk);
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unsigned long r;
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if (siu < 0)
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return siu;
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BUG_ON(siu > 2);
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r = ctrl_inl(sh7722_siu_regs[siu]);
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if (enable)
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ctrl_outl(r & ~(1 << 8), sh7722_siu_regs[siu]);
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else
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ctrl_outl(r | (1 << 8), sh7722_siu_regs[siu]);
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return 0;
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}
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static void sh7722_siu_enable(struct clk *clk)
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{
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sh7722_siu_start_stop(clk, 1);
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}
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static void sh7722_siu_disable(struct clk *clk)
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{
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sh7722_siu_start_stop(clk, 0);
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|
}
|
||
|
|
||
|
static void sh7722_video_enable(struct clk *clk)
|
||
|
{
|
||
|
unsigned long r;
|
||
|
|
||
|
r = ctrl_inl(VCLKCR);
|
||
|
ctrl_outl( r & ~(1<<8), VCLKCR);
|
||
|
}
|
||
|
|
||
|
static void sh7722_video_disable(struct clk *clk)
|
||
|
{
|
||
|
unsigned long r;
|
||
|
|
||
|
r = ctrl_inl(VCLKCR);
|
||
|
ctrl_outl( r | (1<<8), VCLKCR);
|
||
|
}
|
||
|
|
||
|
static int sh7722_video_set_rate(struct clk *clk, unsigned long rate,
|
||
|
int algo_id)
|
||
|
{
|
||
|
unsigned long r;
|
||
|
|
||
|
r = ctrl_inl(VCLKCR);
|
||
|
r &= ~0x3F;
|
||
|
r |= ((clk->parent->rate / rate - 1) & 0x3F);
|
||
|
ctrl_outl(r, VCLKCR);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void sh7722_video_recalc(struct clk *clk)
|
||
|
{
|
||
|
unsigned long r;
|
||
|
|
||
|
r = ctrl_inl(VCLKCR);
|
||
|
clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
|
||
|
}
|
||
|
|
||
|
static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
|
||
|
{
|
||
|
int siu = sh7722_siu_which(clk);
|
||
|
unsigned long r;
|
||
|
int div;
|
||
|
|
||
|
if (siu < 0)
|
||
|
return siu;
|
||
|
BUG_ON(siu > 2);
|
||
|
r = ctrl_inl(sh7722_siu_regs[siu]);
|
||
|
div = sh7722_find_divisors(clk->parent->rate, rate);
|
||
|
if (div < 0)
|
||
|
return div;
|
||
|
r = (r & ~0xF) | div;
|
||
|
ctrl_outl(r, sh7722_siu_regs[siu]);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static void sh7722_siu_recalc(struct clk *clk)
|
||
|
{
|
||
|
int siu = sh7722_siu_which(clk);
|
||
|
unsigned long r;
|
||
|
|
||
|
if (siu < 0)
|
||
|
return /* siu */ ;
|
||
|
BUG_ON(siu > 1);
|
||
|
r = ctrl_inl(sh7722_siu_regs[siu]);
|
||
|
clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
|
||
|
}
|
||
|
|
||
|
static struct clk_ops sh7722_siu_clk_ops = {
|
||
|
.recalc = sh7722_siu_recalc,
|
||
|
.set_rate = sh7722_siu_set_rate,
|
||
|
.enable = sh7722_siu_enable,
|
||
|
.disable = sh7722_siu_disable,
|
||
|
};
|
||
|
|
||
|
static struct clk_ops sh7722_video_clk_ops = {
|
||
|
.recalc = sh7722_video_recalc,
|
||
|
.set_rate = sh7722_video_set_rate,
|
||
|
.enable = sh7722_video_enable,
|
||
|
.disable = sh7722_video_disable,
|
||
|
};
|
||
|
/*
|
||
|
* and at last, clock definitions themselves
|
||
|
*/
|
||
|
static struct clk sh7722_umem_clock = {
|
||
|
.name = "umem_clk",
|
||
|
.ops = &sh7722_frqcr_clk_ops,
|
||
|
};
|
||
|
|
||
|
static struct clk sh7722_sh_clock = {
|
||
|
.name = "sh_clk",
|
||
|
.ops = &sh7722_frqcr_clk_ops,
|
||
|
};
|
||
|
|
||
|
static struct clk sh7722_peripheral_clock = {
|
||
|
.name = "peripheral_clk",
|
||
|
.ops = &sh7722_frqcr_clk_ops,
|
||
|
};
|
||
|
|
||
|
static struct clk sh7722_sdram_clock = {
|
||
|
.name = "sdram_clk",
|
||
|
.ops = &sh7722_frqcr_clk_ops,
|
||
|
};
|
||
|
|
||
|
/*
|
||
|
* these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
|
||
|
* methods of clk_ops determine which register they should access by
|
||
|
* examining clk->name field
|
||
|
*/
|
||
|
static struct clk sh7722_siu_a_clock = {
|
||
|
.name = "siu_a_clk",
|
||
|
.ops = &sh7722_siu_clk_ops,
|
||
|
};
|
||
|
|
||
|
static struct clk sh7722_siu_b_clock = {
|
||
|
.name = "siu_b_clk",
|
||
|
.ops = &sh7722_siu_clk_ops,
|
||
|
};
|
||
|
|
||
|
static struct clk sh7722_irda_clock = {
|
||
|
.name = "irda_clk",
|
||
|
.ops = &sh7722_siu_clk_ops,
|
||
|
};
|
||
|
|
||
|
static struct clk sh7722_video_clock = {
|
||
|
.name = "video_clk",
|
||
|
.ops = &sh7722_video_clk_ops,
|
||
|
};
|
||
|
|
||
|
static struct clk *sh7722_clocks[] = {
|
||
|
&sh7722_umem_clock,
|
||
|
&sh7722_sh_clock,
|
||
|
&sh7722_peripheral_clock,
|
||
|
&sh7722_sdram_clock,
|
||
|
&sh7722_siu_a_clock,
|
||
|
&sh7722_siu_b_clock,
|
||
|
&sh7722_irda_clock,
|
||
|
&sh7722_video_clock,
|
||
|
};
|
||
|
|
||
|
/*
|
||
|
* init in order: master, module, bus, cpu
|
||
|
*/
|
||
|
struct clk_ops *onchip_ops[] = {
|
||
|
&sh7722_master_clk_ops,
|
||
|
&sh7722_frqcr_clk_ops,
|
||
|
&sh7722_frqcr_clk_ops,
|
||
|
&sh7722_frqcr_clk_ops,
|
||
|
};
|
||
|
|
||
|
void __init
|
||
|
arch_init_clk_ops(struct clk_ops **ops, int type)
|
||
|
{
|
||
|
BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
|
||
|
*ops = onchip_ops[type];
|
||
|
}
|
||
|
|
||
|
int __init sh7722_clock_init(void)
|
||
|
{
|
||
|
struct clk *master;
|
||
|
int i;
|
||
|
|
||
|
master = clk_get(NULL, "master_clk");
|
||
|
for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) {
|
||
|
pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
|
||
|
sh7722_clocks[i]->parent = master;
|
||
|
clk_register(sh7722_clocks[i]);
|
||
|
}
|
||
|
clk_put(master);
|
||
|
return 0;
|
||
|
}
|
||
|
arch_initcall(sh7722_clock_init);
|