2018-01-27 02:50:27 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2014-07-23 05:23:45 +08:00
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/*
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* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
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*
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* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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2017-03-27 17:45:08 +08:00
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#include <linux/delay.h>
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2017-10-09 17:03:37 +08:00
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#include <linux/device.h>
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2014-07-23 05:23:45 +08:00
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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2016-08-25 04:57:47 +08:00
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#include <linux/init.h>
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2017-03-27 17:45:08 +08:00
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#include <linux/of_device.h>
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2015-07-28 21:39:09 +08:00
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#include <linux/of_gpio.h>
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2017-01-11 20:06:53 +08:00
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#include <linux/of_pci.h>
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2014-07-23 05:23:45 +08:00
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/resource.h>
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#include <linux/types.h>
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2017-03-27 17:45:11 +08:00
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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2014-07-23 05:23:45 +08:00
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2018-05-31 09:12:37 +08:00
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#include "../../pci.h"
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2014-07-23 05:23:45 +08:00
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#include "pcie-designware.h"
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/* PCIe controller wrapper DRA7XX configuration registers */
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#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
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#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
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#define ERR_SYS BIT(0)
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#define ERR_FATAL BIT(1)
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#define ERR_NONFATAL BIT(2)
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#define ERR_COR BIT(3)
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#define ERR_AXI BIT(4)
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#define ERR_ECRC BIT(5)
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#define PME_TURN_OFF BIT(8)
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#define PME_TO_ACK BIT(9)
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#define PM_PME BIT(10)
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#define LINK_REQ_RST BIT(11)
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#define LINK_UP_EVT BIT(12)
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#define CFG_BME_EVT BIT(13)
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#define CFG_MSE_EVT BIT(14)
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#define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
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ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
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LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
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#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
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#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
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#define INTA BIT(0)
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#define INTB BIT(1)
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#define INTC BIT(2)
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#define INTD BIT(3)
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#define MSI BIT(4)
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#define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
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2017-03-27 17:45:08 +08:00
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#define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
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#define DEVICE_TYPE_EP 0x0
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#define DEVICE_TYPE_LEG_EP 0x1
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#define DEVICE_TYPE_RC 0x4
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2014-07-23 05:23:45 +08:00
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#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
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#define LTSSM_EN 0x1
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#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
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#define LINK_UP BIT(16)
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2015-10-30 08:56:51 +08:00
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#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
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2014-07-23 05:23:45 +08:00
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2017-01-11 20:06:53 +08:00
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#define EXP_CAP_ID_OFFSET 0x70
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2017-03-27 17:45:08 +08:00
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#define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
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#define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
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#define PCIECTRL_TI_CONF_MSI_XMT 0x012c
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#define MSI_REQ_GRANT BIT(0)
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#define MSI_VECTOR_SHIFT 7
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2019-01-24 16:29:57 +08:00
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#define PCIE_1LANE_2LANE_SELECTION BIT(13)
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#define PCIE_B1C0_MODE_SEL BIT(2)
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#define PCIE_B0_B1_TSYNCEN BIT(0)
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2014-07-23 05:23:45 +08:00
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struct dra7xx_pcie {
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci;
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2016-10-07 02:33:06 +08:00
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void __iomem *base; /* DT ti_conf */
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int phy_count; /* DT phy-names count */
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struct phy **phy;
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2017-01-11 20:06:53 +08:00
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int link_gen;
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2017-01-11 20:06:54 +08:00
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struct irq_domain *irq_domain;
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2017-03-27 17:45:08 +08:00
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enum dw_pcie_device_mode mode;
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};
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struct dra7xx_pcie_of_data {
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enum dw_pcie_device_mode mode;
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2019-01-24 16:29:57 +08:00
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u32 b1co_mode_sel_mask;
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2014-07-23 05:23:45 +08:00
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};
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2017-02-15 21:18:14 +08:00
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#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
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2014-07-23 05:23:45 +08:00
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static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
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{
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return readl(pcie->base + offset);
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}
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static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
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u32 value)
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{
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writel(value, pcie->base + offset);
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}
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PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument
The current cpu addr fixup mask for ARTPEC-6, GENMASK(27, 0), is wrong.
The correct cpu addr fixup mask for ARTPEC-6 is GENMASK(28, 0).
However, having a hardcoded cpu addr fixup mask in each driver is
arguably wrong.
A device tree property called something like "cpu-addr-fixup-mask"
would have been a better solution.
Introducing such a property is not needed though, since we already have
pp->cfg0_base and ep->phys_base, which is derived from already existing
device tree properties.
It is also worth noting that for ARTPEC-7, hardcoding the cpu addr fixup
mask is not possible, since it uses a High Address Bits Look Up Table,
which means that it can, at runtime, map the PCIe window to an arbitrary
address in the 32-bit address space.
By using pp->cfg0_base and ep->phys_base, we avoid hardcoding a mask
in each driver. This should work for ARTPEC-6, DRA7xx, and ARTPEC-7.
I have not changed the code in DRA7xx though, since their existing
code works, but if they want, they could use the same logic as
artpec6_pcie_cpu_addr_fixup, and thus remove their hardcoded mask.
The reason why the fixup mask is needed is explained in commit f4c55c5a3f7f
("PCI: designware: Program ATU with untranslated address").
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-12-20 07:29:36 +08:00
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static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
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2017-03-13 21:43:23 +08:00
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{
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return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
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}
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2017-02-15 21:18:14 +08:00
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static int dra7xx_pcie_link_up(struct dw_pcie *pci)
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2014-07-23 05:23:45 +08:00
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{
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2017-02-15 21:18:14 +08:00
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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2014-07-23 05:23:45 +08:00
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u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
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return !!(reg & LINK_UP);
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}
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2017-03-27 17:45:08 +08:00
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static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
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2014-07-23 05:23:45 +08:00
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{
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2017-03-27 17:45:08 +08:00
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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u32 reg;
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
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reg &= ~LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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}
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static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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2017-02-15 21:18:14 +08:00
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struct device *dev = pci->dev;
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2015-06-03 05:47:17 +08:00
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u32 reg;
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2017-01-11 20:06:53 +08:00
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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2014-07-23 05:23:45 +08:00
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2017-02-15 21:18:14 +08:00
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if (dw_pcie_link_up(pci)) {
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2016-10-07 02:33:06 +08:00
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dev_err(dev, "link is already up\n");
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2014-07-23 05:23:45 +08:00
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return 0;
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}
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2017-01-11 20:06:53 +08:00
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if (dra7xx->link_gen == 1) {
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2017-02-15 21:18:14 +08:00
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dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
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2017-02-15 21:18:12 +08:00
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4, ®);
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2017-01-11 20:06:53 +08:00
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if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
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reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
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reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
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2017-02-15 21:18:14 +08:00
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dw_pcie_write(pci->dbi_base + exp_cap_off +
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2017-02-15 21:18:12 +08:00
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PCI_EXP_LNKCAP, 4, reg);
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2017-01-11 20:06:53 +08:00
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}
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2017-02-15 21:18:14 +08:00
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dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
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2017-02-15 21:18:12 +08:00
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2, ®);
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2017-01-11 20:06:53 +08:00
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if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
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reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
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reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
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2017-02-15 21:18:14 +08:00
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dw_pcie_write(pci->dbi_base + exp_cap_off +
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2017-02-15 21:18:12 +08:00
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PCI_EXP_LNKCTL2, 2, reg);
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2017-01-11 20:06:53 +08:00
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}
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}
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2014-07-23 05:23:45 +08:00
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reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
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reg |= LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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2017-03-27 17:45:08 +08:00
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return 0;
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2014-07-23 05:23:45 +08:00
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}
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2017-03-27 17:45:07 +08:00
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static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
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2014-07-23 05:23:45 +08:00
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{
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
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2017-06-19 17:51:36 +08:00
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LEG_EP_INTERRUPTS | MSI);
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2017-03-27 17:45:07 +08:00
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dra7xx_pcie_writel(dra7xx,
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PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
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2017-01-11 20:06:54 +08:00
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MSI | LEG_EP_INTERRUPTS);
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2014-07-23 05:23:45 +08:00
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}
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2017-03-27 17:45:07 +08:00
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static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
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{
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
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2017-06-19 17:51:36 +08:00
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INTERRUPTS);
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2017-03-27 17:45:07 +08:00
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
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INTERRUPTS);
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}
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static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
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{
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dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
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dra7xx_pcie_enable_msi_interrupts(dra7xx);
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}
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2017-07-16 14:39:45 +08:00
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static int dra7xx_pcie_host_init(struct pcie_port *pp)
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2014-07-23 05:23:45 +08:00
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{
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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2016-10-07 02:33:05 +08:00
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2016-03-16 19:40:33 +08:00
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dw_pcie_setup_rc(pp);
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2017-03-27 17:45:08 +08:00
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dra7xx_pcie_establish_link(pci);
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dw_pcie_wait_for_link(pci);
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2017-01-11 20:06:54 +08:00
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dw_pcie_msi_init(pp);
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2016-10-07 02:33:05 +08:00
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dra7xx_pcie_enable_interrupts(dra7xx);
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2017-07-16 14:39:45 +08:00
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return 0;
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2014-07-23 05:23:45 +08:00
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}
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2017-06-05 16:53:46 +08:00
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static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
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2014-07-23 05:23:45 +08:00
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.host_init = dra7xx_pcie_host_init,
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};
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static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = dra7xx_pcie_intx_map,
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2017-12-29 19:41:30 +08:00
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.xlate = pci_irqd_intx_xlate,
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2014-07-23 05:23:45 +08:00
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};
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static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
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{
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct device *dev = pci->dev;
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
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2014-07-23 05:23:45 +08:00
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|
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struct device_node *node = dev->of_node;
|
|
|
|
|
struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
|
|
|
|
|
|
|
|
|
|
if (!pcie_intc_node) {
|
|
|
|
|
dev_err(dev, "No PCIe Intc node found\n");
|
2016-07-15 05:18:27 +08:00
|
|
|
return -ENODEV;
|
2014-07-23 05:23:45 +08:00
|
|
|
}
|
|
|
|
|
|
2017-08-16 05:28:27 +08:00
|
|
|
dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
|
2017-01-11 20:06:54 +08:00
|
|
|
&intx_domain_ops, pp);
|
2019-02-27 12:40:36 +08:00
|
|
|
of_node_put(pcie_intc_node);
|
2017-01-11 20:06:54 +08:00
|
|
|
if (!dra7xx->irq_domain) {
|
2014-07-23 05:23:45 +08:00
|
|
|
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
2016-07-15 05:18:27 +08:00
|
|
|
return -ENODEV;
|
2014-07-23 05:23:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
|
|
|
|
|
{
|
2016-10-07 02:33:05 +08:00
|
|
|
struct dra7xx_pcie *dra7xx = arg;
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = dra7xx->pci;
|
|
|
|
|
struct pcie_port *pp = &pci->pp;
|
2017-12-29 19:41:31 +08:00
|
|
|
unsigned long reg;
|
|
|
|
|
u32 virq, bit;
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
|
|
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
|
case MSI:
|
|
|
|
|
dw_handle_msi_irq(pp);
|
|
|
|
|
break;
|
|
|
|
|
case INTA:
|
|
|
|
|
case INTB:
|
|
|
|
|
case INTC:
|
|
|
|
|
case INTD:
|
2017-12-29 19:41:31 +08:00
|
|
|
for_each_set_bit(bit, ®, PCI_NUM_INTX) {
|
|
|
|
|
virq = irq_find_mapping(dra7xx->irq_domain, bit);
|
|
|
|
|
if (virq)
|
|
|
|
|
generic_handle_irq(virq);
|
|
|
|
|
}
|
2014-07-23 05:23:45 +08:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
|
|
|
|
|
{
|
|
|
|
|
struct dra7xx_pcie *dra7xx = arg;
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = dra7xx->pci;
|
|
|
|
|
struct device *dev = pci->dev;
|
2017-03-27 17:45:08 +08:00
|
|
|
struct dw_pcie_ep *ep = &pci->ep;
|
2014-07-23 05:23:45 +08:00
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
|
|
|
|
|
|
|
|
|
|
if (reg & ERR_SYS)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "System Error\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & ERR_FATAL)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "Fatal Error\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & ERR_NONFATAL)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "Non Fatal Error\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & ERR_COR)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "Correctable Error\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & ERR_AXI)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "AXI tag lookup fatal Error\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & ERR_ECRC)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "ECRC Error\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & PME_TURN_OFF)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev,
|
2014-07-23 05:23:45 +08:00
|
|
|
"Power Management Event Turn-Off message received\n");
|
|
|
|
|
|
|
|
|
|
if (reg & PME_TO_ACK)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev,
|
2014-07-23 05:23:45 +08:00
|
|
|
"Power Management Turn-Off Ack message received\n");
|
|
|
|
|
|
|
|
|
|
if (reg & PM_PME)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "PM Power Management Event message received\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & LINK_REQ_RST)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "Link Request Reset\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
if (reg & LINK_UP_EVT) {
|
|
|
|
|
if (dra7xx->mode == DW_PCIE_EP_TYPE)
|
|
|
|
|
dw_pcie_ep_linkup(ep);
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "Link-up state change\n");
|
2017-03-27 17:45:08 +08:00
|
|
|
}
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & CFG_BME_EVT)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
if (reg & CFG_MSE_EVT)
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
|
|
|
|
|
{
|
|
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
|
2017-08-18 22:58:03 +08:00
|
|
|
enum pci_barno bar;
|
|
|
|
|
|
|
|
|
|
for (bar = BAR_0; bar <= BAR_5; bar++)
|
|
|
|
|
dw_pcie_ep_reset_bar(pci, bar);
|
2017-03-27 17:45:08 +08:00
|
|
|
|
|
|
|
|
dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
|
|
|
|
|
{
|
|
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
|
|
|
|
|
mdelay(1);
|
|
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
|
|
|
|
|
u8 interrupt_num)
|
|
|
|
|
{
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
|
|
|
|
|
reg |= MSI_REQ_GRANT;
|
|
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-02 01:36:07 +08:00
|
|
|
static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
|
2018-07-19 16:32:13 +08:00
|
|
|
enum pci_epc_irq_type type, u16 interrupt_num)
|
2017-03-27 17:45:08 +08:00
|
|
|
{
|
|
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
|
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
|
|
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
|
case PCI_EPC_IRQ_LEGACY:
|
|
|
|
|
dra7xx_pcie_raise_legacy_irq(dra7xx);
|
|
|
|
|
break;
|
|
|
|
|
case PCI_EPC_IRQ_MSI:
|
|
|
|
|
dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_err(pci->dev, "UNKNOWN IRQ type\n");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-01-14 19:15:02 +08:00
|
|
|
static const struct pci_epc_features dra7xx_pcie_epc_features = {
|
|
|
|
|
.linkup_notifier = true,
|
|
|
|
|
.msi_capable = true,
|
|
|
|
|
.msix_capable = false,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct pci_epc_features*
|
|
|
|
|
dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
|
|
|
|
|
{
|
|
|
|
|
return &dra7xx_pcie_epc_features;
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-25 17:39:40 +08:00
|
|
|
static const struct dw_pcie_ep_ops pcie_ep_ops = {
|
2017-03-27 17:45:08 +08:00
|
|
|
.ep_init = dra7xx_pcie_ep_init,
|
|
|
|
|
.raise_irq = dra7xx_pcie_raise_irq,
|
2019-01-14 19:15:02 +08:00
|
|
|
.get_features = dra7xx_pcie_get_features,
|
2017-03-27 17:45:08 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
|
|
|
|
|
struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
struct dw_pcie_ep *ep;
|
|
|
|
|
struct resource *res;
|
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
|
struct dw_pcie *pci = dra7xx->pci;
|
|
|
|
|
|
|
|
|
|
ep = &pci->ep;
|
|
|
|
|
ep->ops = &pcie_ep_ops;
|
|
|
|
|
|
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
|
2018-05-15 01:32:35 +08:00
|
|
|
pci->dbi_base = devm_ioremap_resource(dev, res);
|
|
|
|
|
if (IS_ERR(pci->dbi_base))
|
|
|
|
|
return PTR_ERR(pci->dbi_base);
|
2017-03-27 17:45:08 +08:00
|
|
|
|
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
|
2018-05-15 01:32:35 +08:00
|
|
|
pci->dbi_base2 = devm_ioremap_resource(dev, res);
|
|
|
|
|
if (IS_ERR(pci->dbi_base2))
|
|
|
|
|
return PTR_ERR(pci->dbi_base2);
|
2017-03-27 17:45:08 +08:00
|
|
|
|
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
|
|
|
|
|
if (!res)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
ep->phys_base = res->start;
|
|
|
|
|
ep->addr_size = resource_size(res);
|
|
|
|
|
|
|
|
|
|
ret = dw_pcie_ep_init(ep);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(dev, "failed to initialize endpoint\n");
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-06 13:37:39 +08:00
|
|
|
static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
|
|
|
|
|
struct platform_device *pdev)
|
2014-07-23 05:23:45 +08:00
|
|
|
{
|
|
|
|
|
int ret;
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci = dra7xx->pci;
|
|
|
|
|
struct pcie_port *pp = &pci->pp;
|
|
|
|
|
struct device *dev = pci->dev;
|
2014-07-23 05:23:45 +08:00
|
|
|
struct resource *res;
|
|
|
|
|
|
|
|
|
|
pp->irq = platform_get_irq(pdev, 1);
|
|
|
|
|
if (pp->irq < 0) {
|
|
|
|
|
dev_err(dev, "missing IRQ resource\n");
|
2017-09-01 01:52:02 +08:00
|
|
|
return pp->irq;
|
2014-07-23 05:23:45 +08:00
|
|
|
}
|
|
|
|
|
|
2016-10-07 02:33:06 +08:00
|
|
|
ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
|
2015-12-11 03:18:20 +08:00
|
|
|
IRQF_SHARED | IRQF_NO_THREAD,
|
2016-10-07 02:33:05 +08:00
|
|
|
"dra7-pcie-msi", dra7xx);
|
2014-07-23 05:23:45 +08:00
|
|
|
if (ret) {
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_err(dev, "failed to request irq\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-11 20:06:54 +08:00
|
|
|
ret = dra7xx_pcie_init_irq_domain(pp);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
return ret;
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
|
2018-05-15 01:32:35 +08:00
|
|
|
pci->dbi_base = devm_ioremap_resource(dev, res);
|
|
|
|
|
if (IS_ERR(pci->dbi_base))
|
|
|
|
|
return PTR_ERR(pci->dbi_base);
|
2014-07-23 05:23:45 +08:00
|
|
|
|
2017-12-20 07:29:29 +08:00
|
|
|
pp->ops = &dra7xx_pcie_host_ops;
|
|
|
|
|
|
2014-07-23 05:23:45 +08:00
|
|
|
ret = dw_pcie_host_init(pp);
|
|
|
|
|
if (ret) {
|
2016-10-07 02:33:06 +08:00
|
|
|
dev_err(dev, "failed to initialize host\n");
|
2014-07-23 05:23:45 +08:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-15 21:18:14 +08:00
|
|
|
static const struct dw_pcie_ops dw_pcie_ops = {
|
2017-03-13 21:43:23 +08:00
|
|
|
.cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
|
2017-03-27 17:45:08 +08:00
|
|
|
.start_link = dra7xx_pcie_establish_link,
|
|
|
|
|
.stop_link = dra7xx_pcie_stop_link,
|
2017-02-15 21:18:14 +08:00
|
|
|
.link_up = dra7xx_pcie_link_up,
|
|
|
|
|
};
|
|
|
|
|
|
2017-01-11 20:06:55 +08:00
|
|
|
static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
|
|
|
|
|
{
|
|
|
|
|
int phy_count = dra7xx->phy_count;
|
|
|
|
|
|
|
|
|
|
while (phy_count--) {
|
|
|
|
|
phy_power_off(dra7xx->phy[phy_count]);
|
|
|
|
|
phy_exit(dra7xx->phy[phy_count]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
|
|
|
|
|
{
|
|
|
|
|
int phy_count = dra7xx->phy_count;
|
|
|
|
|
int ret;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < phy_count; i++) {
|
2019-01-24 18:45:37 +08:00
|
|
|
ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
goto err_phy;
|
|
|
|
|
|
2017-01-11 20:06:55 +08:00
|
|
|
ret = phy_init(dra7xx->phy[i]);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
goto err_phy;
|
|
|
|
|
|
|
|
|
|
ret = phy_power_on(dra7xx->phy[i]);
|
|
|
|
|
if (ret < 0) {
|
|
|
|
|
phy_exit(dra7xx->phy[i]);
|
|
|
|
|
goto err_phy;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_phy:
|
|
|
|
|
while (--i >= 0) {
|
|
|
|
|
phy_power_off(dra7xx->phy[i]);
|
|
|
|
|
phy_exit(dra7xx->phy[i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
|
|
|
|
|
.mode = DW_PCIE_RC_TYPE,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
|
|
|
|
|
.mode = DW_PCIE_EP_TYPE,
|
|
|
|
|
};
|
|
|
|
|
|
2019-01-24 16:29:57 +08:00
|
|
|
static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
|
|
|
|
|
.b1co_mode_sel_mask = BIT(2),
|
|
|
|
|
.mode = DW_PCIE_RC_TYPE,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
|
|
|
|
|
.b1co_mode_sel_mask = GENMASK(3, 2),
|
|
|
|
|
.mode = DW_PCIE_RC_TYPE,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
|
|
|
|
|
.b1co_mode_sel_mask = BIT(2),
|
|
|
|
|
.mode = DW_PCIE_EP_TYPE,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
|
|
|
|
|
.b1co_mode_sel_mask = GENMASK(3, 2),
|
|
|
|
|
.mode = DW_PCIE_EP_TYPE,
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
static const struct of_device_id of_dra7xx_pcie_match[] = {
|
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,dra7-pcie",
|
|
|
|
|
.data = &dra7xx_pcie_rc_of_data,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,dra7-pcie-ep",
|
|
|
|
|
.data = &dra7xx_pcie_ep_of_data,
|
|
|
|
|
},
|
2019-01-24 16:29:57 +08:00
|
|
|
{
|
|
|
|
|
.compatible = "ti,dra746-pcie-rc",
|
|
|
|
|
.data = &dra746_pcie_rc_of_data,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,dra726-pcie-rc",
|
|
|
|
|
.data = &dra726_pcie_rc_of_data,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,dra746-pcie-ep",
|
|
|
|
|
.data = &dra746_pcie_ep_of_data,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,dra726-pcie-ep",
|
|
|
|
|
.data = &dra726_pcie_ep_of_data,
|
|
|
|
|
},
|
2017-03-27 17:45:08 +08:00
|
|
|
{},
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-27 17:45:11 +08:00
|
|
|
/*
|
2018-09-25 16:30:24 +08:00
|
|
|
* dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
|
2017-03-27 17:45:11 +08:00
|
|
|
* @dra7xx: the dra7xx device where the workaround should be applied
|
|
|
|
|
*
|
|
|
|
|
* Access to the PCIe slave port that are not 32-bit aligned will result
|
|
|
|
|
* in incorrect mapping to TLP Address and Byte enable fields. Therefore,
|
|
|
|
|
* byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
|
|
|
|
|
* 0x3.
|
|
|
|
|
*
|
|
|
|
|
* To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
|
|
|
|
|
*/
|
2018-09-25 16:30:24 +08:00
|
|
|
static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
|
2017-03-27 17:45:11 +08:00
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
|
struct of_phandle_args args;
|
|
|
|
|
struct regmap *regmap;
|
|
|
|
|
|
|
|
|
|
regmap = syscon_regmap_lookup_by_phandle(np,
|
|
|
|
|
"ti,syscon-unaligned-access");
|
|
|
|
|
if (IS_ERR(regmap)) {
|
|
|
|
|
dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
|
|
|
|
|
2, 0, &args);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ret = regmap_update_bits(regmap, args.args[0], args.args[1],
|
|
|
|
|
args.args[1]);
|
|
|
|
|
if (ret)
|
|
|
|
|
dev_err(dev, "failed to enable unaligned access\n");
|
|
|
|
|
|
|
|
|
|
of_node_put(args.np);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2019-01-24 16:29:57 +08:00
|
|
|
static int dra7xx_pcie_configure_two_lane(struct device *dev,
|
|
|
|
|
u32 b1co_mode_sel_mask)
|
|
|
|
|
{
|
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
|
struct regmap *pcie_syscon;
|
|
|
|
|
unsigned int pcie_reg;
|
|
|
|
|
u32 mask;
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
|
|
|
|
|
if (IS_ERR(pcie_syscon)) {
|
|
|
|
|
dev_err(dev, "unable to get ti,syscon-lane-sel\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
|
|
|
|
|
&pcie_reg)) {
|
|
|
|
|
dev_err(dev, "couldn't get lane selection reg offset\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
|
|
|
|
|
val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
|
|
|
|
|
regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-23 05:23:45 +08:00
|
|
|
static int __init dra7xx_pcie_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
u32 reg;
|
|
|
|
|
int ret;
|
|
|
|
|
int irq;
|
|
|
|
|
int i;
|
|
|
|
|
int phy_count;
|
|
|
|
|
struct phy **phy;
|
2017-10-09 17:03:37 +08:00
|
|
|
struct device_link **link;
|
2014-07-23 05:23:45 +08:00
|
|
|
void __iomem *base;
|
|
|
|
|
struct resource *res;
|
2017-02-15 21:18:14 +08:00
|
|
|
struct dw_pcie *pci;
|
|
|
|
|
struct dra7xx_pcie *dra7xx;
|
2014-07-23 05:23:45 +08:00
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
|
char name[10];
|
2017-01-11 20:06:52 +08:00
|
|
|
struct gpio_desc *reset;
|
2017-03-27 17:45:08 +08:00
|
|
|
const struct of_device_id *match;
|
|
|
|
|
const struct dra7xx_pcie_of_data *data;
|
|
|
|
|
enum dw_pcie_device_mode mode;
|
2019-01-24 16:29:57 +08:00
|
|
|
u32 b1co_mode_sel_mask;
|
2017-03-27 17:45:08 +08:00
|
|
|
|
|
|
|
|
match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
|
|
|
|
|
if (!match)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
data = (struct dra7xx_pcie_of_data *)match->data;
|
|
|
|
|
mode = (enum dw_pcie_device_mode)data->mode;
|
2019-01-24 16:29:57 +08:00
|
|
|
b1co_mode_sel_mask = data->b1co_mode_sel_mask;
|
2014-07-23 05:23:45 +08:00
|
|
|
|
|
|
|
|
dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
|
|
|
|
|
if (!dra7xx)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2017-02-15 21:18:14 +08:00
|
|
|
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
|
|
|
|
|
if (!pci)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
pci->dev = dev;
|
|
|
|
|
pci->ops = &dw_pcie_ops;
|
|
|
|
|
|
2014-07-23 05:23:45 +08:00
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
|
if (irq < 0) {
|
2017-08-10 00:16:03 +08:00
|
|
|
dev_err(dev, "missing IRQ resource: %d\n", irq);
|
|
|
|
|
return irq;
|
2014-07-23 05:23:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
|
|
|
|
|
base = devm_ioremap_nocache(dev, res->start, resource_size(res));
|
|
|
|
|
if (!base)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
phy_count = of_property_count_strings(np, "phy-names");
|
|
|
|
|
if (phy_count < 0) {
|
|
|
|
|
dev_err(dev, "unable to find the strings\n");
|
|
|
|
|
return phy_count;
|
|
|
|
|
}
|
|
|
|
|
|
treewide: devm_kzalloc() -> devm_kcalloc()
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc().
This patch replaces cases of:
devm_kzalloc(handle, a * b, gfp)
with:
devm_kcalloc(handle, a * b, gfp)
as well as handling cases of:
devm_kzalloc(handle, a * b * c, gfp)
with:
devm_kzalloc(handle, array3_size(a, b, c), gfp)
as it's slightly less ugly than:
devm_kcalloc(handle, array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
devm_kzalloc(handle, 4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
Some manual whitespace fixes were needed in this patch, as Coccinelle
really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...".
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
expression HANDLE;
type TYPE;
expression THING, E;
@@
(
devm_kzalloc(HANDLE,
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
devm_kzalloc(HANDLE,
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression HANDLE;
expression COUNT;
typedef u8;
typedef __u8;
@@
(
devm_kzalloc(HANDLE,
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
expression HANDLE;
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
expression HANDLE;
identifier SIZE, COUNT;
@@
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression HANDLE;
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression HANDLE;
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
expression HANDLE;
identifier STRIDE, SIZE, COUNT;
@@
(
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression HANDLE;
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE,
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression HANDLE;
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, sizeof(THING) * C2, ...)
|
devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...)
|
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE, C1 * C2, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * E2
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * (E2)
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-13 05:07:58 +08:00
|
|
|
phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
|
2014-07-23 05:23:45 +08:00
|
|
|
if (!phy)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
treewide: devm_kzalloc() -> devm_kcalloc()
The devm_kzalloc() function has a 2-factor argument form, devm_kcalloc().
This patch replaces cases of:
devm_kzalloc(handle, a * b, gfp)
with:
devm_kcalloc(handle, a * b, gfp)
as well as handling cases of:
devm_kzalloc(handle, a * b * c, gfp)
with:
devm_kzalloc(handle, array3_size(a, b, c), gfp)
as it's slightly less ugly than:
devm_kcalloc(handle, array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
devm_kzalloc(handle, 4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
Some manual whitespace fixes were needed in this patch, as Coccinelle
really liked to write "=devm_kcalloc..." instead of "= devm_kcalloc...".
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
expression HANDLE;
type TYPE;
expression THING, E;
@@
(
devm_kzalloc(HANDLE,
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
devm_kzalloc(HANDLE,
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression HANDLE;
expression COUNT;
typedef u8;
typedef __u8;
@@
(
devm_kzalloc(HANDLE,
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(char) * COUNT
+ COUNT
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
expression HANDLE;
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
expression HANDLE;
identifier SIZE, COUNT;
@@
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression HANDLE;
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression HANDLE;
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
devm_kzalloc(HANDLE,
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
expression HANDLE;
identifier STRIDE, SIZE, COUNT;
@@
(
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
devm_kzalloc(HANDLE,
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression HANDLE;
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE,
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
devm_kzalloc(HANDLE,
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression HANDLE;
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
devm_kzalloc(HANDLE, sizeof(THING) * C2, ...)
|
devm_kzalloc(HANDLE, sizeof(TYPE) * C2, ...)
|
devm_kzalloc(HANDLE, C1 * C2 * C3, ...)
|
devm_kzalloc(HANDLE, C1 * C2, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * E2
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- (E1) * (E2)
+ E1, E2
, ...)
|
- devm_kzalloc
+ devm_kcalloc
(HANDLE,
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-13 05:07:58 +08:00
|
|
|
link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
|
2017-10-09 17:03:37 +08:00
|
|
|
if (!link)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2014-07-23 05:23:45 +08:00
|
|
|
for (i = 0; i < phy_count; i++) {
|
|
|
|
|
snprintf(name, sizeof(name), "pcie-phy%d", i);
|
|
|
|
|
phy[i] = devm_phy_get(dev, name);
|
|
|
|
|
if (IS_ERR(phy[i]))
|
|
|
|
|
return PTR_ERR(phy[i]);
|
2017-10-09 17:03:37 +08:00
|
|
|
|
|
|
|
|
link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
|
|
|
|
|
if (!link[i]) {
|
|
|
|
|
ret = -EINVAL;
|
|
|
|
|
goto err_link;
|
|
|
|
|
}
|
2014-07-23 05:23:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dra7xx->base = base;
|
|
|
|
|
dra7xx->phy = phy;
|
2017-02-15 21:18:14 +08:00
|
|
|
dra7xx->pci = pci;
|
2014-07-23 05:23:45 +08:00
|
|
|
dra7xx->phy_count = phy_count;
|
|
|
|
|
|
2019-01-24 16:29:57 +08:00
|
|
|
if (phy_count == 2) {
|
|
|
|
|
ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-11 20:06:55 +08:00
|
|
|
ret = dra7xx_pcie_enable_phy(dra7xx);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(dev, "failed to enable phy\n");
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-15 21:18:11 +08:00
|
|
|
platform_set_drvdata(pdev, dra7xx);
|
|
|
|
|
|
2014-07-23 05:23:45 +08:00
|
|
|
pm_runtime_enable(dev);
|
|
|
|
|
ret = pm_runtime_get_sync(dev);
|
2015-08-20 14:30:36 +08:00
|
|
|
if (ret < 0) {
|
2014-07-23 05:23:45 +08:00
|
|
|
dev_err(dev, "pm_runtime_get_sync failed\n");
|
2015-07-31 20:25:10 +08:00
|
|
|
goto err_get_sync;
|
2014-07-23 05:23:45 +08:00
|
|
|
}
|
|
|
|
|
|
2017-01-11 20:06:52 +08:00
|
|
|
reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
|
|
|
|
|
if (IS_ERR(reset)) {
|
|
|
|
|
ret = PTR_ERR(reset);
|
|
|
|
|
dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
|
2015-07-28 21:39:09 +08:00
|
|
|
goto err_gpio;
|
2014-07-23 05:23:45 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
|
|
|
|
|
reg &= ~LTSSM_EN;
|
|
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
|
|
|
|
|
|
2017-01-11 20:06:53 +08:00
|
|
|
dra7xx->link_gen = of_pci_get_max_link_speed(np);
|
|
|
|
|
if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
|
|
|
|
|
dra7xx->link_gen = 2;
|
|
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
switch (mode) {
|
|
|
|
|
case DW_PCIE_RC_TYPE:
|
2017-12-20 07:29:30 +08:00
|
|
|
if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
|
|
|
|
|
ret = -ENODEV;
|
|
|
|
|
goto err_gpio;
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
|
|
|
|
|
DEVICE_TYPE_RC);
|
2018-09-25 16:30:24 +08:00
|
|
|
|
|
|
|
|
ret = dra7xx_pcie_unaligned_memaccess(dev);
|
|
|
|
|
if (ret)
|
|
|
|
|
dev_err(dev, "WA for Errata i870 not applied\n");
|
|
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
ret = dra7xx_add_pcie_port(dra7xx, pdev);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
goto err_gpio;
|
|
|
|
|
break;
|
|
|
|
|
case DW_PCIE_EP_TYPE:
|
2017-12-20 07:29:30 +08:00
|
|
|
if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
|
|
|
|
|
ret = -ENODEV;
|
|
|
|
|
goto err_gpio;
|
|
|
|
|
}
|
|
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
|
|
|
|
|
DEVICE_TYPE_EP);
|
2017-03-27 17:45:11 +08:00
|
|
|
|
2018-09-25 16:30:24 +08:00
|
|
|
ret = dra7xx_pcie_unaligned_memaccess(dev);
|
2017-03-27 17:45:11 +08:00
|
|
|
if (ret)
|
|
|
|
|
goto err_gpio;
|
|
|
|
|
|
2017-03-27 17:45:08 +08:00
|
|
|
ret = dra7xx_add_pcie_ep(dra7xx, pdev);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
goto err_gpio;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
dev_err(dev, "INVALID device type %d\n", mode);
|
|
|
|
|
}
|
|
|
|
|
dra7xx->mode = mode;
|
2014-07-23 05:23:45 +08:00
|
|
|
|
2017-03-13 21:43:28 +08:00
|
|
|
ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
|
|
|
|
|
IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(dev, "failed to request irq\n");
|
|
|
|
|
goto err_gpio;
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-23 05:23:45 +08:00
|
|
|
return 0;
|
|
|
|
|
|
2015-07-28 21:39:09 +08:00
|
|
|
err_gpio:
|
2014-07-23 05:23:45 +08:00
|
|
|
pm_runtime_put(dev);
|
2015-07-31 20:25:10 +08:00
|
|
|
|
|
|
|
|
err_get_sync:
|
2014-07-23 05:23:45 +08:00
|
|
|
pm_runtime_disable(dev);
|
2017-01-11 20:06:55 +08:00
|
|
|
dra7xx_pcie_disable_phy(dra7xx);
|
2014-07-23 05:23:45 +08:00
|
|
|
|
2017-10-09 17:03:37 +08:00
|
|
|
err_link:
|
|
|
|
|
while (--i >= 0)
|
|
|
|
|
device_link_del(link[i]);
|
|
|
|
|
|
2014-07-23 05:23:45 +08:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2015-07-31 20:25:11 +08:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2015-07-31 20:25:12 +08:00
|
|
|
static int dra7xx_pcie_suspend(struct device *dev)
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{
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struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
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2017-02-15 21:18:14 +08:00
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struct dw_pcie *pci = dra7xx->pci;
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2015-07-31 20:25:12 +08:00
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u32 val;
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2017-03-27 17:45:08 +08:00
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if (dra7xx->mode != DW_PCIE_RC_TYPE)
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return 0;
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2015-07-31 20:25:12 +08:00
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/* clear MSE */
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2017-02-15 21:18:14 +08:00
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val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
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2015-07-31 20:25:12 +08:00
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val &= ~PCI_COMMAND_MEMORY;
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2017-02-15 21:18:14 +08:00
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dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
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2015-07-31 20:25:12 +08:00
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return 0;
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}
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static int dra7xx_pcie_resume(struct device *dev)
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|
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{
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|
|
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struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
2017-02-15 21:18:14 +08:00
|
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|
struct dw_pcie *pci = dra7xx->pci;
|
2015-07-31 20:25:12 +08:00
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u32 val;
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|
2017-03-27 17:45:08 +08:00
|
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if (dra7xx->mode != DW_PCIE_RC_TYPE)
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|
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return 0;
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|
2015-07-31 20:25:12 +08:00
|
|
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/* set MSE */
|
2017-02-15 21:18:14 +08:00
|
|
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val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
|
2015-07-31 20:25:12 +08:00
|
|
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val |= PCI_COMMAND_MEMORY;
|
2017-02-15 21:18:14 +08:00
|
|
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dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
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2015-07-31 20:25:12 +08:00
|
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|
|
return 0;
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}
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2015-07-31 20:25:11 +08:00
|
|
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static int dra7xx_pcie_suspend_noirq(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
|
|
|
|
|
2017-01-11 20:06:55 +08:00
|
|
|
dra7xx_pcie_disable_phy(dra7xx);
|
2015-07-31 20:25:11 +08:00
|
|
|
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|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int dra7xx_pcie_resume_noirq(struct device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
|
|
|
|
int ret;
|
|
|
|
|
|
2017-01-11 20:06:55 +08:00
|
|
|
ret = dra7xx_pcie_enable_phy(dra7xx);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(dev, "failed to enable phy\n");
|
|
|
|
|
return ret;
|
2015-07-31 20:25:11 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2017-12-01 13:06:52 +08:00
|
|
|
static void dra7xx_pcie_shutdown(struct platform_device *pdev)
|
2017-09-20 13:24:15 +08:00
|
|
|
{
|
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
|
struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
dra7xx_pcie_stop_link(dra7xx->pci);
|
|
|
|
|
|
|
|
|
|
ret = pm_runtime_put_sync(dev);
|
|
|
|
|
if (ret < 0)
|
|
|
|
|
dev_dbg(dev, "pm_runtime_put_sync failed\n");
|
|
|
|
|
|
|
|
|
|
pm_runtime_disable(dev);
|
|
|
|
|
dra7xx_pcie_disable_phy(dra7xx);
|
|
|
|
|
}
|
|
|
|
|
|
2015-07-31 20:25:11 +08:00
|
|
|
static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
|
2015-07-31 20:25:12 +08:00
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
|
2015-07-31 20:25:11 +08:00
|
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
|
|
|
|
|
dra7xx_pcie_resume_noirq)
|
|
|
|
|
};
|
|
|
|
|
|
2014-07-23 05:23:45 +08:00
|
|
|
static struct platform_driver dra7xx_pcie_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "dra7-pcie",
|
|
|
|
|
.of_match_table = of_dra7xx_pcie_match,
|
2016-08-25 04:57:47 +08:00
|
|
|
.suppress_bind_attrs = true,
|
2015-07-31 20:25:11 +08:00
|
|
|
.pm = &dra7xx_pcie_pm_ops,
|
2014-07-23 05:23:45 +08:00
|
|
|
},
|
2017-09-20 13:24:15 +08:00
|
|
|
.shutdown = dra7xx_pcie_shutdown,
|
2014-07-23 05:23:45 +08:00
|
|
|
};
|
2016-08-25 04:57:47 +08:00
|
|
|
builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
|