2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* PKUnity NAND Controller Registers
|
|
|
|
*/
|
|
|
|
/*
|
|
|
|
* ID Reg. 0 NAND_IDR0
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_IDR0 (PKUNITY_NAND_BASE + 0x0000)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* ID Reg. 1 NAND_IDR1
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_IDR1 (PKUNITY_NAND_BASE + 0x0004)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* ID Reg. 2 NAND_IDR2
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_IDR2 (PKUNITY_NAND_BASE + 0x0008)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* ID Reg. 3 NAND_IDR3
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_IDR3 (PKUNITY_NAND_BASE + 0x000C)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Page Address Reg 0 NAND_PAR0
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_PAR0 (PKUNITY_NAND_BASE + 0x0010)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Page Address Reg 1 NAND_PAR1
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_PAR1 (PKUNITY_NAND_BASE + 0x0014)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Page Address Reg 2 NAND_PAR2
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_PAR2 (PKUNITY_NAND_BASE + 0x0018)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* ECC Enable Reg NAND_ECCEN
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_ECCEN (PKUNITY_NAND_BASE + 0x001C)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Buffer Reg NAND_BUF
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_BUF (PKUNITY_NAND_BASE + 0x0020)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* ECC Status Reg NAND_ECCSR
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_ECCSR (PKUNITY_NAND_BASE + 0x0024)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Command Reg NAND_CMD
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_CMD (PKUNITY_NAND_BASE + 0x0028)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* DMA Configure Reg NAND_DMACR
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_DMACR (PKUNITY_NAND_BASE + 0x002C)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Interrupt Reg NAND_IR
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_IR (PKUNITY_NAND_BASE + 0x0030)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Interrupt Mask Reg NAND_IMR
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_IMR (PKUNITY_NAND_BASE + 0x0034)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Chip Enable Reg NAND_CHIPEN
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_CHIPEN (PKUNITY_NAND_BASE + 0x0038)
|
2011-02-26 20:08:36 +08:00
|
|
|
/*
|
|
|
|
* Address Reg NAND_ADDR
|
|
|
|
*/
|
2011-03-04 18:07:48 +08:00
|
|
|
#define NAND_ADDR (PKUNITY_NAND_BASE + 0x003C)
|
2011-02-26 20:08:36 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Command bits NAND_CMD_CMD_MASK
|
|
|
|
*/
|
|
|
|
#define NAND_CMD_CMD_MASK FMASK(4, 4)
|
|
|
|
#define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4)
|
|
|
|
#define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4)
|
|
|
|
#define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4)
|
|
|
|
#define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4)
|
|
|
|
#define NAND_CMD_CMD_READID FIELD(0x9, 4, 4)
|
|
|
|
#define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4)
|
|
|
|
|