2019-05-27 14:55:01 +08:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2005-10-10 20:36:14 +08:00
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This file contains the system call entry code, context switch
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* code, and exception/interrupt return code for PowerPC.
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*/
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#include <linux/errno.h>
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powerpc/kernel: Switch to using MAX_ERRNO
Currently on powerpc we have our own #define for the highest (negative)
errno value, called _LAST_ERRNO. This is defined to be 516, for reasons
which are not clear.
The generic code, and x86, use MAX_ERRNO, which is defined to be 4095.
In particular seccomp uses MAX_ERRNO to restrict the value that a
seccomp filter can return.
Currently with the mismatch between _LAST_ERRNO and MAX_ERRNO, a seccomp
tracer wanting to return 600, expecting it to be seen as an error, would
instead find on powerpc that userspace sees a successful syscall with a
return value of 600.
To avoid this inconsistency, switch powerpc to use MAX_ERRNO.
We are somewhat confident that generic syscalls that can return a
non-error value above negative MAX_ERRNO have already been updated to
use force_successful_syscall_return().
I have also checked all the powerpc specific syscalls, and believe that
none of them expect to return a non-error value between -MAX_ERRNO and
-516. So this change should be safe ...
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Reviewed-by: Kees Cook <keescook@chromium.org>
2015-07-23 18:21:01 +08:00
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#include <linux/err.h>
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powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
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#include <asm/cache.h>
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2005-10-10 20:36:14 +08:00
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#include <asm/unistd.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/thread_info.h>
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2018-07-23 23:07:54 +08:00
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#include <asm/code-patching-asm.h>
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2005-10-10 20:36:14 +08:00
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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2006-09-25 16:19:00 +08:00
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#include <asm/firmware.h>
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2007-01-02 02:45:34 +08:00
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#include <asm/bug.h>
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2008-04-17 12:34:59 +08:00
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#include <asm/ptrace.h>
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2008-04-17 12:35:01 +08:00
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#include <asm/irqflags.h>
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powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 15:27:59 +08:00
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#include <asm/hw_irq.h>
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2013-05-14 00:16:43 +08:00
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#include <asm/context_tracking.h>
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2015-06-12 09:06:32 +08:00
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#include <asm/tm.h>
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2016-04-26 08:28:50 +08:00
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#include <asm/ppc-opcode.h>
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2018-04-24 12:15:59 +08:00
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#include <asm/barrier.h>
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2016-01-14 12:33:46 +08:00
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#include <asm/export.h>
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2018-07-06 00:24:57 +08:00
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#include <asm/asm-compat.h>
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2018-01-10 00:07:15 +08:00
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#ifdef CONFIG_PPC_BOOK3S
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#include <asm/exception-64s.h>
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#else
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#include <asm/exception-64e.h>
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#endif
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2018-07-06 00:25:01 +08:00
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#include <asm/feature-fixups.h>
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2019-04-18 14:51:24 +08:00
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#include <asm/kup.h>
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2005-10-10 20:36:14 +08:00
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/*
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* System calls.
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*/
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.section ".toc","aw"
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2014-02-04 13:05:53 +08:00
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SYS_CALL_TABLE:
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.tc sys_call_table[TC],sys_call_table
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2005-10-10 20:36:14 +08:00
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2020-03-20 18:20:16 +08:00
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#ifdef CONFIG_COMPAT
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2018-12-17 18:40:35 +08:00
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COMPAT_SYS_CALL_TABLE:
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.tc compat_sys_call_table[TC],compat_sys_call_table
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2020-03-20 18:20:16 +08:00
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#endif
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2018-12-17 18:40:35 +08:00
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2005-10-10 20:36:14 +08:00
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/* This value is used to mark exception frames on the stack. */
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exception_marker:
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2008-04-17 12:34:59 +08:00
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.tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
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2005-10-10 20:36:14 +08:00
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.section ".text"
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.align 7
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.globl system_call_common
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system_call_common:
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2015-06-12 09:06:32 +08:00
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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BEGIN_FTR_SECTION
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extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */
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2017-06-30 01:49:16 +08:00
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bne .Ltabort_syscall
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2015-06-12 09:06:32 +08:00
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END_FTR_SECTION_IFSET(CPU_FTR_TM)
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#endif
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2020-02-26 01:35:34 +08:00
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_ASM_NOKPROBE_SYMBOL(system_call_common)
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2005-10-10 20:36:14 +08:00
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mr r10,r1
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ld r1,PACAKSAVE(r13)
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2019-08-27 11:30:07 +08:00
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std r10,0(r1)
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2005-10-10 20:36:14 +08:00
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std r11,_NIP(r1)
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std r12,_MSR(r1)
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std r0,GPR0(r1)
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std r10,GPR1(r1)
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2020-02-26 01:35:34 +08:00
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std r2,GPR2(r1)
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2018-12-12 22:03:05 +08:00
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#ifdef CONFIG_PPC_FSL_BOOK3E
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START_BTB_FLUSH_SECTION
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BTB_FLUSH(r10)
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END_BTB_FLUSH_SECTION
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#endif
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2020-02-26 01:35:34 +08:00
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ld r2,PACATOC(r13)
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mfcr r12
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li r11,0
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/* Can we avoid saving r3-r8 in common case? */
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2005-10-10 20:36:14 +08:00
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std r3,GPR3(r1)
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std r4,GPR4(r1)
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std r5,GPR5(r1)
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std r6,GPR6(r1)
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std r7,GPR7(r1)
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std r8,GPR8(r1)
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2020-02-26 01:35:34 +08:00
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/* Zero r9-r12, this should only be required when restoring all GPRs */
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2005-10-10 20:36:14 +08:00
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std r11,GPR9(r1)
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std r11,GPR10(r1)
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std r11,GPR11(r1)
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std r11,GPR12(r1)
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std r9,GPR13(r1)
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powerpc/64/syscall: Remove non-volatile GPR save optimisation
powerpc has an optimisation where interrupts avoid saving the
non-volatile (or callee saved) registers to the interrupt stack frame
if they are not required.
Two problems with this are that an interrupt does not always know
whether it will need non-volatiles; and if it does need them, they can
only be saved from the entry-scoped asm code (because we don't control
what the C compiler does with these registers).
system calls are the most difficult: some system calls always require
all registers (e.g., fork, to copy regs into the child). Sometimes
registers are only required under certain conditions (e.g., tracing,
signal delivery). These cases require ugly logic in the call
chains (e.g., ppc_fork), and require a lot of logic to be implemented
in asm.
So remove the optimisation for system calls, and always save NVGPRs on
entry. Modern high performance CPUs are not so sensitive, because the
stores are dense in cache and can be hidden by other expensive work in
the syscall path -- the null syscall selftests benchmark on POWER9 is
not slowed (124.40ns before and 123.64ns after, i.e., within the
noise).
Other interrupts retain the NVGPR optimisation for now.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-24-npiggin@gmail.com
2020-02-26 01:35:32 +08:00
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SAVE_NVGPRS(r1)
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2020-02-26 01:35:34 +08:00
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std r11,_XER(r1)
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std r11,_CTR(r1)
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2005-10-10 20:36:14 +08:00
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mflr r10
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2020-02-26 01:35:34 +08:00
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2012-04-05 11:44:48 +08:00
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/*
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* This clears CR0.SO (bit 28), which is the error indication on
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* return from this system call.
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*/
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2020-02-26 01:35:34 +08:00
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rldimi r12,r11,28,(63-28)
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powerpc/64/syscall: Remove non-volatile GPR save optimisation
powerpc has an optimisation where interrupts avoid saving the
non-volatile (or callee saved) registers to the interrupt stack frame
if they are not required.
Two problems with this are that an interrupt does not always know
whether it will need non-volatiles; and if it does need them, they can
only be saved from the entry-scoped asm code (because we don't control
what the C compiler does with these registers).
system calls are the most difficult: some system calls always require
all registers (e.g., fork, to copy regs into the child). Sometimes
registers are only required under certain conditions (e.g., tracing,
signal delivery). These cases require ugly logic in the call
chains (e.g., ppc_fork), and require a lot of logic to be implemented
in asm.
So remove the optimisation for system calls, and always save NVGPRs on
entry. Modern high performance CPUs are not so sensitive, because the
stores are dense in cache and can be hidden by other expensive work in
the syscall path -- the null syscall selftests benchmark on POWER9 is
not slowed (124.40ns before and 123.64ns after, i.e., within the
noise).
Other interrupts retain the NVGPR optimisation for now.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-24-npiggin@gmail.com
2020-02-26 01:35:32 +08:00
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li r11,0xc00
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2005-10-10 20:36:14 +08:00
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std r10,_LINK(r1)
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std r11,_TRAP(r1)
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2020-02-26 01:35:34 +08:00
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std r12,_CCR(r1)
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2005-10-10 20:36:14 +08:00
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std r3,ORIG_GPR3(r1)
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2020-02-26 01:35:34 +08:00
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addi r10,r1,STACK_FRAME_OVERHEAD
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2005-10-10 20:36:14 +08:00
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ld r11,exception_marker@toc(r2)
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2020-02-26 01:35:34 +08:00
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std r11,-16(r10) /* "regshere" marker */
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2018-04-24 12:15:59 +08:00
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2020-02-26 01:35:39 +08:00
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/*
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* RECONCILE_IRQ_STATE without calling trace_hardirqs_off(), which
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* would clobber syscall parameters. Also we always enter with IRQs
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* enabled and nothing pending. system_call_exception() will call
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* trace_hardirqs_off().
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*/
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li r11,IRQS_ALL_DISABLED
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li r12,PACA_IRQ_HARD_DIS
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stb r11,PACAIRQSOFTMASK(r13)
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stb r12,PACAIRQHAPPENED(r13)
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2020-02-26 01:35:34 +08:00
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/* Calling convention has r9 = orig r0, r10 = regs */
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mr r9,r0
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bl system_call_exception
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2005-10-10 20:36:14 +08:00
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2014-12-05 18:16:59 +08:00
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.Lsyscall_exit:
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2020-02-26 01:35:34 +08:00
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addi r4,r1,STACK_FRAME_OVERHEAD
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bl syscall_exit_prepare
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2009-07-24 07:15:59 +08:00
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2020-02-26 01:35:34 +08:00
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ld r2,_CCR(r1)
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ld r4,_NIP(r1)
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ld r5,_MSR(r1)
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ld r6,_LINK(r1)
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2016-02-29 14:53:47 +08:00
|
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2010-08-11 09:40:27 +08:00
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BEGIN_FTR_SECTION
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2005-10-10 20:36:14 +08:00
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stdcx. r0,0,r1 /* to clear the reservation */
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2010-08-11 09:40:27 +08:00
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END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
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2019-04-18 14:51:24 +08:00
|
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2020-02-26 01:35:34 +08:00
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|
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mtspr SPRN_SRR0,r4
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mtspr SPRN_SRR1,r5
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mtlr r6
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2018-11-29 14:42:24 +08:00
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2020-02-26 01:35:34 +08:00
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cmpdi r3,0
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bne .Lsyscall_restore_regs
|
2020-02-26 01:35:35 +08:00
|
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|
/* Zero volatile regs that may contain sensitive kernel data */
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li r0,0
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li r4,0
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li r5,0
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li r6,0
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li r7,0
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li r8,0
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li r9,0
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li r10,0
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li r11,0
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li r12,0
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mtctr r0
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mtspr SPRN_XER,r0
|
2020-02-26 01:35:34 +08:00
|
|
|
.Lsyscall_restore_regs_cont:
|
2015-11-25 11:25:17 +08:00
|
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BEGIN_FTR_SECTION
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HMT_MEDIUM_LOW
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|
|
END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
|
|
|
|
|
|
2019-04-18 14:51:24 +08:00
|
|
|
/*
|
|
|
|
|
* We don't need to restore AMR on the way back to userspace for KUAP.
|
|
|
|
|
* The value of AMR only matters while we're in the kernel.
|
|
|
|
|
*/
|
2020-02-26 01:35:34 +08:00
|
|
|
mtcr r2
|
2018-01-10 00:07:15 +08:00
|
|
|
ld r2,GPR2(r1)
|
2020-02-26 01:35:34 +08:00
|
|
|
ld r3,GPR3(r1)
|
|
|
|
|
ld r13,GPR13(r1)
|
2018-01-10 00:07:15 +08:00
|
|
|
ld r1,GPR1(r1)
|
|
|
|
|
RFI_TO_USER
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
2020-02-26 01:35:34 +08:00
|
|
|
.Lsyscall_restore_regs:
|
|
|
|
|
ld r3,_CTR(r1)
|
|
|
|
|
ld r4,_XER(r1)
|
2006-03-08 10:24:22 +08:00
|
|
|
REST_NVGPRS(r1)
|
2020-02-26 01:35:34 +08:00
|
|
|
mtctr r3
|
|
|
|
|
mtspr SPRN_XER,r4
|
|
|
|
|
ld r0,GPR0(r1)
|
|
|
|
|
REST_8GPRS(4, r1)
|
|
|
|
|
ld r12,GPR12(r1)
|
|
|
|
|
b .Lsyscall_restore_regs_cont
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2015-06-12 09:06:32 +08:00
|
|
|
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
|
2017-06-30 01:49:16 +08:00
|
|
|
.Ltabort_syscall:
|
2015-06-12 09:06:32 +08:00
|
|
|
/* Firstly we need to enable TM in the kernel */
|
|
|
|
|
mfmsr r10
|
2016-07-25 12:26:51 +08:00
|
|
|
li r9, 1
|
|
|
|
|
rldimi r10, r9, MSR_TM_LG, 63-MSR_TM_LG
|
2015-06-12 09:06:32 +08:00
|
|
|
mtmsrd r10, 0
|
|
|
|
|
|
|
|
|
|
/* tabort, this dooms the transaction, nothing else */
|
2016-07-25 12:26:51 +08:00
|
|
|
li r9, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT)
|
|
|
|
|
TABORT(R9)
|
2015-06-12 09:06:32 +08:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Return directly to userspace. We have corrupted user register state,
|
|
|
|
|
* but userspace will never see that register state. Execution will
|
|
|
|
|
* resume after the tbegin of the aborted transaction with the
|
|
|
|
|
* checkpointed register state.
|
|
|
|
|
*/
|
2016-07-25 12:26:51 +08:00
|
|
|
li r9, MSR_RI
|
|
|
|
|
andc r10, r10, r9
|
2015-06-12 09:06:32 +08:00
|
|
|
mtmsrd r10, 1
|
|
|
|
|
mtspr SPRN_SRR0, r11
|
|
|
|
|
mtspr SPRN_SRR1, r12
|
2018-01-10 00:07:15 +08:00
|
|
|
RFI_TO_USER
|
2015-06-12 09:06:32 +08:00
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
#endif
|
|
|
|
|
|
2005-10-10 20:36:14 +08:00
|
|
|
_GLOBAL(ret_from_fork)
|
2014-02-04 13:04:35 +08:00
|
|
|
bl schedule_tail
|
2005-10-10 20:36:14 +08:00
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
li r3,0
|
2014-12-05 18:16:59 +08:00
|
|
|
b .Lsyscall_exit
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2012-09-13 06:32:42 +08:00
|
|
|
_GLOBAL(ret_from_kernel_thread)
|
2014-02-04 13:04:35 +08:00
|
|
|
bl schedule_tail
|
2012-09-13 06:32:42 +08:00
|
|
|
REST_NVGPRS(r1)
|
2020-06-11 20:11:19 +08:00
|
|
|
mtctr r14
|
2012-09-13 06:32:42 +08:00
|
|
|
mr r3,r15
|
2016-06-07 00:56:10 +08:00
|
|
|
#ifdef PPC64_ELF_ABI_v2
|
2014-02-04 13:08:51 +08:00
|
|
|
mr r12,r14
|
|
|
|
|
#endif
|
2020-06-11 20:11:19 +08:00
|
|
|
bctrl
|
2012-09-13 06:32:42 +08:00
|
|
|
li r3,0
|
2014-12-05 18:16:59 +08:00
|
|
|
b .Lsyscall_exit
|
2012-09-01 03:48:05 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
powerpc/64/syscall: Remove non-volatile GPR save optimisation
powerpc has an optimisation where interrupts avoid saving the
non-volatile (or callee saved) registers to the interrupt stack frame
if they are not required.
Two problems with this are that an interrupt does not always know
whether it will need non-volatiles; and if it does need them, they can
only be saved from the entry-scoped asm code (because we don't control
what the C compiler does with these registers).
system calls are the most difficult: some system calls always require
all registers (e.g., fork, to copy regs into the child). Sometimes
registers are only required under certain conditions (e.g., tracing,
signal delivery). These cases require ugly logic in the call
chains (e.g., ppc_fork), and require a lot of logic to be implemented
in asm.
So remove the optimisation for system calls, and always save NVGPRs on
entry. Modern high performance CPUs are not so sensitive, because the
stores are dense in cache and can be hidden by other expensive work in
the syscall path -- the null syscall selftests benchmark on POWER9 is
not slowed (124.40ns before and 123.64ns after, i.e., within the
noise).
Other interrupts retain the NVGPR optimisation for now.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-24-npiggin@gmail.com
2020-02-26 01:35:32 +08:00
|
|
|
/* Save non-volatile GPRs, if not already saved. */
|
|
|
|
|
_GLOBAL(save_nvgprs)
|
|
|
|
|
ld r11,_TRAP(r1)
|
|
|
|
|
andi. r0,r11,1
|
|
|
|
|
beqlr-
|
|
|
|
|
SAVE_NVGPRS(r1)
|
|
|
|
|
clrrdi r0,r11,1
|
|
|
|
|
std r0,_TRAP(r1)
|
|
|
|
|
blr
|
|
|
|
|
_ASM_NOKPROBE_SYMBOL(save_nvgprs);
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
#endif
|
powerpc/64/syscall: Remove non-volatile GPR save optimisation
powerpc has an optimisation where interrupts avoid saving the
non-volatile (or callee saved) registers to the interrupt stack frame
if they are not required.
Two problems with this are that an interrupt does not always know
whether it will need non-volatiles; and if it does need them, they can
only be saved from the entry-scoped asm code (because we don't control
what the C compiler does with these registers).
system calls are the most difficult: some system calls always require
all registers (e.g., fork, to copy regs into the child). Sometimes
registers are only required under certain conditions (e.g., tracing,
signal delivery). These cases require ugly logic in the call
chains (e.g., ppc_fork), and require a lot of logic to be implemented
in asm.
So remove the optimisation for system calls, and always save NVGPRs on
entry. Modern high performance CPUs are not so sensitive, because the
stores are dense in cache and can be hidden by other expensive work in
the syscall path -- the null syscall selftests benchmark on POWER9 is
not slowed (124.40ns before and 123.64ns after, i.e., within the
noise).
Other interrupts retain the NVGPR optimisation for now.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-24-npiggin@gmail.com
2020-02-26 01:35:32 +08:00
|
|
|
|
2018-07-23 23:07:54 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
|
|
|
|
|
#define FLUSH_COUNT_CACHE \
|
|
|
|
|
1: nop; \
|
2020-06-09 15:06:04 +08:00
|
|
|
patch_site 1b, patch__call_flush_branch_caches
|
2018-07-23 23:07:54 +08:00
|
|
|
|
|
|
|
|
.macro nops number
|
|
|
|
|
.rept \number
|
|
|
|
|
nop
|
|
|
|
|
.endr
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.balign 32
|
2020-06-09 15:06:04 +08:00
|
|
|
.global flush_branch_caches
|
|
|
|
|
flush_branch_caches:
|
2018-07-23 23:07:54 +08:00
|
|
|
/* Save LR into r9 */
|
|
|
|
|
mflr r9
|
|
|
|
|
|
2019-11-13 18:05:41 +08:00
|
|
|
// Flush the link stack
|
2018-07-23 23:07:54 +08:00
|
|
|
.rept 64
|
|
|
|
|
bl .+4
|
|
|
|
|
.endr
|
|
|
|
|
b 1f
|
|
|
|
|
nops 6
|
|
|
|
|
|
|
|
|
|
.balign 32
|
|
|
|
|
/* Restore LR */
|
|
|
|
|
1: mtlr r9
|
2019-11-13 18:05:41 +08:00
|
|
|
|
|
|
|
|
// If we're just flushing the link stack, return here
|
|
|
|
|
3: nop
|
|
|
|
|
patch_site 3b patch__flush_link_stack_return
|
|
|
|
|
|
2018-07-23 23:07:54 +08:00
|
|
|
li r9,0x7fff
|
|
|
|
|
mtctr r9
|
|
|
|
|
|
2020-06-09 15:06:08 +08:00
|
|
|
PPC_BCCTR_FLUSH
|
2018-07-23 23:07:54 +08:00
|
|
|
|
|
|
|
|
2: nop
|
|
|
|
|
patch_site 2b patch__flush_count_cache_return
|
|
|
|
|
|
|
|
|
|
nops 3
|
|
|
|
|
|
|
|
|
|
.rept 278
|
|
|
|
|
.balign 32
|
2020-06-09 15:06:08 +08:00
|
|
|
PPC_BCCTR_FLUSH
|
2018-07-23 23:07:54 +08:00
|
|
|
nops 7
|
|
|
|
|
.endr
|
|
|
|
|
|
|
|
|
|
blr
|
|
|
|
|
#else
|
|
|
|
|
#define FLUSH_COUNT_CACHE
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3S_64 */
|
|
|
|
|
|
2005-10-10 20:36:14 +08:00
|
|
|
/*
|
|
|
|
|
* This routine switches between two different tasks. The process
|
|
|
|
|
* state of one is saved on its kernel stack. Then the state
|
|
|
|
|
* of the other is restored from its kernel stack. The memory
|
|
|
|
|
* management hardware is updated to the second process's state.
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
* Finally, we can return to the second process, via interrupt_return.
|
2005-10-10 20:36:14 +08:00
|
|
|
* On entry, r3 points to the THREAD for the current task, r4
|
|
|
|
|
* points to the THREAD for the new task.
|
|
|
|
|
*
|
|
|
|
|
* Note: there are two ways to get to the "going out" portion
|
|
|
|
|
* of this code; either by coming in via the entry (_switch)
|
|
|
|
|
* or via "fork" which must set up an environment equivalent
|
|
|
|
|
* to the "_switch" path. If you change this you'll have to change
|
|
|
|
|
* the fork code also.
|
|
|
|
|
*
|
|
|
|
|
* The code which creates the new task context is in 'copy_thread'
|
2006-01-24 00:58:20 +08:00
|
|
|
* in arch/powerpc/kernel/process.c
|
2005-10-10 20:36:14 +08:00
|
|
|
*/
|
|
|
|
|
.align 7
|
|
|
|
|
_GLOBAL(_switch)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
|
|
|
|
stdu r1,-SWITCH_FRAME_SIZE(r1)
|
|
|
|
|
/* r3-r13 are caller saved -- Cort */
|
2019-12-11 10:35:52 +08:00
|
|
|
SAVE_NVGPRS(r1)
|
2015-10-29 08:43:56 +08:00
|
|
|
std r0,_NIP(r1) /* Return to switch caller */
|
2005-10-10 20:36:14 +08:00
|
|
|
mfcr r23
|
|
|
|
|
std r23,_CCR(r1)
|
|
|
|
|
std r1,KSP(r3) /* Set old stack pointer */
|
|
|
|
|
|
2019-04-18 14:51:24 +08:00
|
|
|
kuap_check_amr r9, r10
|
|
|
|
|
|
2018-07-23 23:07:54 +08:00
|
|
|
FLUSH_COUNT_CACHE
|
|
|
|
|
|
2017-06-08 23:36:08 +08:00
|
|
|
/*
|
|
|
|
|
* On SMP kernels, care must be taken because a task may be
|
|
|
|
|
* scheduled off CPUx and on to CPUy. Memory ordering must be
|
|
|
|
|
* considered.
|
|
|
|
|
*
|
|
|
|
|
* Cacheable stores on CPUx will be visible when the task is
|
|
|
|
|
* scheduled on CPUy by virtue of the core scheduler barriers
|
|
|
|
|
* (see "Notes on Program-Order guarantees on SMP systems." in
|
|
|
|
|
* kernel/sched/core.c).
|
|
|
|
|
*
|
|
|
|
|
* Uncacheable stores in the case of involuntary preemption must
|
|
|
|
|
* be taken care of. The smp_mb__before_spin_lock() in __schedule()
|
|
|
|
|
* is implemented as hwsync on powerpc, which orders MMIO too. So
|
|
|
|
|
* long as there is an hwsync in the context switch path, it will
|
|
|
|
|
* be executed on the source CPU after the task has performed
|
|
|
|
|
* all MMIO ops on that CPU, and on the destination CPU before the
|
|
|
|
|
* task performs any MMIO ops there.
|
2005-10-10 20:36:14 +08:00
|
|
|
*/
|
|
|
|
|
|
2010-08-11 09:40:27 +08:00
|
|
|
/*
|
2017-06-08 23:36:07 +08:00
|
|
|
* The kernel context switch path must contain a spin_lock,
|
|
|
|
|
* which contains larx/stcx, which will clear any reservation
|
|
|
|
|
* of the task being switched.
|
2010-08-11 09:40:27 +08:00
|
|
|
*/
|
2013-05-30 03:34:27 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
|
|
|
|
/* Cancel all explict user streams as they will have no use after context
|
|
|
|
|
* switch and will stop the HW from creating streams itself
|
|
|
|
|
*/
|
2018-02-21 03:08:26 +08:00
|
|
|
DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r6)
|
2013-05-30 03:34:27 +08:00
|
|
|
#endif
|
|
|
|
|
|
2005-10-10 20:36:14 +08:00
|
|
|
addi r6,r4,-THREAD /* Convert THREAD to 'current' */
|
|
|
|
|
std r6,PACACURRENT(r13) /* Set new 'current' */
|
2018-09-27 15:05:55 +08:00
|
|
|
#if defined(CONFIG_STACKPROTECTOR)
|
|
|
|
|
ld r6, TASK_CANARY(r6)
|
|
|
|
|
std r6, PACA_CANARY(r13)
|
|
|
|
|
#endif
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
ld r8,KSP(r4) /* new stack pointer */
|
2017-10-19 12:08:43 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
2016-04-29 21:26:07 +08:00
|
|
|
BEGIN_MMU_FTR_SECTION
|
|
|
|
|
b 2f
|
2016-07-27 11:19:01 +08:00
|
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
|
2007-10-11 18:37:10 +08:00
|
|
|
BEGIN_FTR_SECTION
|
2005-10-10 20:36:14 +08:00
|
|
|
clrrdi r6,r8,28 /* get its ESID */
|
|
|
|
|
clrrdi r9,r1,28 /* get current sp ESID */
|
2014-07-10 10:29:20 +08:00
|
|
|
FTR_SECTION_ELSE
|
2007-10-11 18:37:10 +08:00
|
|
|
clrrdi r6,r8,40 /* get its 1T ESID */
|
|
|
|
|
clrrdi r9,r1,40 /* get current sp 1T ESID */
|
2014-07-10 10:29:20 +08:00
|
|
|
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
|
2005-10-10 20:36:14 +08:00
|
|
|
clrldi. r0,r6,2 /* is new ESID c00000000? */
|
|
|
|
|
cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
|
|
|
|
|
cror eq,4*cr1+eq,eq
|
|
|
|
|
beq 2f /* if yes, don't slbie it */
|
|
|
|
|
|
|
|
|
|
/* Bolt in the new stack SLB entry */
|
|
|
|
|
ld r7,KSP_VSID(r4) /* Get new stack's VSID */
|
|
|
|
|
oris r0,r6,(SLB_ESID_V)@h
|
|
|
|
|
ori r0,r0,(SLB_NUM_BOLTED-1)@l
|
2007-10-11 18:37:10 +08:00
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
li r9,MMU_SEGSIZE_1T /* insert B field */
|
|
|
|
|
oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
|
|
|
|
|
rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
|
2011-04-07 03:48:50 +08:00
|
|
|
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
|
2006-08-07 14:19:19 +08:00
|
|
|
|
2007-08-24 14:58:37 +08:00
|
|
|
/* Update the last bolted SLB. No write barriers are needed
|
|
|
|
|
* here, provided we only update the current CPU's SLB shadow
|
|
|
|
|
* buffer.
|
|
|
|
|
*/
|
2006-08-07 14:19:19 +08:00
|
|
|
ld r9,PACA_SLBSHADOWPTR(r13)
|
2006-08-09 15:00:30 +08:00
|
|
|
li r12,0
|
2013-08-07 00:01:46 +08:00
|
|
|
std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
|
|
|
|
|
li r12,SLBSHADOW_STACKVSID
|
|
|
|
|
STDX_BE r7,r12,r9 /* Save VSID */
|
|
|
|
|
li r12,SLBSHADOW_STACKESID
|
|
|
|
|
STDX_BE r0,r12,r9 /* Save ESID */
|
2006-08-07 14:19:19 +08:00
|
|
|
|
2011-04-07 03:48:50 +08:00
|
|
|
/* No need to check for MMU_FTR_NO_SLBIE_B here, since when
|
2007-10-15 22:58:59 +08:00
|
|
|
* we have 1TB segments, the only CPUs known to have the errata
|
|
|
|
|
* only support less than 1TB of system memory and we'll never
|
|
|
|
|
* actually hit this code path.
|
|
|
|
|
*/
|
|
|
|
|
|
powerpc/mm/hash: Add missing isync prior to kernel stack SLB switch
Currently we do not have an isync, or any other context synchronizing
instruction prior to the slbie/slbmte in _switch() that updates the
SLB entry for the kernel stack.
However that is not correct as outlined in the ISA.
From Power ISA Version 3.0B, Book III, Chapter 11, page 1133:
"Changing the contents of ... the contents of SLB entries ... can
have the side effect of altering the context in which data
addresses and instruction addresses are interpreted, and in which
instructions are executed and data accesses are performed.
...
These side effects need not occur in program order, and therefore
may require explicit synchronization by software.
...
The synchronizing instruction before the context-altering
instruction ensures that all instructions up to and including that
synchronizing instruction are fetched and executed in the context
that existed before the alteration."
And page 1136:
"For data accesses, the context synchronizing instruction before the
slbie, slbieg, slbia, slbmte, tlbie, or tlbiel instruction ensures
that all preceding instructions that access data storage have
completed to a point at which they have reported all exceptions
they will cause."
We're not aware of any bugs caused by this, but it should be fixed
regardless.
Add the missing isync when updating kernel stack SLB entry.
Cc: stable@vger.kernel.org
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
[mpe: Flesh out change log with more ISA text & explanation]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-05-30 21:18:04 +08:00
|
|
|
isync
|
2005-10-10 20:36:14 +08:00
|
|
|
slbie r6
|
2018-09-14 23:30:46 +08:00
|
|
|
BEGIN_FTR_SECTION
|
2005-10-10 20:36:14 +08:00
|
|
|
slbie r6 /* Workaround POWER5 < DD2.1 issue */
|
2018-09-14 23:30:46 +08:00
|
|
|
END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
|
2005-10-10 20:36:14 +08:00
|
|
|
slbmte r7,r0
|
|
|
|
|
isync
|
|
|
|
|
2:
|
2017-10-19 12:08:43 +08:00
|
|
|
#endif /* CONFIG_PPC_BOOK3S_64 */
|
2009-07-24 07:15:59 +08:00
|
|
|
|
2019-01-17 20:23:57 +08:00
|
|
|
clrrdi r7, r8, THREAD_SHIFT /* base of new stack */
|
2005-10-10 20:36:14 +08:00
|
|
|
/* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
|
|
|
|
|
because we don't need to leave the 288-byte ABI gap at the
|
|
|
|
|
top of the kernel stack. */
|
|
|
|
|
addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
|
|
|
|
|
|
2017-06-08 23:36:06 +08:00
|
|
|
/*
|
|
|
|
|
* PMU interrupts in radix may come in here. They will use r1, not
|
|
|
|
|
* PACAKSAVE, so this stack switch will not cause a problem. They
|
|
|
|
|
* will store to the process stack, which may then be migrated to
|
|
|
|
|
* another CPU. However the rq lock release on this CPU paired with
|
|
|
|
|
* the rq lock acquire on the new CPU before the stack becomes
|
|
|
|
|
* active on the new CPU, will order those stores.
|
|
|
|
|
*/
|
2005-10-10 20:36:14 +08:00
|
|
|
mr r1,r8 /* start using new stack pointer */
|
|
|
|
|
std r7,PACAKSAVE(r13)
|
|
|
|
|
|
2012-09-04 00:51:10 +08:00
|
|
|
ld r6,_CCR(r1)
|
|
|
|
|
mtcrf 0xFF,r6
|
|
|
|
|
|
2005-10-10 20:36:14 +08:00
|
|
|
/* r3-r13 are destroyed -- Cort */
|
2019-12-11 10:35:52 +08:00
|
|
|
REST_NVGPRS(r1)
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
/* convert old thread to its task_struct for return value */
|
|
|
|
|
addi r3,r3,-THREAD
|
|
|
|
|
ld r7,_NIP(r1) /* Return to _switch caller in new task */
|
|
|
|
|
mtlr r7
|
|
|
|
|
addi r1,r1,SWITCH_FRAME_SIZE
|
|
|
|
|
blr
|
|
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3S
|
2005-10-10 20:36:14 +08:00
|
|
|
/*
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
* If MSR EE/RI was never enabled, IRQs not reconciled, NVGPRs not
|
2020-04-29 14:56:53 +08:00
|
|
|
* touched, no exit work created, then this can be used.
|
2005-10-10 20:36:14 +08:00
|
|
|
*/
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
.balign IFETCH_ALIGN_BYTES
|
|
|
|
|
.globl fast_interrupt_return
|
|
|
|
|
fast_interrupt_return:
|
|
|
|
|
_ASM_NOKPROBE_SYMBOL(fast_interrupt_return)
|
2020-04-29 14:56:53 +08:00
|
|
|
kuap_check_amr r3, r4
|
2020-04-29 14:56:54 +08:00
|
|
|
ld r5,_MSR(r1)
|
|
|
|
|
andi. r0,r5,MSR_PR
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
bne .Lfast_user_interrupt_return
|
2020-04-29 14:56:54 +08:00
|
|
|
kuap_restore_amr r3, r4
|
|
|
|
|
andi. r0,r5,MSR_RI
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
li r3,0 /* 0 return value, no EMULATE_STACK_STORE */
|
|
|
|
|
bne+ .Lfast_kernel_interrupt_return
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
bl unrecoverable_exception
|
|
|
|
|
b . /* should not get here */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
.balign IFETCH_ALIGN_BYTES
|
|
|
|
|
.globl interrupt_return
|
|
|
|
|
interrupt_return:
|
|
|
|
|
_ASM_NOKPROBE_SYMBOL(interrupt_return)
|
|
|
|
|
ld r4,_MSR(r1)
|
|
|
|
|
andi. r0,r4,MSR_PR
|
|
|
|
|
beq .Lkernel_interrupt_return
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-07 04:56:43 +08:00
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
bl interrupt_exit_user_prepare
|
|
|
|
|
cmpdi r3,0
|
|
|
|
|
bne- .Lrestore_nvgprs
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-07 04:56:43 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
.Lfast_user_interrupt_return:
|
|
|
|
|
ld r11,_NIP(r1)
|
|
|
|
|
ld r12,_MSR(r1)
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
ld r10,_PPR(r1)
|
|
|
|
|
mtspr SPRN_PPR,r10
|
|
|
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
|
|
|
|
|
mtspr SPRN_SRR0,r11
|
|
|
|
|
mtspr SPRN_SRR1,r12
|
2012-09-17 07:54:30 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
stdcx. r0,0,r1 /* to clear the reservation */
|
|
|
|
|
FTR_SECTION_ELSE
|
|
|
|
|
ldarx r0,0,r1
|
|
|
|
|
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
|
2012-09-17 07:54:30 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
ld r3,_CCR(r1)
|
|
|
|
|
ld r4,_LINK(r1)
|
|
|
|
|
ld r5,_CTR(r1)
|
|
|
|
|
ld r6,_XER(r1)
|
|
|
|
|
li r0,0
|
2012-09-17 07:54:30 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
REST_4GPRS(7, r1)
|
|
|
|
|
REST_2GPRS(11, r1)
|
|
|
|
|
REST_GPR(13, r1)
|
ppc64: fix missing to check all bits of _TIF_USER_WORK_MASK in preempt
In entry_64.S version of ret_from_except_lite, you'll notice that
in the !preempt case, after we've checked MSR_PR we test for any
TIF flag in _TIF_USER_WORK_MASK to decide whether to go to do_work
or not. However, in the preempt case, we do a convoluted trick to
test SIGPENDING only if PR was set and always test NEED_RESCHED ...
but we forget to test any other bit of _TIF_USER_WORK_MASK !!! So
that means that with preempt, we completely fail to test for things
like single step, syscall tracing, etc...
This should be fixed as the following path:
- Test PR. If not set, go to resume_kernel, else continue.
- If go resume_kernel, to do that original do_work.
- If else, then always test for _TIF_USER_WORK_MASK to decide to do
that original user_work, else restore directly.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2012-06-07 04:56:43 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
mtcr r3
|
|
|
|
|
mtlr r4
|
|
|
|
|
mtctr r5
|
|
|
|
|
mtspr SPRN_XER,r6
|
2013-01-06 08:49:34 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
REST_4GPRS(2, r1)
|
|
|
|
|
REST_GPR(6, r1)
|
|
|
|
|
REST_GPR(0, r1)
|
|
|
|
|
REST_GPR(1, r1)
|
|
|
|
|
RFI_TO_USER
|
|
|
|
|
b . /* prevent speculative execution */
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 15:27:59 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
.Lrestore_nvgprs:
|
|
|
|
|
REST_NVGPRS(r1)
|
|
|
|
|
b .Lfast_user_interrupt_return
|
2005-10-10 20:36:14 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
.balign IFETCH_ALIGN_BYTES
|
|
|
|
|
.Lkernel_interrupt_return:
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
bl interrupt_exit_kernel_prepare
|
2007-02-07 10:13:26 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
.Lfast_kernel_interrupt_return:
|
|
|
|
|
cmpdi cr1,r3,0
|
|
|
|
|
ld r11,_NIP(r1)
|
|
|
|
|
ld r12,_MSR(r1)
|
|
|
|
|
mtspr SPRN_SRR0,r11
|
|
|
|
|
mtspr SPRN_SRR1,r12
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 15:27:59 +08:00
|
|
|
|
|
|
|
|
BEGIN_FTR_SECTION
|
|
|
|
|
stdcx. r0,0,r1 /* to clear the reservation */
|
|
|
|
|
FTR_SECTION_ELSE
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
ldarx r0,0,r1
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 15:27:59 +08:00
|
|
|
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
|
|
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
ld r3,_LINK(r1)
|
2007-02-07 10:13:26 +08:00
|
|
|
ld r4,_CTR(r1)
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
ld r5,_XER(r1)
|
|
|
|
|
ld r6,_CCR(r1)
|
|
|
|
|
li r0,0
|
2005-10-10 20:36:14 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
REST_4GPRS(7, r1)
|
|
|
|
|
REST_2GPRS(11, r1)
|
2018-01-10 00:07:15 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
mtlr r3
|
|
|
|
|
mtctr r4
|
|
|
|
|
mtspr SPRN_XER,r5
|
2005-10-10 20:36:14 +08:00
|
|
|
|
powerpc/64s: Clear on-stack exception marker upon exception return
The ppc64 specific implementation of the reliable stacktracer,
save_stack_trace_tsk_reliable(), bails out and reports an "unreliable
trace" whenever it finds an exception frame on the stack. Stack frames
are classified as exception frames if the STACK_FRAME_REGS_MARKER
magic, as written by exception prologues, is found at a particular
location.
However, as observed by Joe Lawrence, it is possible in practice that
non-exception stack frames can alias with prior exception frames and
thus, that the reliable stacktracer can find a stale
STACK_FRAME_REGS_MARKER on the stack. It in turn falsely reports an
unreliable stacktrace and blocks any live patching transition to
finish. Said condition lasts until the stack frame is
overwritten/initialized by function call or other means.
In principle, we could mitigate this by making the exception frame
classification condition in save_stack_trace_tsk_reliable() stronger:
in addition to testing for STACK_FRAME_REGS_MARKER, we could also take
into account that for all exceptions executing on the kernel stack
- their stack frames's backlink pointers always match what is saved
in their pt_regs instance's ->gpr[1] slot and that
- their exception frame size equals STACK_INT_FRAME_SIZE, a value
uncommonly large for non-exception frames.
However, while these are currently true, relying on them would make
the reliable stacktrace implementation more sensitive towards future
changes in the exception entry code. Note that false negatives, i.e.
not detecting exception frames, would silently break the live patching
consistency model.
Furthermore, certain other places (diagnostic stacktraces, perf, xmon)
rely on STACK_FRAME_REGS_MARKER as well.
Make the exception exit code clear the on-stack
STACK_FRAME_REGS_MARKER for those exceptions running on the "normal"
kernel stack and returning to kernelspace: because the topmost frame
is ignored by the reliable stack tracer anyway, returns to userspace
don't need to take care of clearing the marker.
Furthermore, as I don't have the ability to test this on Book 3E or 32
bits, limit the change to Book 3S and 64 bits.
Fixes: df78d3f61480 ("powerpc/livepatch: Implement reliable stack tracing for the consistency model")
Reported-by: Joe Lawrence <joe.lawrence@redhat.com>
Signed-off-by: Nicolai Stange <nstange@suse.de>
Signed-off-by: Joe Lawrence <joe.lawrence@redhat.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2019-01-22 23:57:21 +08:00
|
|
|
/*
|
|
|
|
|
* Leaving a stale exception_marker on the stack can confuse
|
|
|
|
|
* the reliable stack unwinder later on. Clear it.
|
|
|
|
|
*/
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
std r0,STACK_FRAME_OVERHEAD-16(r1)
|
2019-04-18 14:51:24 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
REST_4GPRS(2, r1)
|
2019-04-18 14:51:24 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
bne- cr1,1f /* emulate stack store */
|
|
|
|
|
mtcr r6
|
|
|
|
|
REST_GPR(6, r1)
|
|
|
|
|
REST_GPR(0, r1)
|
|
|
|
|
REST_GPR(1, r1)
|
2018-01-10 00:07:15 +08:00
|
|
|
RFI_TO_KERNEL
|
2005-10-10 20:36:14 +08:00
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
1: /*
|
|
|
|
|
* Emulate stack store with update. New r1 value was already calculated
|
|
|
|
|
* and updated in our interrupt regs by emulate_loadstore, but we can't
|
|
|
|
|
* store the previous value of r1 to the stack before re-loading our
|
|
|
|
|
* registers from it, otherwise they could be clobbered. Use
|
|
|
|
|
* PACA_EXGEN as temporary storage to hold the store data, as
|
|
|
|
|
* interrupts are disabled here so it won't be clobbered.
|
2012-05-11 00:12:38 +08:00
|
|
|
*/
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
mtcr r6
|
|
|
|
|
std r9,PACA_EXGEN+0(r13)
|
|
|
|
|
addi r9,r1,INT_FRAME_SIZE /* get original r1 */
|
|
|
|
|
REST_GPR(6, r1)
|
|
|
|
|
REST_GPR(0, r1)
|
|
|
|
|
REST_GPR(1, r1)
|
|
|
|
|
std r9,0(r1) /* perform store component of stdu */
|
|
|
|
|
ld r9,PACA_EXGEN+0(r13)
|
2017-06-30 01:49:19 +08:00
|
|
|
|
powerpc/64s: Implement interrupt exit logic in C
Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack
store.
The stack store emulation is significantly simplfied, rather than
creating a new return frame and switching to that before performing
the store, it uses the PACA to keep a scratch register around to
perform the store.
The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.
This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.
mpe: Includes fixes from Nick for _TIF_EMULATE_STACK_STORE
handling (including the fast_interrupt_return path), to remove
trace_hardirqs_on(), and fixes the interrupt-return part of the
MSR_VSX restore bug caught by tm-unavailable selftest.
mpe: Incorporate fix from Nick:
The return-to-kernel path has to replay any soft-pending interrupts if
it is returning to a context that had interrupts soft-enabled. It has
to do this carefully and avoid plain enabling interrupts if this is an
irq context, which can cause multiple nesting of interrupts on the
stack, and other unexpected issues.
The code which avoided this case got the soft-mask state wrong, and
marked interrupts as enabled before going around again to retry. This
seems to be mostly harmless except when PREEMPT=y, this calls
preempt_schedule_irq with irqs apparently enabled and runs into a BUG
in kernel/sched/core.c
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200225173541.1549955-29-npiggin@gmail.com
2020-02-26 01:35:37 +08:00
|
|
|
RFI_TO_KERNEL
|
|
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
#endif /* CONFIG_PPC_BOOK3S */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_RTAS
|
|
|
|
|
/*
|
|
|
|
|
* On CHRP, the Run-Time Abstraction Services (RTAS) have to be
|
|
|
|
|
* called with the MMU off.
|
|
|
|
|
*
|
|
|
|
|
* In addition, we need to be in 32b mode, at least for now.
|
|
|
|
|
*
|
|
|
|
|
* Note: r3 is an input parameter to rtas, so don't trash it...
|
|
|
|
|
*/
|
|
|
|
|
_GLOBAL(enter_rtas)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
2018-10-12 10:44:06 +08:00
|
|
|
stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space. */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
/* Because RTAS is running in 32b mode, it clobbers the high order half
|
|
|
|
|
* of all registers that it saves. We therefore save those registers
|
|
|
|
|
* RTAS might touch to the stack. (r0, r3-r13 are caller saved)
|
|
|
|
|
*/
|
|
|
|
|
SAVE_GPR(2, r1) /* Save the TOC */
|
|
|
|
|
SAVE_GPR(13, r1) /* Save paca */
|
2019-12-11 10:35:52 +08:00
|
|
|
SAVE_NVGPRS(r1) /* Save the non-volatiles */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
mfcr r4
|
|
|
|
|
std r4,_CCR(r1)
|
|
|
|
|
mfctr r5
|
|
|
|
|
std r5,_CTR(r1)
|
|
|
|
|
mfspr r6,SPRN_XER
|
|
|
|
|
std r6,_XER(r1)
|
|
|
|
|
mfdar r7
|
|
|
|
|
std r7,_DAR(r1)
|
|
|
|
|
mfdsisr r8
|
|
|
|
|
std r8,_DSISR(r1)
|
|
|
|
|
|
2006-03-28 07:20:00 +08:00
|
|
|
/* Temporary workaround to clear CR until RTAS can be modified to
|
|
|
|
|
* ignore all bits.
|
|
|
|
|
*/
|
|
|
|
|
li r0,0
|
|
|
|
|
mtcr r0
|
|
|
|
|
|
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 11:55:49 +08:00
|
|
|
#ifdef CONFIG_BUG
|
2005-10-10 20:36:14 +08:00
|
|
|
/* There is no way it is acceptable to get here with interrupts enabled,
|
|
|
|
|
* check it with the asm equivalent of WARN_ON
|
|
|
|
|
*/
|
2017-12-20 11:55:50 +08:00
|
|
|
lbz r0,PACAIRQSOFTMASK(r13)
|
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 11:55:49 +08:00
|
|
|
1: tdeqi r0,IRQS_ENABLED
|
2007-01-02 02:45:34 +08:00
|
|
|
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING
|
|
|
|
|
#endif
|
powerpc/64: Change soft_enabled from flag to bitmask
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabled MSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts as
enabled. arch_local_irq_disable() will toggle the value when
interrupts needs to disbled. At this point, the interrupts are not
actually disabled, instead, interrupt vector has code to check for the
flag and mask it when it occurs. By "mask it", it update interrupt
paca->irq_happened and return. arch_local_irq_restore() is called to
re-enable interrupts, which checks and replays interrupts if any
occured.
Now, as mentioned, current logic doesnot mask "performance monitoring
interrupts" and PMIs are implemented as NMI. But this patchset depends
on local_irq_* for a successful local_* update. Meaning, mask all
possible interrupts during local_* update and replay them after the
update.
So the idea here is to reserve the "paca->soft_enabled" logic. New
values and details:
soft_enabled MSR[EE]
1 0 Disabled (PMI and HMI not masked)
0 1 Enabled
Reason for the this change is to create foundation for a third mask
value "0x2" for "soft_enabled" to add support to mask PMIs. When
->soft_enabled is set to a value "3", PMI interrupts are mask and when
set to a value of "1", PMI are not mask. With this patch also extends
soft_enabled as interrupt disable mask.
Current flags are renamed from IRQ_[EN?DIS}ABLED to
IRQS_ENABLED and IRQS_DISABLED.
Patch also fixes the ptrace call to force the user to see the softe
value to be alway 1. Reason being, even though userspace has no
business knowing about softe, it is part of pt_regs. Like-wise in
signal context.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-12-20 11:55:49 +08:00
|
|
|
|
[POWERPC] Lazy interrupt disabling for 64-bit machines
This implements a lazy strategy for disabling interrupts. This means
that local_irq_disable() et al. just clear the 'interrupts are
enabled' flag in the paca. If an interrupt comes along, the interrupt
entry code notices that interrupts are supposed to be disabled, and
clears the EE bit in SRR1, clears the 'interrupts are hard-enabled'
flag in the paca, and returns. This means that interrupts only
actually get disabled in the processor when an interrupt comes along.
When interrupts are enabled by local_irq_enable() et al., the code
sets the interrupts-enabled flag in the paca, and then checks whether
interrupts got hard-disabled. If so, it also sets the EE bit in the
MSR to hard-enable the interrupts.
This has the potential to improve performance, and also makes it
easier to make a kernel that can boot on iSeries and on other 64-bit
machines, since this lazy-disable strategy is very similar to the
soft-disable strategy that iSeries already uses.
This version renames paca->proc_enabled to paca->soft_enabled, and
changes a couple of soft-disables in the kexec code to hard-disables,
which should fix the crash that Michael Ellerman saw. This doesn't
yet use a reserved CR field for the soft_enabled and hard_enabled
flags. This applies on top of Stephen Rothwell's patches to make it
possible to build a combined iSeries/other kernel.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2006-10-04 14:47:49 +08:00
|
|
|
/* Hard-disable interrupts */
|
|
|
|
|
mfmsr r6
|
|
|
|
|
rldicl r7,r6,48,1
|
|
|
|
|
rotldi r7,r7,16
|
|
|
|
|
mtmsrd r7,1
|
|
|
|
|
|
2005-10-10 20:36:14 +08:00
|
|
|
/* Unfortunately, the stack pointer and the MSR are also clobbered,
|
|
|
|
|
* so they are saved in the PACA which allows us to restore
|
|
|
|
|
* our original state after RTAS returns.
|
|
|
|
|
*/
|
|
|
|
|
std r1,PACAR1(r13)
|
|
|
|
|
std r6,PACASAVEDMSR(r13)
|
|
|
|
|
|
|
|
|
|
/* Setup our real return addr */
|
2014-02-04 13:04:52 +08:00
|
|
|
LOAD_REG_ADDR(r4,rtas_return_loc)
|
2006-01-13 11:56:25 +08:00
|
|
|
clrldi r4,r4,2 /* convert to realmode address */
|
2005-10-10 20:36:14 +08:00
|
|
|
mtlr r4
|
|
|
|
|
|
|
|
|
|
li r0,0
|
|
|
|
|
ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
|
|
|
|
|
andc r0,r6,r0
|
|
|
|
|
|
|
|
|
|
li r9,1
|
|
|
|
|
rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
|
2013-09-23 10:04:45 +08:00
|
|
|
ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
|
2005-10-10 20:36:14 +08:00
|
|
|
andc r6,r0,r9
|
2017-06-30 01:49:20 +08:00
|
|
|
|
|
|
|
|
__enter_rtas:
|
2005-10-10 20:36:14 +08:00
|
|
|
sync /* disable interrupts so SRR0/1 */
|
|
|
|
|
mtmsrd r0 /* don't get trashed */
|
|
|
|
|
|
2006-01-13 11:56:25 +08:00
|
|
|
LOAD_REG_ADDR(r4, rtas)
|
2005-10-10 20:36:14 +08:00
|
|
|
ld r5,RTASENTRY(r4) /* get the rtas->entry value */
|
|
|
|
|
ld r4,RTASBASE(r4) /* get the rtas->base value */
|
|
|
|
|
|
|
|
|
|
mtspr SPRN_SRR0,r5
|
|
|
|
|
mtspr SPRN_SRR1,r6
|
2018-01-10 00:07:15 +08:00
|
|
|
RFI_TO_KERNEL
|
2005-10-10 20:36:14 +08:00
|
|
|
b . /* prevent speculative execution */
|
|
|
|
|
|
2014-02-04 13:04:52 +08:00
|
|
|
rtas_return_loc:
|
2013-09-23 10:04:45 +08:00
|
|
|
FIXUP_ENDIAN
|
|
|
|
|
|
2017-12-22 19:17:10 +08:00
|
|
|
/*
|
|
|
|
|
* Clear RI and set SF before anything.
|
|
|
|
|
*/
|
|
|
|
|
mfmsr r6
|
|
|
|
|
li r0,MSR_RI
|
|
|
|
|
andc r6,r6,r0
|
|
|
|
|
sldi r0,r0,(MSR_SF_LG - MSR_RI_LG)
|
|
|
|
|
or r6,r6,r0
|
|
|
|
|
sync
|
|
|
|
|
mtmsrd r6
|
|
|
|
|
|
2005-10-10 20:36:14 +08:00
|
|
|
/* relocation is off at this point */
|
2011-01-20 14:50:21 +08:00
|
|
|
GET_PACA(r4)
|
2006-01-13 11:56:25 +08:00
|
|
|
clrldi r4,r4,2 /* convert to realmode address */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2008-08-30 09:41:12 +08:00
|
|
|
bcl 20,31,$+4
|
|
|
|
|
0: mflr r3
|
2014-02-04 13:04:52 +08:00
|
|
|
ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */
|
2008-08-30 09:41:12 +08:00
|
|
|
|
2005-10-10 20:36:14 +08:00
|
|
|
ld r1,PACAR1(r4) /* Restore our SP */
|
|
|
|
|
ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
|
|
|
|
|
|
|
|
|
|
mtspr SPRN_SRR0,r3
|
|
|
|
|
mtspr SPRN_SRR1,r4
|
2018-01-10 00:07:15 +08:00
|
|
|
RFI_TO_KERNEL
|
2005-10-10 20:36:14 +08:00
|
|
|
b . /* prevent speculative execution */
|
2017-06-30 01:49:20 +08:00
|
|
|
_ASM_NOKPROBE_SYMBOL(__enter_rtas)
|
|
|
|
|
_ASM_NOKPROBE_SYMBOL(rtas_return_loc)
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2008-08-30 09:41:12 +08:00
|
|
|
.align 3
|
2017-03-09 13:42:12 +08:00
|
|
|
1: .8byte rtas_restore_regs
|
2008-08-30 09:41:12 +08:00
|
|
|
|
2014-02-04 13:04:52 +08:00
|
|
|
rtas_restore_regs:
|
2005-10-10 20:36:14 +08:00
|
|
|
/* relocation is on at this point */
|
|
|
|
|
REST_GPR(2, r1) /* Restore the TOC */
|
|
|
|
|
REST_GPR(13, r1) /* Restore paca */
|
2019-12-11 10:35:52 +08:00
|
|
|
REST_NVGPRS(r1) /* Restore the non-volatiles */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2011-01-20 14:50:21 +08:00
|
|
|
GET_PACA(r13)
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
ld r4,_CCR(r1)
|
|
|
|
|
mtcr r4
|
|
|
|
|
ld r5,_CTR(r1)
|
|
|
|
|
mtctr r5
|
|
|
|
|
ld r6,_XER(r1)
|
|
|
|
|
mtspr SPRN_XER,r6
|
|
|
|
|
ld r7,_DAR(r1)
|
|
|
|
|
mtdar r7
|
|
|
|
|
ld r8,_DSISR(r1)
|
|
|
|
|
mtdsisr r8
|
|
|
|
|
|
2018-10-12 10:44:06 +08:00
|
|
|
addi r1,r1,SWITCH_FRAME_SIZE /* Unstack our frame */
|
2005-10-10 20:36:14 +08:00
|
|
|
ld r0,16(r1) /* get return address */
|
|
|
|
|
|
|
|
|
|
mtlr r0
|
|
|
|
|
blr /* return to caller */
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_PPC_RTAS */
|
|
|
|
|
|
|
|
|
|
_GLOBAL(enter_prom)
|
|
|
|
|
mflr r0
|
|
|
|
|
std r0,16(r1)
|
2018-10-12 10:44:06 +08:00
|
|
|
stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
/* Because PROM is running in 32b mode, it clobbers the high order half
|
|
|
|
|
* of all registers that it saves. We therefore save those registers
|
|
|
|
|
* PROM might touch to the stack. (r0, r3-r13 are caller saved)
|
|
|
|
|
*/
|
2009-07-24 07:15:07 +08:00
|
|
|
SAVE_GPR(2, r1)
|
2005-10-10 20:36:14 +08:00
|
|
|
SAVE_GPR(13, r1)
|
2019-12-11 10:35:52 +08:00
|
|
|
SAVE_NVGPRS(r1)
|
2009-07-24 07:15:07 +08:00
|
|
|
mfcr r10
|
2005-10-10 20:36:14 +08:00
|
|
|
mfmsr r11
|
2009-07-24 07:15:07 +08:00
|
|
|
std r10,_CCR(r1)
|
2005-10-10 20:36:14 +08:00
|
|
|
std r11,_MSR(r1)
|
|
|
|
|
|
2013-09-23 10:04:45 +08:00
|
|
|
/* Put PROM address in SRR0 */
|
|
|
|
|
mtsrr0 r4
|
|
|
|
|
|
|
|
|
|
/* Setup our trampoline return addr in LR */
|
|
|
|
|
bcl 20,31,$+4
|
|
|
|
|
0: mflr r4
|
|
|
|
|
addi r4,r4,(1f - 0b)
|
|
|
|
|
mtlr r4
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2013-09-23 10:04:45 +08:00
|
|
|
/* Prepare a 32-bit mode big endian MSR
|
2005-10-10 20:36:14 +08:00
|
|
|
*/
|
2009-07-24 07:15:59 +08:00
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
|
|
|
rlwinm r11,r11,0,1,31
|
2013-09-23 10:04:45 +08:00
|
|
|
mtsrr1 r11
|
|
|
|
|
rfi
|
2009-07-24 07:15:59 +08:00
|
|
|
#else /* CONFIG_PPC_BOOK3E */
|
2013-09-23 10:04:45 +08:00
|
|
|
LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE)
|
|
|
|
|
andc r11,r11,r12
|
|
|
|
|
mtsrr1 r11
|
2018-01-10 00:07:15 +08:00
|
|
|
RFI_TO_KERNEL
|
2009-07-24 07:15:59 +08:00
|
|
|
#endif /* CONFIG_PPC_BOOK3E */
|
2005-10-10 20:36:14 +08:00
|
|
|
|
2013-09-23 10:04:45 +08:00
|
|
|
1: /* Return from OF */
|
|
|
|
|
FIXUP_ENDIAN
|
2005-10-10 20:36:14 +08:00
|
|
|
|
|
|
|
|
/* Just make sure that r1 top 32 bits didn't get
|
|
|
|
|
* corrupt by OF
|
|
|
|
|
*/
|
|
|
|
|
rldicl r1,r1,0,32
|
|
|
|
|
|
|
|
|
|
/* Restore the MSR (back to 64 bits) */
|
|
|
|
|
ld r0,_MSR(r1)
|
2009-07-24 07:15:07 +08:00
|
|
|
MTMSRD(r0)
|
2005-10-10 20:36:14 +08:00
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
/* Restore other registers */
|
|
|
|
|
REST_GPR(2, r1)
|
|
|
|
|
REST_GPR(13, r1)
|
2019-12-11 10:35:52 +08:00
|
|
|
REST_NVGPRS(r1)
|
2005-10-10 20:36:14 +08:00
|
|
|
ld r4,_CCR(r1)
|
|
|
|
|
mtcr r4
|
2018-10-12 10:44:06 +08:00
|
|
|
|
|
|
|
|
addi r1,r1,SWITCH_FRAME_SIZE
|
2005-10-10 20:36:14 +08:00
|
|
|
ld r0,16(r1)
|
|
|
|
|
mtlr r0
|
|
|
|
|
blr
|