2015-07-31 17:43:12 +08:00
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/*
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* Copyright (C) 2015 Atmel Corporation,
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* Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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2014-09-07 14:14:29 +08:00
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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2015-07-31 17:43:12 +08:00
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#include "pmc.h"
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#define PERIPHERAL_MAX 64
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#define PERIPHERAL_ID_MIN 2
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#define GENERATED_SOURCE_MAX 6
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#define GENERATED_MAX_DIV 255
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struct clk_generated {
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struct clk_hw hw;
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2014-09-07 14:14:29 +08:00
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struct regmap *regmap;
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2015-07-31 17:43:12 +08:00
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struct clk_range range;
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2014-09-07 14:14:29 +08:00
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spinlock_t *lock;
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2015-07-31 17:43:12 +08:00
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u32 id;
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u32 gckdiv;
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u8 parent_id;
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};
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#define to_clk_generated(hw) \
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container_of(hw, struct clk_generated, hw)
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static int clk_generated_enable(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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2014-09-07 14:14:29 +08:00
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unsigned long flags;
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2015-07-31 17:43:12 +08:00
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pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
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__func__, gck->gckdiv, gck->parent_id);
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2014-09-07 14:14:29 +08:00
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spin_lock_irqsave(gck->lock, flags);
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regmap_write(gck->regmap, AT91_PMC_PCR,
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(gck->id & AT91_PMC_PCR_PID_MASK));
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regmap_update_bits(gck->regmap, AT91_PMC_PCR,
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AT91_PMC_PCR_GCKDIV_MASK | AT91_PMC_PCR_GCKCSS_MASK |
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AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
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AT91_PMC_PCR_GCKCSS(gck->parent_id) |
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AT91_PMC_PCR_CMD |
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AT91_PMC_PCR_GCKDIV(gck->gckdiv) |
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AT91_PMC_PCR_GCKEN);
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spin_unlock_irqrestore(gck->lock, flags);
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2015-07-31 17:43:12 +08:00
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return 0;
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}
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static void clk_generated_disable(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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2014-09-07 14:14:29 +08:00
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unsigned long flags;
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spin_lock_irqsave(gck->lock, flags);
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regmap_write(gck->regmap, AT91_PMC_PCR,
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(gck->id & AT91_PMC_PCR_PID_MASK));
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regmap_update_bits(gck->regmap, AT91_PMC_PCR,
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AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
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AT91_PMC_PCR_CMD);
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spin_unlock_irqrestore(gck->lock, flags);
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2015-07-31 17:43:12 +08:00
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}
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static int clk_generated_is_enabled(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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2014-09-07 14:14:29 +08:00
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unsigned long flags;
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unsigned int status;
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2015-07-31 17:43:12 +08:00
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2014-09-07 14:14:29 +08:00
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spin_lock_irqsave(gck->lock, flags);
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regmap_write(gck->regmap, AT91_PMC_PCR,
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(gck->id & AT91_PMC_PCR_PID_MASK));
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regmap_read(gck->regmap, AT91_PMC_PCR, &status);
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spin_unlock_irqrestore(gck->lock, flags);
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2015-07-31 17:43:12 +08:00
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2014-09-07 14:14:29 +08:00
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return status & AT91_PMC_PCR_GCKEN ? 1 : 0;
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2015-07-31 17:43:12 +08:00
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}
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static unsigned long
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clk_generated_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
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}
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static int clk_generated_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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struct clk_hw *parent = NULL;
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long best_rate = -EINVAL;
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unsigned long tmp_rate, min_rate;
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int best_diff = -1;
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int tmp_diff;
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int i;
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for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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u32 div;
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unsigned long parent_rate;
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parent = clk_hw_get_parent_by_index(hw, i);
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if (!parent)
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continue;
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parent_rate = clk_hw_get_rate(parent);
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min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1);
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if (!parent_rate ||
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(gck->range.max && min_rate > gck->range.max))
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continue;
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for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
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tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
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tmp_diff = abs(req->rate - tmp_rate);
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if (best_diff < 0 || best_diff > tmp_diff) {
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best_rate = tmp_rate;
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best_diff = tmp_diff;
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req->best_parent_rate = parent_rate;
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req->best_parent_hw = parent;
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}
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if (!best_diff || tmp_rate < req->rate)
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break;
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}
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if (!best_diff)
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break;
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}
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pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n",
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__func__, best_rate,
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__clk_get_name((req->best_parent_hw)->clk),
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req->best_parent_rate);
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if (best_rate < 0)
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return best_rate;
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req->rate = best_rate;
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return 0;
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}
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/* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */
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static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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if (index >= clk_hw_get_num_parents(hw))
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return -EINVAL;
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gck->parent_id = index;
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return 0;
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}
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static u8 clk_generated_get_parent(struct clk_hw *hw)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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return gck->parent_id;
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}
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/* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */
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static int clk_generated_set_rate(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_generated *gck = to_clk_generated(hw);
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u32 div;
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if (!rate)
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return -EINVAL;
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if (gck->range.max && rate > gck->range.max)
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return -EINVAL;
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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if (div > GENERATED_MAX_DIV + 1 || !div)
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return -EINVAL;
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gck->gckdiv = div - 1;
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return 0;
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}
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static const struct clk_ops generated_ops = {
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.enable = clk_generated_enable,
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.disable = clk_generated_disable,
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.is_enabled = clk_generated_is_enabled,
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.recalc_rate = clk_generated_recalc_rate,
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.determine_rate = clk_generated_determine_rate,
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.get_parent = clk_generated_get_parent,
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.set_parent = clk_generated_set_parent,
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.set_rate = clk_generated_set_rate,
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};
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/**
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* clk_generated_startup - Initialize a given clock to its default parent and
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* divisor parameter.
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*
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* @gck: Generated clock to set the startup parameters for.
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*
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* Take parameters from the hardware and update local clock configuration
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* accordingly.
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*/
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static void clk_generated_startup(struct clk_generated *gck)
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{
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u32 tmp;
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2014-09-07 14:14:29 +08:00
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unsigned long flags;
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2015-07-31 17:43:12 +08:00
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2014-09-07 14:14:29 +08:00
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spin_lock_irqsave(gck->lock, flags);
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regmap_write(gck->regmap, AT91_PMC_PCR,
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(gck->id & AT91_PMC_PCR_PID_MASK));
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regmap_read(gck->regmap, AT91_PMC_PCR, &tmp);
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spin_unlock_irqrestore(gck->lock, flags);
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2015-07-31 17:43:12 +08:00
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gck->parent_id = (tmp & AT91_PMC_PCR_GCKCSS_MASK)
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>> AT91_PMC_PCR_GCKCSS_OFFSET;
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gck->gckdiv = (tmp & AT91_PMC_PCR_GCKDIV_MASK)
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>> AT91_PMC_PCR_GCKDIV_OFFSET;
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}
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static struct clk * __init
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2014-09-07 14:14:29 +08:00
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at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, const char
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*name, const char **parent_names, u8 num_parents,
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2015-07-31 17:43:12 +08:00
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u8 id, const struct clk_range *range)
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{
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struct clk_generated *gck;
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struct clk *clk = NULL;
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struct clk_init_data init;
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gck = kzalloc(sizeof(*gck), GFP_KERNEL);
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if (!gck)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &generated_ops;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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gck->id = id;
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gck->hw.init = &init;
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2014-09-07 14:14:29 +08:00
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gck->regmap = regmap;
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gck->lock = lock;
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2015-07-31 17:43:12 +08:00
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gck->range = *range;
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clk = clk_register(NULL, &gck->hw);
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if (IS_ERR(clk))
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kfree(gck);
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else
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clk_generated_startup(gck);
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return clk;
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}
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2014-09-07 14:14:29 +08:00
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void __init of_sama5d2_clk_generated_setup(struct device_node *np)
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2015-07-31 17:43:12 +08:00
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{
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int num;
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u32 id;
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const char *name;
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struct clk *clk;
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2016-02-20 09:29:17 +08:00
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unsigned int num_parents;
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2015-07-31 17:43:12 +08:00
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const char *parent_names[GENERATED_SOURCE_MAX];
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struct device_node *gcknp;
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struct clk_range range = CLK_RANGE(0, 0);
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2014-09-07 14:14:29 +08:00
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struct regmap *regmap;
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2015-07-31 17:43:12 +08:00
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num_parents = of_clk_get_parent_count(np);
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2016-02-20 09:29:17 +08:00
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if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
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2015-07-31 17:43:12 +08:00
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return;
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of_clk_parent_fill(np, parent_names, num_parents);
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num = of_get_child_count(np);
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if (!num || num > PERIPHERAL_MAX)
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return;
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2014-09-07 14:14:29 +08:00
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap))
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return;
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2015-07-31 17:43:12 +08:00
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for_each_child_of_node(np, gcknp) {
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if (of_property_read_u32(gcknp, "reg", &id))
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continue;
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if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
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continue;
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if (of_property_read_string(np, "clock-output-names", &name))
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name = gcknp->name;
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of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
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&range);
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2014-09-07 14:14:29 +08:00
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clk = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
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parent_names, num_parents,
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id, &range);
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2015-07-31 17:43:12 +08:00
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if (IS_ERR(clk))
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continue;
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of_clk_add_provider(gcknp, of_clk_src_simple_get, clk);
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}
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}
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2014-09-07 14:14:29 +08:00
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CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
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of_sama5d2_clk_generated_setup);
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