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linux/arch/powerpc/platforms/cell/axon_msi.c

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[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
/*
* Copyright 2007, Michael Ellerman, IBM Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/msi.h>
[POWERPC] Convert axon_msi to an of_platform driver Now that we create of_platform devices earlier on cell, we can make the axon_msi driver an of_platform driver. This makes the code cleaner in several ways, and most importantly means we have a struct device. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
#include <linux/of_platform.h>
[POWERPC] Add debugging trigger to Axon MSI code This adds some debugging code to the Axon MSI driver. It creates a file per MSIC in /sys/kernel/debug/powerpc, which allows the user to trigger a fake MSI interrupt by writing to the file. This can be used to test some of the MSI generation path. In particular, that the MSIC recognises a write to the MSI address, generates an interrupt and writes the MSI packet into the ring buffer. All the code is inside #ifdef DEBUG so it causes no harm unless it's enabled. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-23 12:21:30 +08:00
#include <linux/debugfs.h>
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
#include <linux/slab.h>
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
#include <asm/dcr.h>
#include <asm/machdep.h>
#include <asm/prom.h>
/*
* MSIC registers, specified as offsets from dcr_base
*/
#define MSIC_CTRL_REG 0x0
/* Base Address registers specify FIFO location in BE memory */
#define MSIC_BASE_ADDR_HI_REG 0x3
#define MSIC_BASE_ADDR_LO_REG 0x4
/* Hold the read/write offsets into the FIFO */
#define MSIC_READ_OFFSET_REG 0x5
#define MSIC_WRITE_OFFSET_REG 0x6
/* MSIC control register flags */
#define MSIC_CTRL_ENABLE 0x0001
#define MSIC_CTRL_FIFO_FULL_ENABLE 0x0002
#define MSIC_CTRL_IRQ_ENABLE 0x0008
#define MSIC_CTRL_FULL_STOP_ENABLE 0x0010
/*
* The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
* Currently we're using a 64KB FIFO size.
*/
#define MSIC_FIFO_SIZE_SHIFT 16
#define MSIC_FIFO_SIZE_BYTES (1 << MSIC_FIFO_SIZE_SHIFT)
/*
* To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
* 8-9 of the MSIC control reg.
*/
#define MSIC_CTRL_FIFO_SIZE (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
/*
* We need to mask the read/write offsets to make sure they stay within
* the bounds of the FIFO. Also they should always be 16-byte aligned.
*/
#define MSIC_FIFO_SIZE_MASK ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
/* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
#define MSIC_FIFO_ENTRY_SIZE 0x10
struct axon_msic {
struct irq_host *irq_host;
[POWERPC] Avoid DMA exception when using axon_msi with IOMMU There's a brown-paper-bag bug in axon_msi, we pass the address of our FIFO directly to the hardware, without DMA mapping it. This leads to DMA exceptions if you enable MSI & the IOMMU. The fix is to correctly DMA map the fifo, dma_alloc_coherent() does what we want - and we need to track the virt & phys addresses. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
__le32 *fifo_virt;
dma_addr_t fifo_phys;
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
dcr_host_t dcr_host;
u32 read_offset;
[POWERPC] Add debugging trigger to Axon MSI code This adds some debugging code to the Axon MSI driver. It creates a file per MSIC in /sys/kernel/debug/powerpc, which allows the user to trigger a fake MSI interrupt by writing to the file. This can be used to test some of the MSI generation path. In particular, that the MSIC recognises a write to the MSI address, generates an interrupt and writes the MSI packet into the ring buffer. All the code is inside #ifdef DEBUG so it causes no harm unless it's enabled. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-23 12:21:30 +08:00
#ifdef DEBUG
u32 __iomem *trigger;
#endif
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
};
[POWERPC] Add debugging trigger to Axon MSI code This adds some debugging code to the Axon MSI driver. It creates a file per MSIC in /sys/kernel/debug/powerpc, which allows the user to trigger a fake MSI interrupt by writing to the file. This can be used to test some of the MSI generation path. In particular, that the MSIC recognises a write to the MSI address, generates an interrupt and writes the MSI packet into the ring buffer. All the code is inside #ifdef DEBUG so it causes no harm unless it's enabled. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-23 12:21:30 +08:00
#ifdef DEBUG
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
#else
static inline void axon_msi_debug_setup(struct device_node *dn,
struct axon_msic *msic) { }
#endif
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
{
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
Add dcr_host_t.base in dcr_read()/dcr_write() Now that all users of dcr_read()/dcr_write() add the dcr_host_t.base, we can save them the trouble and do it in dcr_read()/dcr_write(). As some background to why we just went through all this jiggery-pokery, benh sayeth: Initially the goal of the dcr_read/dcr_write routines was to operate like mfdcr/mtdcr which take absolute DCR numbers. The reason is that on 4xx hardware, indirect DCR access is a pain (goes through a table of instructions) and it's useful to have the compiler resolve an absolute DCR inline. We decided that wasn't worth the API bastardisation since most places where absolute DCR values are used are low level 4xx-only code which may as well continue using mfdcr/mtdcr, while the new API is designed for device "instances" that can exist on 4xx and Axon type platforms and may be located at variable DCR offsets. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-15 17:34:36 +08:00
dcr_write(msic->dcr_host, dcr_n, val);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
}
static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
powerpc: Convert to new irq_* function names Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-25 23:45:20 +08:00
struct irq_chip *chip = irq_desc_get_chip(desc);
struct axon_msic *msic = irq_get_handler_data(irq);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
u32 write_offset, msi;
int idx;
powerpc/cell/axon-msi: Retry on missing interrupt The MSI capture logic for the axon bridge can sometimes lose interrupts in case of high DMA and interrupt load, when it signals an MSI interrupt to the MPIC interrupt controller while we are already handling another MSI. Each MSI vector gets written into a FIFO buffer in main memory using DMA, and that DMA access is normally flushed by the actual interrupt packet on the IOIF. An MMIO register in the MSIC holds the position of the last entry in the FIFO buffer that was written. However, reading that position does not flush the DMA, so that we can observe stale data in the buffer. In a stress test, we have observed the DMA to arrive up to 14 microseconds after reading the register. This patch works around this problem by retrying the access to the FIFO buffer. We can reliably detect the conditioning by writing an invalid MSI vector into the FIFO buffer after reading from it, assuming that all MSIs we get are valid. After detecting an invalid MSI vector, we udelay(1) in the interrupt cascade for up to 100 times before giving up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-11-28 17:51:22 +08:00
int retry = 0;
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
Remove msic_dcr_read() in axon_msi.c msic_dcr_read() doesn't really do anything useful, just replace it with direct calls to dcr_read(). Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-10-15 17:34:38 +08:00
write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
/* write_offset doesn't wrap properly, so we have to mask it */
write_offset &= MSIC_FIFO_SIZE_MASK;
powerpc/cell/axon-msi: Retry on missing interrupt The MSI capture logic for the axon bridge can sometimes lose interrupts in case of high DMA and interrupt load, when it signals an MSI interrupt to the MPIC interrupt controller while we are already handling another MSI. Each MSI vector gets written into a FIFO buffer in main memory using DMA, and that DMA access is normally flushed by the actual interrupt packet on the IOIF. An MMIO register in the MSIC holds the position of the last entry in the FIFO buffer that was written. However, reading that position does not flush the DMA, so that we can observe stale data in the buffer. In a stress test, we have observed the DMA to arrive up to 14 microseconds after reading the register. This patch works around this problem by retrying the access to the FIFO buffer. We can reliably detect the conditioning by writing an invalid MSI vector into the FIFO buffer after reading from it, assuming that all MSIs we get are valid. After detecting an invalid MSI vector, we udelay(1) in the interrupt cascade for up to 100 times before giving up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-11-28 17:51:22 +08:00
while (msic->read_offset != write_offset && retry < 100) {
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
idx = msic->read_offset / sizeof(__le32);
[POWERPC] Avoid DMA exception when using axon_msi with IOMMU There's a brown-paper-bag bug in axon_msi, we pass the address of our FIFO directly to the hardware, without DMA mapping it. This leads to DMA exceptions if you enable MSI & the IOMMU. The fix is to correctly DMA map the fifo, dma_alloc_coherent() does what we want - and we need to track the virt & phys addresses. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
msi = le32_to_cpu(msic->fifo_virt[idx]);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
msi &= 0xFFFF;
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: woff %x roff %x msi %x\n",
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
write_offset, msic->read_offset, msi);
powerpc/cell/axon-msi: Retry on missing interrupt The MSI capture logic for the axon bridge can sometimes lose interrupts in case of high DMA and interrupt load, when it signals an MSI interrupt to the MPIC interrupt controller while we are already handling another MSI. Each MSI vector gets written into a FIFO buffer in main memory using DMA, and that DMA access is normally flushed by the actual interrupt packet on the IOIF. An MMIO register in the MSIC holds the position of the last entry in the FIFO buffer that was written. However, reading that position does not flush the DMA, so that we can observe stale data in the buffer. In a stress test, we have observed the DMA to arrive up to 14 microseconds after reading the register. This patch works around this problem by retrying the access to the FIFO buffer. We can reliably detect the conditioning by writing an invalid MSI vector into the FIFO buffer after reading from it, assuming that all MSIs we get are valid. After detecting an invalid MSI vector, we udelay(1) in the interrupt cascade for up to 100 times before giving up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-11-28 17:51:22 +08:00
if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) {
generic_handle_irq(msi);
msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
} else {
/*
* Reading the MSIC_WRITE_OFFSET_REG does not
* reliably flush the outstanding DMA to the
* FIFO buffer. Here we were reading stale
* data, so we need to retry.
*/
udelay(1);
retry++;
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
powerpc/cell/axon-msi: Retry on missing interrupt The MSI capture logic for the axon bridge can sometimes lose interrupts in case of high DMA and interrupt load, when it signals an MSI interrupt to the MPIC interrupt controller while we are already handling another MSI. Each MSI vector gets written into a FIFO buffer in main memory using DMA, and that DMA access is normally flushed by the actual interrupt packet on the IOIF. An MMIO register in the MSIC holds the position of the last entry in the FIFO buffer that was written. However, reading that position does not flush the DMA, so that we can observe stale data in the buffer. In a stress test, we have observed the DMA to arrive up to 14 microseconds after reading the register. This patch works around this problem by retrying the access to the FIFO buffer. We can reliably detect the conditioning by writing an invalid MSI vector into the FIFO buffer after reading from it, assuming that all MSIs we get are valid. After detecting an invalid MSI vector, we udelay(1) in the interrupt cascade for up to 100 times before giving up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-11-28 17:51:22 +08:00
continue;
}
if (retry) {
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: late irq 0x%x, retry %d\n",
powerpc/cell/axon-msi: Retry on missing interrupt The MSI capture logic for the axon bridge can sometimes lose interrupts in case of high DMA and interrupt load, when it signals an MSI interrupt to the MPIC interrupt controller while we are already handling another MSI. Each MSI vector gets written into a FIFO buffer in main memory using DMA, and that DMA access is normally flushed by the actual interrupt packet on the IOIF. An MMIO register in the MSIC holds the position of the last entry in the FIFO buffer that was written. However, reading that position does not flush the DMA, so that we can observe stale data in the buffer. In a stress test, we have observed the DMA to arrive up to 14 microseconds after reading the register. This patch works around this problem by retrying the access to the FIFO buffer. We can reliably detect the conditioning by writing an invalid MSI vector into the FIFO buffer after reading from it, assuming that all MSIs we get are valid. After detecting an invalid MSI vector, we udelay(1) in the interrupt cascade for up to 100 times before giving up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-11-28 17:51:22 +08:00
msi, retry);
retry = 0;
}
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
msic->read_offset &= MSIC_FIFO_SIZE_MASK;
powerpc/cell/axon-msi: Retry on missing interrupt The MSI capture logic for the axon bridge can sometimes lose interrupts in case of high DMA and interrupt load, when it signals an MSI interrupt to the MPIC interrupt controller while we are already handling another MSI. Each MSI vector gets written into a FIFO buffer in main memory using DMA, and that DMA access is normally flushed by the actual interrupt packet on the IOIF. An MMIO register in the MSIC holds the position of the last entry in the FIFO buffer that was written. However, reading that position does not flush the DMA, so that we can observe stale data in the buffer. In a stress test, we have observed the DMA to arrive up to 14 microseconds after reading the register. This patch works around this problem by retrying the access to the FIFO buffer. We can reliably detect the conditioning by writing an invalid MSI vector into the FIFO buffer after reading from it, assuming that all MSIs we get are valid. After detecting an invalid MSI vector, we udelay(1) in the interrupt cascade for up to 100 times before giving up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-11-28 17:51:22 +08:00
}
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
powerpc/cell/axon-msi: Retry on missing interrupt The MSI capture logic for the axon bridge can sometimes lose interrupts in case of high DMA and interrupt load, when it signals an MSI interrupt to the MPIC interrupt controller while we are already handling another MSI. Each MSI vector gets written into a FIFO buffer in main memory using DMA, and that DMA access is normally flushed by the actual interrupt packet on the IOIF. An MMIO register in the MSIC holds the position of the last entry in the FIFO buffer that was written. However, reading that position does not flush the DMA, so that we can observe stale data in the buffer. In a stress test, we have observed the DMA to arrive up to 14 microseconds after reading the register. This patch works around this problem by retrying the access to the FIFO buffer. We can reliably detect the conditioning by writing an invalid MSI vector into the FIFO buffer after reading from it, assuming that all MSIs we get are valid. After detecting an invalid MSI vector, we udelay(1) in the interrupt cascade for up to 100 times before giving up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-11-28 17:51:22 +08:00
if (retry) {
printk(KERN_WARNING "axon_msi: irq timed out\n");
msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
msic->read_offset &= MSIC_FIFO_SIZE_MASK;
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
}
powerpc: platforms/cell irq_data conversion. Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-03-07 21:59:28 +08:00
chip->irq_eoi(&desc->irq_data);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
}
static struct axon_msic *find_msi_translator(struct pci_dev *dev)
{
struct irq_host *irq_host;
struct device_node *dn, *tmp;
const phandle *ph;
struct axon_msic *msic = NULL;
[POWERPC] Make sure to of_node_get() the result of pci_device_to_OF_node() pci_device_to_OF_node() returns the device node attached to a PCI device, but doesn't actually grab a reference - we need to do it ourselves. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-09-17 14:03:45 +08:00
dn = of_node_get(pci_device_to_OF_node(dev));
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
if (!dn) {
dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
return NULL;
}
[POWERPC] Use of_get_next_parent() in platforms/cell/axon_msi.c Replace two open-coded occurences of the of_get_next_parent() logic. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-24 10:08:54 +08:00
for (; dn; dn = of_get_next_parent(dn)) {
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
ph = of_get_property(dn, "msi-translator", NULL);
if (ph)
break;
}
if (!ph) {
dev_dbg(&dev->dev,
"axon_msi: no msi-translator property found\n");
goto out_error;
}
tmp = dn;
dn = of_find_node_by_phandle(*ph);
[POWERPC] Avoid possible extra of_node_put in axon_msi.c I got this warning from gcc: arch/powerpc/platforms/cell/axon_msi.c:118: warning: 'tmp' may be used uninitialized in this function Which turns out to be a false positive, but pointed out that it was possible for the error path in find_msi_translator() to do an extra of_node_put on a node. This fixes it by localising the ref counting a bit. As a side effect, the warning goes away. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-02-05 10:13:15 +08:00
of_node_put(tmp);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
if (!dn) {
dev_dbg(&dev->dev,
"axon_msi: msi-translator doesn't point to a node\n");
goto out_error;
}
irq_host = irq_find_host(dn);
if (!irq_host) {
dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
dn->full_name);
goto out_error;
}
msic = irq_host->host_data;
out_error:
of_node_put(dn);
return msic;
}
static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
{
if (!find_msi_translator(dev))
return -ENODEV;
return 0;
}
static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
{
[POWERPC] Use of_get_next_parent() in platforms/cell/axon_msi.c Replace two open-coded occurences of the of_get_next_parent() logic. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-24 10:08:54 +08:00
struct device_node *dn;
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
struct msi_desc *entry;
int len;
const u32 *prop;
[POWERPC] Make sure to of_node_get() the result of pci_device_to_OF_node() pci_device_to_OF_node() returns the device node attached to a PCI device, but doesn't actually grab a reference - we need to do it ourselves. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-09-17 14:03:45 +08:00
dn = of_node_get(pci_device_to_OF_node(dev));
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
if (!dn) {
dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
return -ENODEV;
}
entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
[POWERPC] Use of_get_next_parent() in platforms/cell/axon_msi.c Replace two open-coded occurences of the of_get_next_parent() logic. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-24 10:08:54 +08:00
for (; dn; dn = of_get_next_parent(dn)) {
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
if (entry->msi_attrib.is_64) {
prop = of_get_property(dn, "msi-address-64", &len);
if (prop)
break;
}
prop = of_get_property(dn, "msi-address-32", &len);
if (prop)
break;
}
if (!prop) {
dev_dbg(&dev->dev,
"axon_msi: no msi-address-(32|64) properties found\n");
return -ENOENT;
}
switch (len) {
case 8:
msg->address_hi = prop[0];
msg->address_lo = prop[1];
break;
case 4:
msg->address_hi = 0;
msg->address_lo = prop[0];
break;
default:
dev_dbg(&dev->dev,
"axon_msi: malformed msi-address-(32|64) property\n");
of_node_put(dn);
return -EINVAL;
}
of_node_put(dn);
return 0;
}
static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
unsigned int virq, rc;
struct msi_desc *entry;
struct msi_msg msg;
struct axon_msic *msic;
msic = find_msi_translator(dev);
if (!msic)
return -ENODEV;
rc = setup_msi_msg_address(dev, &msg);
if (rc)
return rc;
/* We rely on being able to stash a virq in a u16 */
BUILD_BUG_ON(NR_IRQS > 65536);
list_for_each_entry(entry, &dev->msi_list, list) {
virq = irq_create_direct_mapping(msic->irq_host);
if (virq == NO_IRQ) {
dev_warn(&dev->dev,
"axon_msi: virq allocation failed!\n");
return -1;
}
dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
powerpc: Convert to new irq_* function names Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-25 23:45:20 +08:00
irq_set_msi_desc(virq, entry);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
msg.data = virq;
write_msi_msg(virq, &msg);
}
return 0;
}
static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
{
struct msi_desc *entry;
dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
list_for_each_entry(entry, &dev->msi_list, list) {
if (entry->irq == NO_IRQ)
continue;
powerpc: Convert to new irq_* function names Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-25 23:45:20 +08:00
irq_set_msi_desc(entry->irq, NULL);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
irq_dispose_mapping(entry->irq);
}
}
static struct irq_chip msic_irq_chip = {
pci: Convert msi to new irq_chip functions Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Tony Luck <tony.luck@intel.com> Cc: Russell King <linux@arm.linux.org.uk>
2010-09-28 22:46:51 +08:00
.irq_mask = mask_msi_irq,
.irq_unmask = unmask_msi_irq,
.irq_shutdown = mask_msi_irq,
powerpc: Fixup last users of irq_chip->typename The typename member of struct irq_chip was kept for migration purposes and is obsolete since more than 2 years. Fix up the leftovers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linuxppc-dev@ozlabs.org Acked-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-11-19 07:44:21 +08:00
.name = "AXON-MSI",
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
};
static int msic_host_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t hw)
{
powerpc: Convert to new irq_* function names Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-25 23:45:20 +08:00
irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
return 0;
}
static struct irq_host_ops msic_host_ops = {
.map = msic_host_map,
};
dt/powerpc: Eliminate users of of_platform_{,un}register_driver Get rid of old users of of_platform_driver in arch/powerpc. Most of_platform_driver users can be converted to use the platform_bus directly. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-23 10:59:54 +08:00
static void axon_msi_shutdown(struct platform_device *device)
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
{
powerpc/cell: Use driver_data acessors, not platform_data in Axon MSI The Axon MSI driver incorrectly uses platform_data, rather than the proper accessors for driver_data. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-11 03:06:34 +08:00
struct axon_msic *msic = dev_get_drvdata(&device->dev);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
u32 tmp;
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: disabling %s\n",
[POWERPC] Convert axon_msi to an of_platform driver Now that we create of_platform devices earlier on cell, we can make the axon_msi driver an of_platform driver. This makes the code cleaner in several ways, and most importantly means we have a struct device. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
msic->irq_host->of_node->full_name);
tmp = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
}
dt/powerpc: Eliminate users of of_platform_{,un}register_driver Get rid of old users of of_platform_driver in arch/powerpc. Most of_platform_driver users can be converted to use the platform_bus directly. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-23 10:59:54 +08:00
static int axon_msi_probe(struct platform_device *device)
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
{
of: Always use 'struct device.of_node' to get device node pointer. The following structure elements duplicate the information in 'struct device.of_node' and so are being eliminated. This patch makes all readers of these elements use device.of_node instead. (struct of_device *)->node (struct dev_archdata *)->prom_node (sparc) (struct dev_archdata *)->of_node (powerpc & microblaze) Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2010-04-14 07:12:29 +08:00
struct device_node *dn = device->dev.of_node;
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
struct axon_msic *msic;
unsigned int virq;
[POWERPC] Update axon_msi to use dcr_host_t.base Now that dcr_host_t contains the base address, we can use that in the axon_msi code, rather than storing it separately. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-09-17 14:05:02 +08:00
int dcr_base, dcr_len;
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
if (!msic) {
printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
dn->full_name);
goto out;
}
[POWERPC] Update axon_msi to use dcr_host_t.base Now that dcr_host_t contains the base address, we can use that in the axon_msi code, rather than storing it separately. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-09-17 14:05:02 +08:00
dcr_base = dcr_resource_start(dn, 0);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
dcr_len = dcr_resource_len(dn, 0);
[POWERPC] Update axon_msi to use dcr_host_t.base Now that dcr_host_t contains the base address, we can use that in the axon_msi code, rather than storing it separately. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-09-17 14:05:02 +08:00
if (dcr_base == 0 || dcr_len == 0) {
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
printk(KERN_ERR
"axon_msi: couldn't parse dcr properties on %s\n",
dn->full_name);
powerpc: Fix memory leak in axon_msi.c cppcheck found a memory leak in axon_msi, if dcr_base or dcr_len are zero, we have already allocated msic, so we should free it in the error path. Signed-off-by: Eric Sesterhenn <eric.sesterhenn@lsexperts.de> Acked-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-10-12 22:29:40 +08:00
goto out_free_msic;
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
}
[POWERPC] Update axon_msi to use dcr_host_t.base Now that dcr_host_t contains the base address, we can use that in the axon_msi code, rather than storing it separately. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-09-17 14:05:02 +08:00
msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
if (!DCR_MAP_OK(msic->dcr_host)) {
printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
dn->full_name);
goto out_free_msic;
}
[POWERPC] Avoid DMA exception when using axon_msi with IOMMU There's a brown-paper-bag bug in axon_msi, we pass the address of our FIFO directly to the hardware, without DMA mapping it. This leads to DMA exceptions if you enable MSI & the IOMMU. The fix is to correctly DMA map the fifo, dma_alloc_coherent() does what we want - and we need to track the virt & phys addresses. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
&msic->fifo_phys, GFP_KERNEL);
if (!msic->fifo_virt) {
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
dn->full_name);
goto out_free_msic;
}
powerpc: Rework Axon MSI setup so we can avoid freeing the irq_host If we do the call to irq_of_parse_and_map() first, then we don't need to worry about freeing the irq_host. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-26 10:12:30 +08:00
virq = irq_of_parse_and_map(dn, 0);
if (virq == NO_IRQ) {
printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
dn->full_name);
goto out_free_fifo;
}
powerpc/cell/axon-msi: Retry on missing interrupt The MSI capture logic for the axon bridge can sometimes lose interrupts in case of high DMA and interrupt load, when it signals an MSI interrupt to the MPIC interrupt controller while we are already handling another MSI. Each MSI vector gets written into a FIFO buffer in main memory using DMA, and that DMA access is normally flushed by the actual interrupt packet on the IOIF. An MMIO register in the MSIC holds the position of the last entry in the FIFO buffer that was written. However, reading that position does not flush the DMA, so that we can observe stale data in the buffer. In a stress test, we have observed the DMA to arrive up to 14 microseconds after reading the register. This patch works around this problem by retrying the access to the FIFO buffer. We can reliably detect the conditioning by writing an invalid MSI vector into the FIFO buffer after reading from it, assuming that all MSIs we get are valid. After detecting an invalid MSI vector, we udelay(1) in the interrupt cascade for up to 100 times before giving up. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-11-28 17:51:22 +08:00
memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
powerpc: Rework Axon MSI setup so we can avoid freeing the irq_host If we do the call to irq_of_parse_and_map() first, then we don't need to worry about freeing the irq_host. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-26 10:12:30 +08:00
powerpc: Fix irq_alloc_host() reference counting and callers When I changed irq_alloc_host() to take an of_node (52964f87c64e6c6ea671b5bf3030fb1494090a48: "Add an optional device_node pointer to the irq_host"), I botched the reference counting semantics. Stephen pointed out that it's irq_alloc_host()'s business if it needs to take an additional reference to the device_node, the caller shouldn't need to care. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-26 10:12:32 +08:00
msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
[POWERPC] Add an optional device_node pointer to the irq_host The majority of irq_host implementations (3 out of 4) are associated with a device_node, and need to stash it somewhere. Rather than having it somewhere different for each host, add an optional device_node pointer to the irq_host structure. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-08-28 16:47:54 +08:00
NR_IRQS, &msic_host_ops, 0);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
if (!msic->irq_host) {
printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
dn->full_name);
goto out_free_fifo;
}
msic->irq_host->host_data = msic;
powerpc: Convert to new irq_* function names Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-25 23:45:20 +08:00
irq_set_handler_data(virq, msic);
irq_set_chained_handler(virq, axon_msi_cascade);
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
/* Enable the MSIC hardware */
[POWERPC] Avoid DMA exception when using axon_msi with IOMMU There's a brown-paper-bag bug in axon_msi, we pass the address of our FIFO directly to the hardware, without DMA mapping it. This leads to DMA exceptions if you enable MSI & the IOMMU. The fix is to correctly DMA map the fifo, dma_alloc_coherent() does what we want - and we need to track the virt & phys addresses. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
[POWERPC] Avoid DMA exception when using axon_msi with IOMMU There's a brown-paper-bag bug in axon_msi, we pass the address of our FIFO directly to the hardware, without DMA mapping it. This leads to DMA exceptions if you enable MSI & the IOMMU. The fix is to correctly DMA map the fifo, dma_alloc_coherent() does what we want - and we need to track the virt & phys addresses. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
msic->fifo_phys & 0xFFFFFFFF);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
msic_dcr_write(msic, MSIC_CTRL_REG,
MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
MSIC_CTRL_FIFO_SIZE);
powerpc/cell/axon-msi: Fix MSI after kexec Commit d015fe995 'powerpc/cell/axon-msi: Retry on missing interrupt' has turned a rare failure to kexec on QS22 into a reproducible error, which we have now analysed. The problem is that after a kexec, the MSIC hardware still points into the middle of the old ring buffer. We set up the ring buffer during reboot, but not the offset into it. On older kernels, this would cause a storm of thousands of spurious interrupts after a kexec, which would most of the time get dropped silently. With the new code, we time out on each interrupt, waiting for it to become valid. If more interrupts come in that we time out on, this goes on indefinitely, which eventually leads to a hard crash. The solution in this commit is to read the current offset from the MSIC when reinitializing it. This now works correctly, as expected. Reported-by: Dirk Herrendoerfer <d.herrendoerfer@de.ibm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-12-12 17:19:50 +08:00
msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
& MSIC_FIFO_SIZE_MASK;
powerpc/cell: Use driver_data acessors, not platform_data in Axon MSI The Axon MSI driver incorrectly uses platform_data, rather than the proper accessors for driver_data. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-11 03:06:34 +08:00
dev_set_drvdata(&device->dev, msic);
[POWERPC] Convert axon_msi to an of_platform driver Now that we create of_platform devices earlier on cell, we can make the axon_msi driver an of_platform driver. This makes the code cleaner in several ways, and most importantly means we have a struct device. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
ppc_md.msi_check_device = axon_msi_check_device;
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
[POWERPC] Add debugging trigger to Axon MSI code This adds some debugging code to the Axon MSI driver. It creates a file per MSIC in /sys/kernel/debug/powerpc, which allows the user to trigger a fake MSI interrupt by writing to the file. This can be used to test some of the MSI generation path. In particular, that the MSIC recognises a write to the MSI address, generates an interrupt and writes the MSI packet into the ring buffer. All the code is inside #ifdef DEBUG so it causes no harm unless it's enabled. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-23 12:21:30 +08:00
axon_msi_debug_setup(dn, msic);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
return 0;
out_free_fifo:
[POWERPC] Avoid DMA exception when using axon_msi with IOMMU There's a brown-paper-bag bug in axon_msi, we pass the address of our FIFO directly to the hardware, without DMA mapping it. This leads to DMA exceptions if you enable MSI & the IOMMU. The fix is to correctly DMA map the fifo, dma_alloc_coherent() does what we want - and we need to track the virt & phys addresses. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
msic->fifo_phys);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
out_free_msic:
kfree(msic);
out:
return -1;
}
[POWERPC] Convert axon_msi to an of_platform driver Now that we create of_platform devices earlier on cell, we can make the axon_msi driver an of_platform driver. This makes the code cleaner in several ways, and most importantly means we have a struct device. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
static const struct of_device_id axon_msi_device_id[] = {
{
.compatible = "ibm,axon-msic"
},
{}
};
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
dt/powerpc: Eliminate users of of_platform_{,un}register_driver Get rid of old users of of_platform_driver in arch/powerpc. Most of_platform_driver users can be converted to use the platform_bus directly. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-23 10:59:54 +08:00
static struct platform_driver axon_msi_driver = {
[POWERPC] Convert axon_msi to an of_platform driver Now that we create of_platform devices earlier on cell, we can make the axon_msi driver an of_platform driver. This makes the code cleaner in several ways, and most importantly means we have a struct device. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
.probe = axon_msi_probe,
.shutdown = axon_msi_shutdown,
of: Remove duplicate fields from of_platform_driver .name, .match_table and .owner are duplicated in both of_platform_driver and device_driver. This patch is a removes the extra copies from struct of_platform_driver and converts all users to the device_driver members. This patch is a pretty mechanical change. The usage model doesn't change and if any drivers have been missed, or if anything has been fixed up incorrectly, then it will fail with a compile time error, and the fixup will be trivial. This patch looks big and scary because it touches so many files, but it should be pretty safe. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Sean MacLennan <smaclennan@pikatech.com>
2010-04-14 07:13:02 +08:00
.driver = {
.name = "axon-msi",
.owner = THIS_MODULE,
.of_match_table = axon_msi_device_id,
[POWERPC] Convert axon_msi to an of_platform driver Now that we create of_platform devices earlier on cell, we can make the axon_msi driver an of_platform driver. This makes the code cleaner in several ways, and most importantly means we have a struct device. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
},
};
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
[POWERPC] Convert axon_msi to an of_platform driver Now that we create of_platform devices earlier on cell, we can make the axon_msi driver an of_platform driver. This makes the code cleaner in several ways, and most importantly means we have a struct device. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
static int __init axon_msi_init(void)
{
dt/powerpc: Eliminate users of of_platform_{,un}register_driver Get rid of old users of of_platform_driver in arch/powerpc. Most of_platform_driver users can be converted to use the platform_bus directly. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2011-02-23 10:59:54 +08:00
return platform_driver_register(&axon_msi_driver);
[CELL] add support for MSI on Axon-based Cell systems This patch adds support for the setup and decoding of MSIs on Axon-based Cell systems, using the MSIC mechanism. This involves setting up an area of BE memory which the Axon then uses as a FIFO for MSI messages. When one or more MSIs are decoded by the MSIC we receive an interrupt on the MPIC, and the MSI messages are written into the FIFO. At the moment we use a 64KB FIFO, one per MSIC/BE. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
2007-07-21 03:39:28 +08:00
}
[POWERPC] Convert axon_msi to an of_platform driver Now that we create of_platform devices earlier on cell, we can make the axon_msi driver an of_platform driver. This makes the code cleaner in several ways, and most importantly means we have a struct device. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-01-25 13:59:14 +08:00
subsys_initcall(axon_msi_init);
[POWERPC] Add debugging trigger to Axon MSI code This adds some debugging code to the Axon MSI driver. It creates a file per MSIC in /sys/kernel/debug/powerpc, which allows the user to trigger a fake MSI interrupt by writing to the file. This can be used to test some of the MSI generation path. In particular, that the MSIC recognises a write to the MSI address, generates an interrupt and writes the MSI packet into the ring buffer. All the code is inside #ifdef DEBUG so it causes no harm unless it's enabled. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-23 12:21:30 +08:00
#ifdef DEBUG
static int msic_set(void *data, u64 val)
{
struct axon_msic *msic = data;
out_le32(msic->trigger, val);
return 0;
}
static int msic_get(void *data, u64 *val)
{
*val = 0;
return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
{
char name[8];
u64 addr;
addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
if (addr == OF_BAD_ADDR) {
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: couldn't translate reg property\n");
[POWERPC] Add debugging trigger to Axon MSI code This adds some debugging code to the Axon MSI driver. It creates a file per MSIC in /sys/kernel/debug/powerpc, which allows the user to trigger a fake MSI interrupt by writing to the file. This can be used to test some of the MSI generation path. In particular, that the MSIC recognises a write to the MSI address, generates an interrupt and writes the MSI packet into the ring buffer. All the code is inside #ifdef DEBUG so it causes no harm unless it's enabled. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-23 12:21:30 +08:00
return;
}
msic->trigger = ioremap(addr, 0x4);
if (!msic->trigger) {
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: ioremap failed\n");
[POWERPC] Add debugging trigger to Axon MSI code This adds some debugging code to the Axon MSI driver. It creates a file per MSIC in /sys/kernel/debug/powerpc, which allows the user to trigger a fake MSI interrupt by writing to the file. This can be used to test some of the MSI generation path. In particular, that the MSIC recognises a write to the MSI address, generates an interrupt and writes the MSI packet into the ring buffer. All the code is inside #ifdef DEBUG so it causes no harm unless it's enabled. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-23 12:21:30 +08:00
return;
}
snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
msic, &fops_msic)) {
powerpc/cell: Use pr_devel() in axon_msi.c pr_debug() can now result in code being generated even when DEBUG is not defined. That's not really desirable in some places. With CONFIG_DYNAMIC_DEBUG=y: size before: text data bss dec hex filename 7083 1616 0 8699 21fb arch/powerpc/../axon_msi.o size after: text data bss dec hex filename 5772 1208 0 6980 1b44 arch/powerpc/../axon_msi.o Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-06-18 02:13:53 +08:00
pr_devel("axon_msi: debugfs_create_file failed!\n");
[POWERPC] Add debugging trigger to Axon MSI code This adds some debugging code to the Axon MSI driver. It creates a file per MSIC in /sys/kernel/debug/powerpc, which allows the user to trigger a fake MSI interrupt by writing to the file. This can be used to test some of the MSI generation path. In particular, that the MSIC recognises a write to the MSI address, generates an interrupt and writes the MSI packet into the ring buffer. All the code is inside #ifdef DEBUG so it causes no harm unless it's enabled. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-05-23 12:21:30 +08:00
return;
}
}
#endif /* DEBUG */