2008-10-29 12:46:30 +08:00
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/*
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2009-03-13 11:37:23 +08:00
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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2008-10-29 12:46:30 +08:00
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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2009-09-14 14:55:05 +08:00
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#include "hw.h"
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2010-06-12 12:33:42 +08:00
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#include "hw-ops.h"
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2008-10-29 12:46:30 +08:00
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2010-04-16 05:39:26 +08:00
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static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
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struct ath9k_tx_queue_info *qi)
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{
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2010-12-03 11:12:37 +08:00
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ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
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"tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
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ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
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ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
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ah->txurn_interrupt_mask);
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2010-04-16 05:39:26 +08:00
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2010-04-16 14:23:57 +08:00
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ENABLE_REGWRITE_BUFFER(ah);
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2010-04-16 05:39:26 +08:00
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REG_WRITE(ah, AR_IMR_S0,
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SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
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| SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
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REG_WRITE(ah, AR_IMR_S1,
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SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
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| SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
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ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
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ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
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REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
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2010-04-16 14:23:57 +08:00
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REGWRITE_BUFFER_FLUSH(ah);
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2010-04-16 05:39:26 +08:00
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}
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u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
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{
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return REG_READ(ah, AR_QTXDP(q));
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}
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EXPORT_SYMBOL(ath9k_hw_gettxbuf);
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void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
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{
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REG_WRITE(ah, AR_QTXDP(q), txdp);
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}
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EXPORT_SYMBOL(ath9k_hw_puttxbuf);
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void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
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{
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2010-12-03 11:12:37 +08:00
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ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
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"Enable TXE on queue: %u\n", q);
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2010-04-16 05:39:26 +08:00
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REG_WRITE(ah, AR_Q_TXE, 1 << q);
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}
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EXPORT_SYMBOL(ath9k_hw_txstart);
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void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds)
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{
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struct ar5416_desc *ads = AR5416DESC(ds);
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ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
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ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
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ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
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ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
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ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
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}
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EXPORT_SYMBOL(ath9k_hw_cleartxdesc);
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u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
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{
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u32 npend;
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npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
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if (npend == 0) {
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if (REG_READ(ah, AR_Q_TXE) & (1 << q))
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npend = 1;
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}
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return npend;
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}
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EXPORT_SYMBOL(ath9k_hw_numtxpending);
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/**
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* ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
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*
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* @ah: atheros hardware struct
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* @bIncTrigLevel: whether or not the frame trigger level should be updated
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*
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* The frame trigger level specifies the minimum number of bytes,
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* in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
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* before the PCU will initiate sending the frame on the air. This can
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* mean we initiate transmit before a full frame is on the PCU TX FIFO.
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* Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
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* first)
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*
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* Caution must be taken to ensure to set the frame trigger level based
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* on the DMA request size. For example if the DMA request size is set to
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* 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
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* there need to be enough space in the tx FIFO for the requested transfer
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* size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
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* the threshold to a value beyond 6, then the transmit will hang.
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*
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* Current dual stream devices have a PCU TX FIFO size of 8 KB.
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* Current single stream devices have a PCU TX FIFO size of 4 KB, however,
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* there is a hardware issue which forces us to use 2 KB instead so the
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* frame trigger level must not exceed 2 KB for these chipsets.
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*/
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bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
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{
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u32 txcfg, curLevel, newLevel;
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if (ah->tx_trig_level >= ah->config.max_txtrig_level)
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return false;
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2010-11-09 03:54:47 +08:00
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ath9k_hw_disable_interrupts(ah);
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2010-04-16 05:39:26 +08:00
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txcfg = REG_READ(ah, AR_TXCFG);
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curLevel = MS(txcfg, AR_FTRIG);
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newLevel = curLevel;
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if (bIncTrigLevel) {
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if (curLevel < ah->config.max_txtrig_level)
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newLevel++;
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} else if (curLevel > MIN_TX_FIFO_THRESHOLD)
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newLevel--;
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if (newLevel != curLevel)
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REG_WRITE(ah, AR_TXCFG,
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(txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
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2010-11-09 03:54:47 +08:00
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ath9k_hw_enable_interrupts(ah);
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2010-04-16 05:39:26 +08:00
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ah->tx_trig_level = newLevel;
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return newLevel != curLevel;
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}
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EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
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2011-03-12 04:38:18 +08:00
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void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
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2010-04-16 05:39:26 +08:00
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{
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2011-03-12 04:38:18 +08:00
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int i, q;
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2010-04-16 05:39:26 +08:00
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2011-03-12 04:38:18 +08:00
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REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
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2010-04-16 05:39:26 +08:00
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2011-03-12 04:38:18 +08:00
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REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
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REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
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REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
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2010-04-16 05:39:26 +08:00
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2011-03-12 04:38:18 +08:00
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for (q = 0; q < AR_NUM_QCU; q++) {
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for (i = 0; i < 1000; i++) {
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if (i)
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udelay(5);
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2010-04-16 05:39:26 +08:00
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2011-03-12 04:38:18 +08:00
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if (!ath9k_hw_numtxpending(ah, q))
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2010-04-16 05:39:26 +08:00
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break;
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}
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2011-03-12 04:38:18 +08:00
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}
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2010-04-16 05:39:26 +08:00
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2011-03-12 04:38:18 +08:00
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REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
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REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
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REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
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2010-04-16 05:39:26 +08:00
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2011-03-12 04:38:18 +08:00
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REG_WRITE(ah, AR_Q_TXD, 0);
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}
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EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
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2010-04-16 05:39:26 +08:00
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2011-03-12 04:38:20 +08:00
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bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
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2010-04-16 05:39:26 +08:00
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{
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2011-03-12 04:38:20 +08:00
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#define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */
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2010-04-16 05:39:26 +08:00
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#define ATH9K_TIME_QUANTUM 100 /* usec */
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2011-03-12 04:38:20 +08:00
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int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
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int wait;
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2010-04-16 05:39:26 +08:00
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REG_WRITE(ah, AR_Q_TXD, 1 << q);
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for (wait = wait_time; wait != 0; wait--) {
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2011-03-12 04:38:20 +08:00
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if (wait != wait_time)
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2010-04-16 05:39:26 +08:00
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udelay(ATH9K_TIME_QUANTUM);
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2011-03-12 04:38:20 +08:00
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if (ath9k_hw_numtxpending(ah, q) == 0)
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break;
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2010-04-16 05:39:26 +08:00
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}
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REG_WRITE(ah, AR_Q_TXD, 0);
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2011-03-12 04:38:20 +08:00
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2010-04-16 05:39:26 +08:00
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return wait != 0;
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#undef ATH9K_TX_STOP_DMA_TIMEOUT
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#undef ATH9K_TIME_QUANTUM
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}
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2011-03-12 04:38:20 +08:00
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EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
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2010-04-16 05:39:26 +08:00
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2009-02-09 15:57:12 +08:00
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void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs)
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2008-10-29 12:46:30 +08:00
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{
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2009-02-09 15:57:26 +08:00
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*txqs &= ah->intr_txqs;
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ah->intr_txqs &= ~(*txqs);
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2008-10-29 12:46:30 +08:00
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}
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2009-09-24 11:07:00 +08:00
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EXPORT_SYMBOL(ath9k_hw_gettxintrtxqs);
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2008-10-29 12:46:30 +08:00
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2009-02-09 15:57:12 +08:00
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bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
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2008-10-29 12:46:30 +08:00
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const struct ath9k_tx_queue_info *qinfo)
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{
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u32 cw;
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2009-09-13 17:42:02 +08:00
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struct ath_common *common = ath9k_hw_common(ah);
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2008-10-29 12:46:30 +08:00
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struct ath9k_tx_queue_info *qi;
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2009-02-09 15:57:26 +08:00
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qi = &ah->txq[q];
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2008-10-29 12:46:30 +08:00
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if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
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2010-12-03 11:12:37 +08:00
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ath_dbg(common, ATH_DBG_QUEUE,
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"Set TXQ properties, inactive queue: %u\n", q);
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2008-10-29 12:46:30 +08:00
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return false;
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}
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2010-12-03 11:12:37 +08:00
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ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
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2008-10-29 12:46:30 +08:00
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qi->tqi_ver = qinfo->tqi_ver;
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qi->tqi_subtype = qinfo->tqi_subtype;
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qi->tqi_qflags = qinfo->tqi_qflags;
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qi->tqi_priority = qinfo->tqi_priority;
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if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
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qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
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else
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qi->tqi_aifs = INIT_AIFS;
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if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
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cw = min(qinfo->tqi_cwmin, 1024U);
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qi->tqi_cwmin = 1;
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while (qi->tqi_cwmin < cw)
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qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
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} else
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qi->tqi_cwmin = qinfo->tqi_cwmin;
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if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
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cw = min(qinfo->tqi_cwmax, 1024U);
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qi->tqi_cwmax = 1;
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while (qi->tqi_cwmax < cw)
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qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
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} else
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qi->tqi_cwmax = INIT_CWMAX;
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if (qinfo->tqi_shretry != 0)
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qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
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else
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qi->tqi_shretry = INIT_SH_RETRY;
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if (qinfo->tqi_lgretry != 0)
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qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
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else
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qi->tqi_lgretry = INIT_LG_RETRY;
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qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
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qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
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qi->tqi_burstTime = qinfo->tqi_burstTime;
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qi->tqi_readyTime = qinfo->tqi_readyTime;
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switch (qinfo->tqi_subtype) {
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case ATH9K_WME_UPSD:
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if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
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qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
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break;
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default:
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break;
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}
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return true;
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}
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2009-09-24 11:07:00 +08:00
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EXPORT_SYMBOL(ath9k_hw_set_txq_props);
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2008-10-29 12:46:30 +08:00
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2009-02-09 15:57:12 +08:00
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bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
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2008-10-29 12:46:30 +08:00
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struct ath9k_tx_queue_info *qinfo)
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{
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2009-09-13 17:42:02 +08:00
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struct ath_common *common = ath9k_hw_common(ah);
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2008-10-29 12:46:30 +08:00
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struct ath9k_tx_queue_info *qi;
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2009-02-09 15:57:26 +08:00
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qi = &ah->txq[q];
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2008-10-29 12:46:30 +08:00
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if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_QUEUE,
|
|
|
|
"Get TXQ properties, inactive queue: %u\n", q);
|
2008-10-29 12:46:30 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
qinfo->tqi_qflags = qi->tqi_qflags;
|
|
|
|
qinfo->tqi_ver = qi->tqi_ver;
|
|
|
|
qinfo->tqi_subtype = qi->tqi_subtype;
|
|
|
|
qinfo->tqi_qflags = qi->tqi_qflags;
|
|
|
|
qinfo->tqi_priority = qi->tqi_priority;
|
|
|
|
qinfo->tqi_aifs = qi->tqi_aifs;
|
|
|
|
qinfo->tqi_cwmin = qi->tqi_cwmin;
|
|
|
|
qinfo->tqi_cwmax = qi->tqi_cwmax;
|
|
|
|
qinfo->tqi_shretry = qi->tqi_shretry;
|
|
|
|
qinfo->tqi_lgretry = qi->tqi_lgretry;
|
|
|
|
qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
|
|
|
|
qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
|
|
|
|
qinfo->tqi_burstTime = qi->tqi_burstTime;
|
|
|
|
qinfo->tqi_readyTime = qi->tqi_readyTime;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_get_txq_props);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2009-02-09 15:57:12 +08:00
|
|
|
int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
|
2008-10-29 12:46:30 +08:00
|
|
|
const struct ath9k_tx_queue_info *qinfo)
|
|
|
|
{
|
2009-09-13 17:42:02 +08:00
|
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
2008-10-29 12:46:30 +08:00
|
|
|
struct ath9k_tx_queue_info *qi;
|
|
|
|
int q;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case ATH9K_TX_QUEUE_BEACON:
|
2011-03-24 03:57:28 +08:00
|
|
|
q = ATH9K_NUM_TX_QUEUES - 1;
|
2008-10-29 12:46:30 +08:00
|
|
|
break;
|
|
|
|
case ATH9K_TX_QUEUE_CAB:
|
2011-03-24 03:57:28 +08:00
|
|
|
q = ATH9K_NUM_TX_QUEUES - 2;
|
2008-10-29 12:46:30 +08:00
|
|
|
break;
|
|
|
|
case ATH9K_TX_QUEUE_PSPOLL:
|
|
|
|
q = 1;
|
|
|
|
break;
|
|
|
|
case ATH9K_TX_QUEUE_UAPSD:
|
2011-03-24 03:57:28 +08:00
|
|
|
q = ATH9K_NUM_TX_QUEUES - 3;
|
2008-10-29 12:46:30 +08:00
|
|
|
break;
|
|
|
|
case ATH9K_TX_QUEUE_DATA:
|
2011-03-24 03:57:28 +08:00
|
|
|
for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
|
2009-02-09 15:57:26 +08:00
|
|
|
if (ah->txq[q].tqi_type ==
|
2008-10-29 12:46:30 +08:00
|
|
|
ATH9K_TX_QUEUE_INACTIVE)
|
|
|
|
break;
|
2011-03-24 03:57:28 +08:00
|
|
|
if (q == ATH9K_NUM_TX_QUEUES) {
|
2010-12-03 11:12:36 +08:00
|
|
|
ath_err(common, "No available TX queue\n");
|
2008-10-29 12:46:30 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
2010-12-03 11:12:36 +08:00
|
|
|
ath_err(common, "Invalid TX queue type: %u\n", type);
|
2008-10-29 12:46:30 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2009-02-09 15:57:26 +08:00
|
|
|
qi = &ah->txq[q];
|
2008-10-29 12:46:30 +08:00
|
|
|
if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
|
2010-12-03 11:12:36 +08:00
|
|
|
ath_err(common, "TX queue: %u already active\n", q);
|
2008-10-29 12:46:30 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
|
|
|
|
qi->tqi_type = type;
|
|
|
|
if (qinfo == NULL) {
|
|
|
|
qi->tqi_qflags =
|
|
|
|
TXQ_FLAG_TXOKINT_ENABLE
|
|
|
|
| TXQ_FLAG_TXERRINT_ENABLE
|
|
|
|
| TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
|
|
|
|
qi->tqi_aifs = INIT_AIFS;
|
|
|
|
qi->tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
|
|
|
|
qi->tqi_cwmax = INIT_CWMAX;
|
|
|
|
qi->tqi_shretry = INIT_SH_RETRY;
|
|
|
|
qi->tqi_lgretry = INIT_LG_RETRY;
|
|
|
|
qi->tqi_physCompBuf = 0;
|
|
|
|
} else {
|
|
|
|
qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
|
|
|
|
(void) ath9k_hw_set_txq_props(ah, q, qinfo);
|
|
|
|
}
|
|
|
|
|
|
|
|
return q;
|
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2009-02-09 15:57:12 +08:00
|
|
|
bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
|
2008-10-29 12:46:30 +08:00
|
|
|
{
|
2009-09-13 17:42:02 +08:00
|
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
2008-10-29 12:46:30 +08:00
|
|
|
struct ath9k_tx_queue_info *qi;
|
|
|
|
|
2009-02-09 15:57:26 +08:00
|
|
|
qi = &ah->txq[q];
|
2008-10-29 12:46:30 +08:00
|
|
|
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_QUEUE,
|
|
|
|
"Release TXQ, inactive queue: %u\n", q);
|
2008-10-29 12:46:30 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
|
|
|
qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txok_interrupt_mask &= ~(1 << q);
|
|
|
|
ah->txerr_interrupt_mask &= ~(1 << q);
|
|
|
|
ah->txdesc_interrupt_mask &= ~(1 << q);
|
|
|
|
ah->txeol_interrupt_mask &= ~(1 << q);
|
|
|
|
ah->txurn_interrupt_mask &= ~(1 << q);
|
2008-10-29 12:46:30 +08:00
|
|
|
ath9k_hw_set_txq_interrupts(ah, qi);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2009-02-09 15:57:12 +08:00
|
|
|
bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
|
2008-10-29 12:46:30 +08:00
|
|
|
{
|
2009-09-13 17:42:02 +08:00
|
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
2009-02-09 15:57:26 +08:00
|
|
|
struct ath9k_channel *chan = ah->curchan;
|
2008-10-29 12:46:30 +08:00
|
|
|
struct ath9k_tx_queue_info *qi;
|
|
|
|
u32 cwMin, chanCwMin, value;
|
|
|
|
|
2009-02-09 15:57:26 +08:00
|
|
|
qi = &ah->txq[q];
|
2008-10-29 12:46:30 +08:00
|
|
|
if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_QUEUE,
|
|
|
|
"Reset TXQ, inactive queue: %u\n", q);
|
2008-10-29 12:46:30 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
|
|
|
if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
|
|
|
|
if (chan && IS_CHAN_B(chan))
|
|
|
|
chanCwMin = INIT_CWMIN_11B;
|
|
|
|
else
|
|
|
|
chanCwMin = INIT_CWMIN;
|
|
|
|
|
|
|
|
for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
|
|
|
|
} else
|
|
|
|
cwMin = qi->tqi_cwmin;
|
|
|
|
|
2010-04-16 14:23:57 +08:00
|
|
|
ENABLE_REGWRITE_BUFFER(ah);
|
|
|
|
|
2008-10-29 12:46:30 +08:00
|
|
|
REG_WRITE(ah, AR_DLCL_IFS(q),
|
|
|
|
SM(cwMin, AR_D_LCL_IFS_CWMIN) |
|
|
|
|
SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
|
|
|
|
SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_DRETRY_LIMIT(q),
|
|
|
|
SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
|
|
|
|
SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
|
|
|
|
SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
|
|
|
|
REG_WRITE(ah, AR_DMISC(q),
|
|
|
|
AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
|
|
|
|
|
|
|
|
if (qi->tqi_cbrPeriod) {
|
|
|
|
REG_WRITE(ah, AR_QCBRCFG(q),
|
|
|
|
SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
|
|
|
|
SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
|
2011-03-24 03:57:26 +08:00
|
|
|
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
|
|
|
|
(qi->tqi_cbrOverflowLimit ?
|
|
|
|
AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
|
2008-10-29 12:46:30 +08:00
|
|
|
}
|
|
|
|
if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
|
|
|
|
REG_WRITE(ah, AR_QRDYTIMECFG(q),
|
|
|
|
SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
|
|
|
|
AR_Q_RDYTIMECFG_EN);
|
|
|
|
}
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_DCHNTIME(q),
|
|
|
|
SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
|
|
|
|
(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
|
|
|
|
|
|
|
|
if (qi->tqi_burstTime
|
2011-03-24 03:57:26 +08:00
|
|
|
&& (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
|
|
|
|
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2011-03-24 03:57:26 +08:00
|
|
|
if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
|
|
|
|
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
|
2010-04-16 14:23:57 +08:00
|
|
|
|
|
|
|
REGWRITE_BUFFER_FLUSH(ah);
|
|
|
|
|
2011-03-24 03:57:26 +08:00
|
|
|
if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
|
|
|
|
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
|
|
|
|
|
2008-10-29 12:46:30 +08:00
|
|
|
switch (qi->tqi_type) {
|
|
|
|
case ATH9K_TX_QUEUE_BEACON:
|
2010-04-16 14:23:57 +08:00
|
|
|
ENABLE_REGWRITE_BUFFER(ah);
|
|
|
|
|
2011-03-24 03:57:26 +08:00
|
|
|
REG_SET_BIT(ah, AR_QMISC(q),
|
|
|
|
AR_Q_MISC_FSP_DBA_GATED
|
|
|
|
| AR_Q_MISC_BEACON_USE
|
|
|
|
| AR_Q_MISC_CBR_INCR_DIS1);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2011-03-24 03:57:26 +08:00
|
|
|
REG_SET_BIT(ah, AR_DMISC(q),
|
|
|
|
(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
|
2008-10-29 12:46:30 +08:00
|
|
|
AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
|
2011-03-24 03:57:26 +08:00
|
|
|
| AR_D_MISC_BEACON_USE
|
|
|
|
| AR_D_MISC_POST_FR_BKOFF_DIS);
|
2010-04-16 14:23:57 +08:00
|
|
|
|
|
|
|
REGWRITE_BUFFER_FLUSH(ah);
|
|
|
|
|
2010-06-15 08:17:36 +08:00
|
|
|
/*
|
|
|
|
* cwmin and cwmax should be 0 for beacon queue
|
|
|
|
* but not for IBSS as we would create an imbalance
|
|
|
|
* on beaconing fairness for participating nodes.
|
|
|
|
*/
|
|
|
|
if (AR_SREV_9300_20_OR_LATER(ah) &&
|
|
|
|
ah->opmode != NL80211_IFTYPE_ADHOC) {
|
2010-04-16 05:39:32 +08:00
|
|
|
REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
|
|
|
|
| SM(0, AR_D_LCL_IFS_CWMAX)
|
|
|
|
| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
|
|
|
|
}
|
2008-10-29 12:46:30 +08:00
|
|
|
break;
|
|
|
|
case ATH9K_TX_QUEUE_CAB:
|
2010-04-16 14:23:57 +08:00
|
|
|
ENABLE_REGWRITE_BUFFER(ah);
|
|
|
|
|
2011-03-24 03:57:26 +08:00
|
|
|
REG_SET_BIT(ah, AR_QMISC(q),
|
|
|
|
AR_Q_MISC_FSP_DBA_GATED
|
|
|
|
| AR_Q_MISC_CBR_INCR_DIS1
|
|
|
|
| AR_Q_MISC_CBR_INCR_DIS0);
|
2008-10-29 12:46:30 +08:00
|
|
|
value = (qi->tqi_readyTime -
|
2009-02-09 15:57:26 +08:00
|
|
|
(ah->config.sw_beacon_response_time -
|
|
|
|
ah->config.dma_beacon_response_time) -
|
|
|
|
ah->config.additional_swba_backoff) * 1024;
|
2008-10-29 12:46:30 +08:00
|
|
|
REG_WRITE(ah, AR_QRDYTIMECFG(q),
|
|
|
|
value | AR_Q_RDYTIMECFG_EN);
|
2011-03-24 03:57:26 +08:00
|
|
|
REG_SET_BIT(ah, AR_DMISC(q),
|
|
|
|
(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
|
2008-10-29 12:46:30 +08:00
|
|
|
AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
|
2010-04-16 14:23:57 +08:00
|
|
|
|
|
|
|
REGWRITE_BUFFER_FLUSH(ah);
|
|
|
|
|
2008-10-29 12:46:30 +08:00
|
|
|
break;
|
|
|
|
case ATH9K_TX_QUEUE_PSPOLL:
|
2011-03-24 03:57:26 +08:00
|
|
|
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
|
2008-10-29 12:46:30 +08:00
|
|
|
break;
|
|
|
|
case ATH9K_TX_QUEUE_UAPSD:
|
2011-03-24 03:57:26 +08:00
|
|
|
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
|
2008-10-29 12:46:30 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
|
2011-03-24 03:57:26 +08:00
|
|
|
REG_SET_BIT(ah, AR_DMISC(q),
|
|
|
|
SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
|
|
|
|
AR_D_MISC_ARB_LOCKOUT_CNTRL) |
|
|
|
|
AR_D_MISC_POST_FR_BKOFF_DIS);
|
2008-10-29 12:46:30 +08:00
|
|
|
}
|
|
|
|
|
2010-04-16 05:39:31 +08:00
|
|
|
if (AR_SREV_9300_20_OR_LATER(ah))
|
|
|
|
REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
|
|
|
|
|
2008-10-29 12:46:30 +08:00
|
|
|
if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txok_interrupt_mask |= 1 << q;
|
2008-10-29 12:46:30 +08:00
|
|
|
else
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txok_interrupt_mask &= ~(1 << q);
|
2008-10-29 12:46:30 +08:00
|
|
|
if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txerr_interrupt_mask |= 1 << q;
|
2008-10-29 12:46:30 +08:00
|
|
|
else
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txerr_interrupt_mask &= ~(1 << q);
|
2008-10-29 12:46:30 +08:00
|
|
|
if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txdesc_interrupt_mask |= 1 << q;
|
2008-10-29 12:46:30 +08:00
|
|
|
else
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txdesc_interrupt_mask &= ~(1 << q);
|
2008-10-29 12:46:30 +08:00
|
|
|
if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txeol_interrupt_mask |= 1 << q;
|
2008-10-29 12:46:30 +08:00
|
|
|
else
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txeol_interrupt_mask &= ~(1 << q);
|
2008-10-29 12:46:30 +08:00
|
|
|
if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txurn_interrupt_mask |= 1 << q;
|
2008-10-29 12:46:30 +08:00
|
|
|
else
|
2009-02-09 15:57:26 +08:00
|
|
|
ah->txurn_interrupt_mask &= ~(1 << q);
|
2008-10-29 12:46:30 +08:00
|
|
|
ath9k_hw_set_txq_interrupts(ah, qi);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_resettxqueue);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2009-02-09 15:57:12 +08:00
|
|
|
int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
|
2010-03-30 11:09:27 +08:00
|
|
|
struct ath_rx_status *rs, u64 tsf)
|
2008-10-29 12:46:30 +08:00
|
|
|
{
|
|
|
|
struct ar5416_desc ads;
|
|
|
|
struct ar5416_desc *adsp = AR5416DESC(ds);
|
|
|
|
u32 phyerr;
|
|
|
|
|
|
|
|
if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
|
|
|
|
return -EINPROGRESS;
|
|
|
|
|
|
|
|
ads.u.rx = adsp->u.rx;
|
|
|
|
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_status = 0;
|
|
|
|
rs->rs_flags = 0;
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
|
|
|
|
rs->rs_tstamp = ads.AR_RcvTimestamp;
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2009-07-15 08:17:08 +08:00
|
|
|
if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_rssi = ATH9K_RSSI_BAD;
|
|
|
|
rs->rs_rssi_ctl0 = ATH9K_RSSI_BAD;
|
|
|
|
rs->rs_rssi_ctl1 = ATH9K_RSSI_BAD;
|
|
|
|
rs->rs_rssi_ctl2 = ATH9K_RSSI_BAD;
|
|
|
|
rs->rs_rssi_ext0 = ATH9K_RSSI_BAD;
|
|
|
|
rs->rs_rssi_ext1 = ATH9K_RSSI_BAD;
|
|
|
|
rs->rs_rssi_ext2 = ATH9K_RSSI_BAD;
|
2009-07-15 08:17:08 +08:00
|
|
|
} else {
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
|
|
|
|
rs->rs_rssi_ctl0 = MS(ads.ds_rxstatus0,
|
2009-07-15 08:17:08 +08:00
|
|
|
AR_RxRSSIAnt00);
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_rssi_ctl1 = MS(ads.ds_rxstatus0,
|
2009-07-15 08:17:08 +08:00
|
|
|
AR_RxRSSIAnt01);
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_rssi_ctl2 = MS(ads.ds_rxstatus0,
|
2009-07-15 08:17:08 +08:00
|
|
|
AR_RxRSSIAnt02);
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_rssi_ext0 = MS(ads.ds_rxstatus4,
|
2009-07-15 08:17:08 +08:00
|
|
|
AR_RxRSSIAnt10);
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_rssi_ext1 = MS(ads.ds_rxstatus4,
|
2009-07-15 08:17:08 +08:00
|
|
|
AR_RxRSSIAnt11);
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_rssi_ext2 = MS(ads.ds_rxstatus4,
|
2009-07-15 08:17:08 +08:00
|
|
|
AR_RxRSSIAnt12);
|
|
|
|
}
|
2008-10-29 12:46:30 +08:00
|
|
|
if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
|
2008-10-29 12:46:30 +08:00
|
|
|
else
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_rate = RXSTATUS_RATE(ah, (&ads));
|
|
|
|
rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
|
|
|
|
rs->rs_moreaggr =
|
2008-10-29 12:46:30 +08:00
|
|
|
(ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
|
|
|
|
rs->rs_flags =
|
2008-10-29 12:46:30 +08:00
|
|
|
(ads.ds_rxstatus3 & AR_GI) ? ATH9K_RX_GI : 0;
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_flags |=
|
2008-10-29 12:46:30 +08:00
|
|
|
(ads.ds_rxstatus3 & AR_2040) ? ATH9K_RX_2040 : 0;
|
|
|
|
|
|
|
|
if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
|
2008-10-29 12:46:30 +08:00
|
|
|
if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
|
2008-10-29 12:46:30 +08:00
|
|
|
if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
|
2008-10-29 12:46:30 +08:00
|
|
|
|
|
|
|
if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
|
2011-01-14 07:06:27 +08:00
|
|
|
/*
|
|
|
|
* Treat these errors as mutually exclusive to avoid spurious
|
|
|
|
* extra error reports from the hardware. If a CRC error is
|
|
|
|
* reported, then decryption and MIC errors are irrelevant,
|
|
|
|
* the frame is going to be dropped either way
|
|
|
|
*/
|
2008-10-29 12:46:30 +08:00
|
|
|
if (ads.ds_rxstatus8 & AR_CRCErr)
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_status |= ATH9K_RXERR_CRC;
|
2011-01-14 07:06:27 +08:00
|
|
|
else if (ads.ds_rxstatus8 & AR_PHYErr) {
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_status |= ATH9K_RXERR_PHY;
|
2008-10-29 12:46:30 +08:00
|
|
|
phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_phyerr = phyerr;
|
2011-01-14 07:06:27 +08:00
|
|
|
} else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_status |= ATH9K_RXERR_DECRYPT;
|
2011-01-14 07:06:27 +08:00
|
|
|
else if (ads.ds_rxstatus8 & AR_MichaelErr)
|
2010-03-30 11:09:27 +08:00
|
|
|
rs->rs_status |= ATH9K_RXERR_MIC;
|
2011-01-14 07:06:27 +08:00
|
|
|
|
2010-12-28 22:46:16 +08:00
|
|
|
if (ads.ds_rxstatus8 & AR_KeyMiss)
|
2010-09-15 00:38:26 +08:00
|
|
|
rs->rs_status |= ATH9K_RXERR_DECRYPT;
|
2008-10-29 12:46:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2009-11-24 15:53:25 +08:00
|
|
|
/*
|
|
|
|
* This can stop or re-enables RX.
|
|
|
|
*
|
|
|
|
* If bool is set this will kill any frame which is currently being
|
|
|
|
* transferred between the MAC and baseband and also prevent any new
|
|
|
|
* frames from getting started.
|
|
|
|
*/
|
2009-02-09 15:57:12 +08:00
|
|
|
bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
|
2008-10-29 12:46:30 +08:00
|
|
|
{
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
if (set) {
|
|
|
|
REG_SET_BIT(ah, AR_DIAG_SW,
|
|
|
|
(AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
|
|
|
|
|
2009-02-16 15:53:20 +08:00
|
|
|
if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
|
|
|
|
0, AH_WAIT_TIMEOUT)) {
|
2008-10-29 12:46:30 +08:00
|
|
|
REG_CLR_BIT(ah, AR_DIAG_SW,
|
|
|
|
(AR_DIAG_RX_DIS |
|
|
|
|
AR_DIAG_RX_ABORT));
|
|
|
|
|
|
|
|
reg = REG_READ(ah, AR_OBS_BUS_1);
|
2010-12-03 11:12:36 +08:00
|
|
|
ath_err(ath9k_hw_common(ah),
|
|
|
|
"RX failed to go idle in 10 ms RXSM=0x%x\n",
|
|
|
|
reg);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
REG_CLR_BIT(ah, AR_DIAG_SW,
|
|
|
|
(AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_setrxabort);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2009-02-09 15:57:12 +08:00
|
|
|
void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
|
2008-10-29 12:46:30 +08:00
|
|
|
{
|
|
|
|
REG_WRITE(ah, AR_RXDP, rxdp);
|
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_putrxbuf);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2010-06-12 12:33:44 +08:00
|
|
|
void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
|
2008-10-29 12:46:30 +08:00
|
|
|
{
|
|
|
|
ath9k_enable_mib_counters(ah);
|
|
|
|
|
2010-06-12 12:33:44 +08:00
|
|
|
ath9k_ani_reset(ah, is_scanning);
|
2008-12-08 22:13:48 +08:00
|
|
|
|
2008-12-08 22:13:50 +08:00
|
|
|
REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
|
2008-10-29 12:46:30 +08:00
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_startpcureceive);
|
2008-10-29 12:46:30 +08:00
|
|
|
|
2010-04-16 05:39:41 +08:00
|
|
|
void ath9k_hw_abortpcurecv(struct ath_hw *ah)
|
|
|
|
{
|
|
|
|
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
|
|
|
|
|
|
|
|
ath9k_hw_disable_mib_counters(ah);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
|
|
|
|
|
2009-02-09 15:57:12 +08:00
|
|
|
bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
|
2008-10-29 12:46:30 +08:00
|
|
|
{
|
2009-02-16 15:53:20 +08:00
|
|
|
#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
|
2009-09-13 17:42:02 +08:00
|
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
2009-02-16 15:53:20 +08:00
|
|
|
int i;
|
|
|
|
|
2008-10-29 12:46:30 +08:00
|
|
|
REG_WRITE(ah, AR_CR, AR_CR_RXD);
|
|
|
|
|
2009-02-16 15:53:20 +08:00
|
|
|
/* Wait for rx enable bit to go low */
|
|
|
|
for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
|
|
|
|
if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
|
|
|
|
break;
|
|
|
|
udelay(AH_TIME_QUANTUM);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == 0) {
|
2010-12-03 11:12:36 +08:00
|
|
|
ath_err(common,
|
|
|
|
"DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
|
|
|
|
AH_RX_STOP_DMA_TIMEOUT / 1000,
|
|
|
|
REG_READ(ah, AR_CR),
|
|
|
|
REG_READ(ah, AR_DIAG_SW));
|
2008-10-29 12:46:30 +08:00
|
|
|
return false;
|
|
|
|
} else {
|
|
|
|
return true;
|
|
|
|
}
|
2009-02-16 15:53:20 +08:00
|
|
|
|
|
|
|
#undef AH_RX_STOP_DMA_TIMEOUT
|
2008-10-29 12:46:30 +08:00
|
|
|
}
|
2009-09-24 11:07:00 +08:00
|
|
|
EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
|
2009-10-07 09:19:11 +08:00
|
|
|
|
|
|
|
int ath9k_hw_beaconq_setup(struct ath_hw *ah)
|
|
|
|
{
|
|
|
|
struct ath9k_tx_queue_info qi;
|
|
|
|
|
|
|
|
memset(&qi, 0, sizeof(qi));
|
|
|
|
qi.tqi_aifs = 1;
|
|
|
|
qi.tqi_cwmin = 0;
|
|
|
|
qi.tqi_cwmax = 0;
|
|
|
|
/* NB: don't enable any interrupts */
|
|
|
|
return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
|
2010-04-16 05:39:06 +08:00
|
|
|
|
|
|
|
bool ath9k_hw_intrpend(struct ath_hw *ah)
|
|
|
|
{
|
|
|
|
u32 host_isr;
|
|
|
|
|
|
|
|
if (AR_SREV_9100(ah))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
|
|
|
|
if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
|
|
|
|
if ((host_isr & AR_INTR_SYNC_DEFAULT)
|
|
|
|
&& (host_isr != AR_INTR_SPURIOUS))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(ath9k_hw_intrpend);
|
|
|
|
|
2010-11-09 03:54:47 +08:00
|
|
|
void ath9k_hw_disable_interrupts(struct ath_hw *ah)
|
|
|
|
{
|
|
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
|
2010-11-09 03:54:47 +08:00
|
|
|
REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
|
|
|
|
(void) REG_READ(ah, AR_IER);
|
|
|
|
if (!AR_SREV_9100(ah)) {
|
|
|
|
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
|
|
|
|
(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
|
|
|
|
(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
|
|
|
|
|
|
|
|
void ath9k_hw_enable_interrupts(struct ath_hw *ah)
|
|
|
|
{
|
|
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
|
|
|
if (!(ah->imask & ATH9K_INT_GLOBAL))
|
|
|
|
return;
|
|
|
|
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
|
2010-11-09 03:54:47 +08:00
|
|
|
REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
|
|
|
|
if (!AR_SREV_9100(ah)) {
|
|
|
|
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
|
|
|
|
AR_INTR_MAC_IRQ);
|
|
|
|
REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
|
|
|
|
|
|
|
|
|
|
|
|
REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
|
|
|
|
AR_INTR_SYNC_DEFAULT);
|
|
|
|
REG_WRITE(ah, AR_INTR_SYNC_MASK,
|
|
|
|
AR_INTR_SYNC_DEFAULT);
|
|
|
|
}
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
|
|
|
|
REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
|
2010-11-09 03:54:47 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
|
|
|
|
|
|
|
|
void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
|
2010-04-16 05:39:06 +08:00
|
|
|
{
|
|
|
|
enum ath9k_int omask = ah->imask;
|
|
|
|
u32 mask, mask2;
|
|
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
|
2010-11-09 03:54:47 +08:00
|
|
|
if (!(ints & ATH9K_INT_GLOBAL))
|
2011-02-21 22:02:41 +08:00
|
|
|
ath9k_hw_disable_interrupts(ah);
|
2010-04-16 05:39:06 +08:00
|
|
|
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
|
2010-04-16 05:39:06 +08:00
|
|
|
|
|
|
|
/* TODO: global int Ref count */
|
|
|
|
mask = ints & ATH9K_INT_COMMON;
|
|
|
|
mask2 = 0;
|
|
|
|
|
|
|
|
if (ints & ATH9K_INT_TX) {
|
|
|
|
if (ah->config.tx_intr_mitigation)
|
|
|
|
mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
|
2010-04-27 03:04:41 +08:00
|
|
|
else {
|
|
|
|
if (ah->txok_interrupt_mask)
|
|
|
|
mask |= AR_IMR_TXOK;
|
|
|
|
if (ah->txdesc_interrupt_mask)
|
|
|
|
mask |= AR_IMR_TXDESC;
|
|
|
|
}
|
2010-04-16 05:39:06 +08:00
|
|
|
if (ah->txerr_interrupt_mask)
|
|
|
|
mask |= AR_IMR_TXERR;
|
|
|
|
if (ah->txeol_interrupt_mask)
|
|
|
|
mask |= AR_IMR_TXEOL;
|
|
|
|
}
|
|
|
|
if (ints & ATH9K_INT_RX) {
|
|
|
|
if (AR_SREV_9300_20_OR_LATER(ah)) {
|
|
|
|
mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
|
|
|
|
if (ah->config.rx_intr_mitigation) {
|
|
|
|
mask &= ~AR_IMR_RXOK_LP;
|
|
|
|
mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
|
|
|
|
} else {
|
|
|
|
mask |= AR_IMR_RXOK_LP;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (ah->config.rx_intr_mitigation)
|
|
|
|
mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
|
|
|
|
else
|
|
|
|
mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
|
|
|
|
}
|
|
|
|
if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
|
|
|
|
mask |= AR_IMR_GENTMR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ints & (ATH9K_INT_BMISC)) {
|
|
|
|
mask |= AR_IMR_BCNMISC;
|
|
|
|
if (ints & ATH9K_INT_TIM)
|
|
|
|
mask2 |= AR_IMR_S2_TIM;
|
|
|
|
if (ints & ATH9K_INT_DTIM)
|
|
|
|
mask2 |= AR_IMR_S2_DTIM;
|
|
|
|
if (ints & ATH9K_INT_DTIMSYNC)
|
|
|
|
mask2 |= AR_IMR_S2_DTIMSYNC;
|
|
|
|
if (ints & ATH9K_INT_CABEND)
|
|
|
|
mask2 |= AR_IMR_S2_CABEND;
|
|
|
|
if (ints & ATH9K_INT_TSFOOR)
|
|
|
|
mask2 |= AR_IMR_S2_TSFOOR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
|
|
|
|
mask |= AR_IMR_BCNMISC;
|
|
|
|
if (ints & ATH9K_INT_GTT)
|
|
|
|
mask2 |= AR_IMR_S2_GTT;
|
|
|
|
if (ints & ATH9K_INT_CST)
|
|
|
|
mask2 |= AR_IMR_S2_CST;
|
|
|
|
}
|
|
|
|
|
2010-12-03 11:12:37 +08:00
|
|
|
ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
|
2010-04-16 05:39:06 +08:00
|
|
|
REG_WRITE(ah, AR_IMR, mask);
|
|
|
|
ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
|
|
|
|
AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
|
|
|
|
AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
|
|
|
|
ah->imrs2_reg |= mask2;
|
|
|
|
REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
|
|
|
|
|
|
|
|
if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
|
|
|
|
if (ints & ATH9K_INT_TIM_TIMER)
|
|
|
|
REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
|
|
|
|
else
|
|
|
|
REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
|
|
|
|
}
|
|
|
|
|
2011-02-21 22:02:41 +08:00
|
|
|
if (ints & ATH9K_INT_GLOBAL)
|
|
|
|
ath9k_hw_enable_interrupts(ah);
|
2010-04-16 05:39:06 +08:00
|
|
|
|
2010-11-09 03:54:47 +08:00
|
|
|
return;
|
2010-04-16 05:39:06 +08:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(ath9k_hw_set_interrupts);
|