2009-10-20 08:32:58 +08:00
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/*
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* arch/arm/mach-omap1/include/mach/hardware.h
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2012-09-01 01:59:07 +08:00
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*
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* Hardware definitions for TI OMAP processors and boards
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*
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* NOTE: Please put device driver specific defines into a separate header
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* file for each driver.
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*
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* Copyright (C) 2001 RidgeRun, Inc.
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* Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
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*
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* Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
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* and Dirk Behme <dirk.behme@de.bosch.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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2009-10-20 08:32:58 +08:00
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*/
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2012-09-01 01:59:07 +08:00
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#ifndef __ASM_ARCH_OMAP_HARDWARE_H
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#define __ASM_ARCH_OMAP_HARDWARE_H
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2012-02-25 02:34:35 +08:00
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2012-09-01 01:59:07 +08:00
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#include <asm/sizes.h>
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2012-02-25 02:34:35 +08:00
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#ifndef __ASSEMBLER__
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2012-09-01 01:59:07 +08:00
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#include <asm/types.h>
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2012-10-06 04:25:59 +08:00
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#include "../../mach-omap1/soc.h"
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2012-09-01 01:59:07 +08:00
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2012-02-25 02:34:35 +08:00
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/*
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* NOTE: Please use ioremap + __raw_read/write where possible instead of these
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*/
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extern u8 omap_readb(u32 pa);
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extern u16 omap_readw(u32 pa);
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extern u32 omap_readl(u32 pa);
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extern void omap_writeb(u8 v, u32 pa);
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extern void omap_writew(u16 v, u32 pa);
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extern void omap_writel(u32 v, u32 pa);
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2012-10-03 04:39:28 +08:00
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#include <mach/tc.h>
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2012-02-25 02:34:35 +08:00
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/* Almost all documentation for chip and board memory maps assumes
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* BM is clear. Most devel boards have a switch to control booting
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* from NOR flash (using external chipselect 3) rather than mask ROM,
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* which uses BM to interchange the physical CS0 and CS3 addresses.
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*/
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static inline u32 omap_cs0m_phys(void)
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{
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return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
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? OMAP_CS3_PHYS : 0;
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}
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static inline u32 omap_cs3_phys(void)
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{
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return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
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? 0 : OMAP_CS3_PHYS;
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}
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2012-09-01 01:59:07 +08:00
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#endif /* ifndef __ASSEMBLER__ */
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#include <plat/serial.h>
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/*
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* ---------------------------------------------------------------------------
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* Common definitions for all OMAP processors
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* NOTE: Put all processor or board specific parts to the special header
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* files.
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* ---------------------------------------------------------------------------
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*/
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/*
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* ----------------------------------------------------------------------------
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* Timers
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* ----------------------------------------------------------------------------
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*/
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#define OMAP_MPU_TIMER1_BASE (0xfffec500)
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#define OMAP_MPU_TIMER2_BASE (0xfffec600)
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#define OMAP_MPU_TIMER3_BASE (0xfffec700)
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#define MPU_TIMER_FREE (1 << 6)
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#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
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#define MPU_TIMER_AR (1 << 1)
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#define MPU_TIMER_ST (1 << 0)
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/*
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* ----------------------------------------------------------------------------
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* Clocks
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* ----------------------------------------------------------------------------
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*/
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#define CLKGEN_REG_BASE (0xfffece00)
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#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
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#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
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#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
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#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
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#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
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#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
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#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
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#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
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#define CK_RATEF 1
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#define CK_IDLEF 2
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#define CK_ENABLEF 4
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#define CK_SELECTF 8
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#define SETARM_IDLE_SHIFT
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/* DPLL control registers */
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#define DPLL_CTL (0xfffecf00)
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/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
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#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
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#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
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#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
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#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
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#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
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/*
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* ---------------------------------------------------------------------------
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* UPLD
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* ---------------------------------------------------------------------------
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*/
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#define ULPD_REG_BASE (0xfffe0800)
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#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
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#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
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#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
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# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
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# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
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#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
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# define SOFT_UDC_REQ (1 << 4)
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# define SOFT_USB_CLK_REQ (1 << 3)
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# define SOFT_DPLL_REQ (1 << 0)
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#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
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#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
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#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
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#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
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#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
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# define DIS_MMC2_DPLL_REQ (1 << 11)
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# define DIS_MMC1_DPLL_REQ (1 << 10)
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# define DIS_UART3_DPLL_REQ (1 << 9)
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# define DIS_UART2_DPLL_REQ (1 << 8)
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# define DIS_UART1_DPLL_REQ (1 << 7)
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# define DIS_USB_HOST_DPLL_REQ (1 << 6)
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#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
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#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
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/*
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* ---------------------------------------------------------------------------
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* Watchdog timer
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* ---------------------------------------------------------------------------
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*/
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/* Watchdog timer within the OMAP3.2 gigacell */
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#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
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#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
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#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
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#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
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#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
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/*
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* ---------------------------------------------------------------------------
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* Interrupts
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* ---------------------------------------------------------------------------
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*/
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#ifdef CONFIG_ARCH_OMAP1
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/*
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* XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
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* or something similar.. -- PFM.
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*/
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#define OMAP_IH1_BASE 0xfffecb00
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#define OMAP_IH2_BASE 0xfffe0000
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#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
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#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
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#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
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#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
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#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
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#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
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#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
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#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
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#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
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#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
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#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
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#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
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#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
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#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
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#define IRQ_ITR_REG_OFFSET 0x00
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#define IRQ_MIR_REG_OFFSET 0x04
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#define IRQ_SIR_IRQ_REG_OFFSET 0x10
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#define IRQ_SIR_FIQ_REG_OFFSET 0x14
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#define IRQ_CONTROL_REG_OFFSET 0x18
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#define IRQ_ISR_REG_OFFSET 0x9c
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#define IRQ_ILR0_REG_OFFSET 0x1c
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#define IRQ_GMR_REG_OFFSET 0xa0
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2012-02-25 02:34:35 +08:00
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#endif
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2012-09-01 01:59:07 +08:00
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/*
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* ----------------------------------------------------------------------------
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* System control registers
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* ----------------------------------------------------------------------------
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*/
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#define MOD_CONF_CTRL_0 0xfffe1080
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#define MOD_CONF_CTRL_1 0xfffe1110
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/*
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* ----------------------------------------------------------------------------
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* Pin multiplexing registers
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* ----------------------------------------------------------------------------
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*/
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#define FUNC_MUX_CTRL_0 0xfffe1000
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#define FUNC_MUX_CTRL_1 0xfffe1004
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#define FUNC_MUX_CTRL_2 0xfffe1008
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#define COMP_MODE_CTRL_0 0xfffe100c
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#define FUNC_MUX_CTRL_3 0xfffe1010
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#define FUNC_MUX_CTRL_4 0xfffe1014
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#define FUNC_MUX_CTRL_5 0xfffe1018
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#define FUNC_MUX_CTRL_6 0xfffe101C
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#define FUNC_MUX_CTRL_7 0xfffe1020
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#define FUNC_MUX_CTRL_8 0xfffe1024
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#define FUNC_MUX_CTRL_9 0xfffe1028
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#define FUNC_MUX_CTRL_A 0xfffe102C
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#define FUNC_MUX_CTRL_B 0xfffe1030
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#define FUNC_MUX_CTRL_C 0xfffe1034
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#define FUNC_MUX_CTRL_D 0xfffe1038
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#define PULL_DWN_CTRL_0 0xfffe1040
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#define PULL_DWN_CTRL_1 0xfffe1044
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#define PULL_DWN_CTRL_2 0xfffe1048
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#define PULL_DWN_CTRL_3 0xfffe104c
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#define PULL_DWN_CTRL_4 0xfffe10ac
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/* OMAP-1610 specific multiplexing registers */
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#define FUNC_MUX_CTRL_E 0xfffe1090
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#define FUNC_MUX_CTRL_F 0xfffe1094
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#define FUNC_MUX_CTRL_10 0xfffe1098
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#define FUNC_MUX_CTRL_11 0xfffe109c
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#define FUNC_MUX_CTRL_12 0xfffe10a0
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#define PU_PD_SEL_0 0xfffe10b4
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#define PU_PD_SEL_1 0xfffe10b8
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#define PU_PD_SEL_2 0xfffe10bc
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#define PU_PD_SEL_3 0xfffe10c0
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#define PU_PD_SEL_4 0xfffe10c4
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/* Timer32K for 1610 and 1710*/
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#define OMAP_TIMER32K_BASE 0xFFFBC400
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/*
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* ---------------------------------------------------------------------------
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* TIPB bus interface
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* ---------------------------------------------------------------------------
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*/
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#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
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#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
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#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
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#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
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/*
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* ----------------------------------------------------------------------------
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* MPUI interface
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* ----------------------------------------------------------------------------
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*/
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#define MPUI_BASE (0xfffec900)
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#define MPUI_CTRL (MPUI_BASE + 0x0)
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#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
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#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
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#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
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#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
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#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
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#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
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#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
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/*
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* ----------------------------------------------------------------------------
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* LED Pulse Generator
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* ----------------------------------------------------------------------------
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*/
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#define OMAP_LPG1_BASE 0xfffbd000
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#define OMAP_LPG2_BASE 0xfffbd800
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#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
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#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
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#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
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#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
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/*
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* ----------------------------------------------------------------------------
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* Pulse-Width Light
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* ----------------------------------------------------------------------------
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*/
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#define OMAP_PWL_BASE 0xfffb5800
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#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
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#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
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/*
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* ---------------------------------------------------------------------------
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* Processor specific defines
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* ---------------------------------------------------------------------------
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*/
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2012-09-01 08:04:35 +08:00
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#include "omap7xx.h"
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#include "omap1510.h"
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#include "omap16xx.h"
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2012-09-01 01:59:07 +08:00
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#endif /* __ASM_ARCH_OMAP_HARDWARE_H */
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