2014-12-05 14:26:31 +08:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2011 Freescale Semiconductor, Inc.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
|
|
* (at your option) any later version.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef __DW_HDMI__
|
|
|
|
#define __DW_HDMI__
|
|
|
|
|
|
|
|
#include <drm/drmP.h>
|
|
|
|
|
2015-03-27 20:50:58 +08:00
|
|
|
struct dw_hdmi;
|
|
|
|
|
2014-12-05 14:26:31 +08:00
|
|
|
enum {
|
|
|
|
DW_HDMI_RES_8,
|
|
|
|
DW_HDMI_RES_10,
|
|
|
|
DW_HDMI_RES_12,
|
|
|
|
DW_HDMI_RES_MAX,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum dw_hdmi_devtype {
|
|
|
|
IMX6Q_HDMI,
|
|
|
|
IMX6DL_HDMI,
|
2015-01-07 15:48:27 +08:00
|
|
|
RK3288_HDMI,
|
2014-12-05 14:26:31 +08:00
|
|
|
};
|
|
|
|
|
2017-01-17 16:29:06 +08:00
|
|
|
enum dw_hdmi_phy_type {
|
|
|
|
DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
|
|
|
|
DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
|
|
|
|
DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
|
|
|
|
DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
|
|
|
|
DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
|
|
|
|
DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
|
|
|
|
DW_HDMI_PHY_VENDOR_PHY = 0xfe,
|
|
|
|
};
|
|
|
|
|
2014-12-05 14:26:31 +08:00
|
|
|
struct dw_hdmi_mpll_config {
|
|
|
|
unsigned long mpixelclock;
|
|
|
|
struct {
|
|
|
|
u16 cpce;
|
|
|
|
u16 gmp;
|
|
|
|
} res[DW_HDMI_RES_MAX];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dw_hdmi_curr_ctrl {
|
|
|
|
unsigned long mpixelclock;
|
|
|
|
u16 curr[DW_HDMI_RES_MAX];
|
|
|
|
};
|
|
|
|
|
2015-04-01 11:56:10 +08:00
|
|
|
struct dw_hdmi_phy_config {
|
2014-12-05 14:26:31 +08:00
|
|
|
unsigned long mpixelclock;
|
|
|
|
u16 sym_ctr; /*clock symbol and transmitter control*/
|
|
|
|
u16 term; /*transmission termination value*/
|
2015-04-01 11:56:10 +08:00
|
|
|
u16 vlev_ctr; /* voltage level control */
|
2014-12-05 14:26:31 +08:00
|
|
|
};
|
|
|
|
|
2017-03-06 07:36:15 +08:00
|
|
|
struct dw_hdmi_phy_ops {
|
|
|
|
int (*init)(struct dw_hdmi *hdmi, void *data,
|
|
|
|
struct drm_display_mode *mode);
|
|
|
|
void (*disable)(struct dw_hdmi *hdmi, void *data);
|
|
|
|
enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
|
|
|
|
};
|
|
|
|
|
2014-12-05 14:26:31 +08:00
|
|
|
struct dw_hdmi_plat_data {
|
|
|
|
enum dw_hdmi_devtype dev_type;
|
2017-03-06 07:36:15 +08:00
|
|
|
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
|
|
|
|
struct drm_display_mode *mode);
|
|
|
|
|
|
|
|
/* Vendor PHY support */
|
|
|
|
const struct dw_hdmi_phy_ops *phy_ops;
|
|
|
|
const char *phy_name;
|
|
|
|
void *phy_data;
|
|
|
|
|
|
|
|
/* Synopsys PHY support */
|
2014-12-05 14:26:31 +08:00
|
|
|
const struct dw_hdmi_mpll_config *mpll_cfg;
|
|
|
|
const struct dw_hdmi_curr_ctrl *cur_ctr;
|
2015-04-01 11:56:10 +08:00
|
|
|
const struct dw_hdmi_phy_config *phy_config;
|
2014-12-05 14:26:31 +08:00
|
|
|
};
|
|
|
|
|
2017-01-17 16:29:00 +08:00
|
|
|
int dw_hdmi_probe(struct platform_device *pdev,
|
|
|
|
const struct dw_hdmi_plat_data *plat_data);
|
|
|
|
void dw_hdmi_remove(struct platform_device *pdev);
|
2017-01-17 16:28:52 +08:00
|
|
|
void dw_hdmi_unbind(struct device *dev);
|
2017-01-17 16:28:57 +08:00
|
|
|
int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
|
2014-12-05 14:26:31 +08:00
|
|
|
const struct dw_hdmi_plat_data *plat_data);
|
2015-03-27 20:50:58 +08:00
|
|
|
|
|
|
|
void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
|
2015-03-27 20:59:58 +08:00
|
|
|
void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
|
|
|
|
void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
|
2015-03-27 20:50:58 +08:00
|
|
|
|
2014-12-05 14:26:31 +08:00
|
|
|
#endif /* __IMX_HDMI_H__ */
|