mirror of https://gitee.com/openkylin/linux.git
74 lines
2.4 KiB
C
74 lines
2.4 KiB
C
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/* MN10300 On-board interrupt controller registers
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_INTCTL_REGS_H
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#define _ASM_INTCTL_REGS_H
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#include <asm/cpu-regs.h>
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#ifdef __KERNEL__
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/* interrupt controller registers */
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#define GxICR(X) __SYSREG(0xd4000000 + (X) * 4, u16) /* group irq ctrl regs */
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#define IAGR __SYSREG(0xd4000100, u16) /* intr acceptance group reg */
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#define IAGR_GN 0x00fc /* group number register
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* (documentation _has_ to be wrong)
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*/
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#define EXTMD __SYSREG(0xd4000200, u16) /* external pin intr spec reg */
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#define GET_XIRQ_TRIGGER(X) ((EXTMD >> ((X) * 2)) & 3)
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#define SET_XIRQ_TRIGGER(X,Y) \
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do { \
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u16 x = EXTMD; \
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x &= ~(3 << ((X) * 2)); \
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x |= ((Y) & 3) << ((X) * 2); \
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EXTMD = x; \
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} while (0)
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#define XIRQ_TRIGGER_LOWLEVEL 0
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#define XIRQ_TRIGGER_HILEVEL 1
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#define XIRQ_TRIGGER_NEGEDGE 2
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#define XIRQ_TRIGGER_POSEDGE 3
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/* non-maskable interrupt control */
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#define NMIIRQ 0
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#define NMICR GxICR(NMIIRQ) /* NMI control register */
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#define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */
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#define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */
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#define NMICR_ABUSERR 0x0008 /* async bus error flag */
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/* maskable interrupt control */
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#define GxICR_DETECT 0x0001 /* interrupt detect flag */
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#define GxICR_REQUEST 0x0010 /* interrupt request flag */
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#define GxICR_ENABLE 0x0100 /* interrupt enable flag */
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#define GxICR_LEVEL 0x7000 /* interrupt priority level */
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#define GxICR_LEVEL_0 0x0000 /* - level 0 */
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#define GxICR_LEVEL_1 0x1000 /* - level 1 */
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#define GxICR_LEVEL_2 0x2000 /* - level 2 */
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#define GxICR_LEVEL_3 0x3000 /* - level 3 */
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#define GxICR_LEVEL_4 0x4000 /* - level 4 */
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#define GxICR_LEVEL_5 0x5000 /* - level 5 */
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#define GxICR_LEVEL_6 0x6000 /* - level 6 */
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#define GxICR_LEVEL_SHIFT 12
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#ifndef __ASSEMBLY__
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extern void set_intr_level(int irq, u16 level);
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extern void set_intr_postackable(int irq);
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#endif
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/* external interrupts */
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#define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
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#endif /* __KERNEL__ */
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#endif /* _ASM_INTCTL_REGS_H */
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