2010-04-01 19:30:19 +08:00
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/*
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* arch/arm/mach-spear3xx/include/mach/spear310.h
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*
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* SPEAr310 Machine specific definition
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifdef CONFIG_MACH_SPEAR310
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#ifndef __MACH_SPEAR310_H
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#define __MACH_SPEAR310_H
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2011-03-07 12:57:08 +08:00
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#define SPEAR310_NAND_BASE UL(0x40000000)
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#define SPEAR310_FSMC_BASE UL(0x44000000)
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#define SPEAR310_UART1_BASE UL(0xB2000000)
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#define SPEAR310_UART2_BASE UL(0xB2080000)
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#define SPEAR310_UART3_BASE UL(0xB2100000)
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#define SPEAR310_UART4_BASE UL(0xB2180000)
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#define SPEAR310_UART5_BASE UL(0xB2200000)
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#define SPEAR310_HDLC_BASE UL(0xB2800000)
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#define SPEAR310_RS485_0_BASE UL(0xB3000000)
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#define SPEAR310_RS485_1_BASE UL(0xB3800000)
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#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
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2011-03-07 12:57:07 +08:00
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2010-05-03 16:24:30 +08:00
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/* Interrupt registers offsets and masks */
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#define INT_STS_MASK_REG 0x04
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#define SMII0_IRQ_MASK (1 << 0)
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#define SMII1_IRQ_MASK (1 << 1)
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#define SMII2_IRQ_MASK (1 << 2)
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#define SMII3_IRQ_MASK (1 << 3)
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#define WAKEUP_SMII0_IRQ_MASK (1 << 4)
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#define WAKEUP_SMII1_IRQ_MASK (1 << 5)
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#define WAKEUP_SMII2_IRQ_MASK (1 << 6)
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#define WAKEUP_SMII3_IRQ_MASK (1 << 7)
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#define UART1_IRQ_MASK (1 << 8)
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#define UART2_IRQ_MASK (1 << 9)
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#define UART3_IRQ_MASK (1 << 10)
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#define UART4_IRQ_MASK (1 << 11)
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#define UART5_IRQ_MASK (1 << 12)
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#define EMI_IRQ_MASK (1 << 13)
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#define TDM_HDLC_IRQ_MASK (1 << 14)
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#define RS485_0_IRQ_MASK (1 << 15)
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#define RS485_1_IRQ_MASK (1 << 16)
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#define SHIRQ_RAS1_MASK 0x000FF
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#define SHIRQ_RAS2_MASK 0x01F00
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#define SHIRQ_RAS3_MASK 0x02000
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#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000
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2010-04-01 19:30:19 +08:00
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#endif /* __MACH_SPEAR310_H */
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#endif /* CONFIG_MACH_SPEAR310 */
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