2005-11-08 05:05:42 +08:00
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/*
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* linux/arch/arm/mach-realview/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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2009-01-08 17:58:51 +08:00
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#include <linux/jiffies.h>
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2005-11-08 05:05:42 +08:00
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#include <linux/smp.h>
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2008-09-06 19:10:45 +08:00
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#include <linux/io.h>
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2005-11-08 05:05:42 +08:00
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#include <asm/cacheflush.h>
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2008-08-05 23:14:15 +08:00
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#include <mach/hardware.h>
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2008-02-05 00:39:00 +08:00
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#include <asm/mach-types.h>
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2009-07-24 19:33:00 +08:00
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#include <asm/unified.h>
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2005-11-08 05:05:42 +08:00
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2008-08-05 23:14:15 +08:00
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#include <mach/board-eb.h>
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#include <mach/board-pb11mp.h>
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2009-05-30 20:56:12 +08:00
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#include <mach/board-pbx.h>
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2009-05-16 18:41:53 +08:00
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#include <asm/smp_scu.h>
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2008-04-19 05:43:08 +08:00
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2008-12-01 22:54:58 +08:00
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#include "core.h"
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2005-11-08 05:05:42 +08:00
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extern void realview_secondary_startup(void);
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen"
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*/
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volatile int __cpuinitdata pen_release = -1;
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ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 18:53:12 +08:00
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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2008-12-01 22:54:58 +08:00
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static void __iomem *scu_base_addr(void)
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{
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if (machine_is_realview_eb_mp())
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return __io_address(REALVIEW_EB11MP_SCU_BASE);
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else if (machine_is_realview_pb11mp())
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return __io_address(REALVIEW_TC11MP_SCU_BASE);
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2009-05-30 20:56:12 +08:00
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else if (machine_is_realview_pbx() &&
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(core_tile_pbx11mp() || core_tile_pbxa9mp()))
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return __io_address(REALVIEW_PBX_TILE_SCU_BASE);
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2008-12-01 22:54:58 +08:00
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else
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return (void __iomem *)0;
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}
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2005-11-08 05:05:42 +08:00
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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2010-12-05 00:01:03 +08:00
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gic_secondary_init(0);
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2005-11-08 05:05:42 +08:00
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 18:53:12 +08:00
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write_pen_release(-1);
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2005-11-08 05:05:42 +08:00
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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ARM: Fix subtle race in CPU pen_release hotplug code
There is a subtle race in the CPU hotplug code, where a CPU which has
been offlined can online itself before being requested, which results
in things going astray on the next online/offline cycle.
What happens in the normal online/offline/online cycle is:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads -1
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
However, as the write of -1 of pen_release is not fully flushed back to
memory, and the checking of pen_release is done with caches disabled,
this allows CPU3 the opportunity to read the old value of pen_release:
CPU0 CPU3
requests boot of CPU3
pen_release = 3
flush cache line
checks pen_release, reads 3
starts boot
pen_release = -1
... requests CPU3 offline ...
... dies ...
checks pen_release, reads 3
starts boot
pen_release = -1
requests boot of CPU3
pen_release = 3
flush cache line
Fix this by grouping the write of pen_release along with its cache line
flushing code to ensure that any update to pen_release is always pushed
out to physical memory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-12-18 18:53:12 +08:00
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write_pen_release(cpu);
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2005-11-08 05:05:42 +08:00
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/*
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2010-12-03 03:10:01 +08:00
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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2005-11-08 05:05:42 +08:00
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*/
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2010-11-15 17:42:08 +08:00
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smp_cross_call(cpumask_of(cpu), 1);
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2005-11-08 05:05:42 +08:00
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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2007-02-16 02:05:29 +08:00
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smp_rmb();
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2005-11-08 05:05:42 +08:00
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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2006-02-16 19:08:09 +08:00
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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2010-12-03 02:09:37 +08:00
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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2006-02-16 19:08:09 +08:00
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2010-12-03 02:09:37 +08:00
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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2005-11-08 05:05:42 +08:00
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/* sanity check */
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if (ncores > NR_CPUS) {
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printk(KERN_WARNING
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"Realview: no. of cores (%d) greater than configured "
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"maximum of %d - clipping\n",
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ncores, NR_CPUS);
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ncores = NR_CPUS;
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}
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2010-12-03 18:42:58 +08:00
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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2005-11-08 05:05:42 +08:00
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2010-12-03 19:09:48 +08:00
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void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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2010-12-03 18:42:58 +08:00
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{
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int i;
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2005-11-08 05:05:42 +08:00
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/*
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2006-02-16 19:08:09 +08:00
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* Initialise the present map, which describes the set of CPUs
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* actually populated at the present time.
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2005-11-08 05:05:42 +08:00
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*/
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2006-02-16 19:08:09 +08:00
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for (i = 0; i < max_cpus; i++)
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2009-05-28 21:16:52 +08:00
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set_cpu_present(i, true);
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2005-11-08 05:05:42 +08:00
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2010-12-03 19:09:48 +08:00
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scu_enable(scu_base_addr());
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2005-11-08 05:05:42 +08:00
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/*
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2010-12-03 19:09:48 +08:00
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* Write the address of secondary startup into the
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* system-wide flags register. The BootMonitor waits
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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2005-11-08 05:05:42 +08:00
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*/
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2010-12-03 19:09:48 +08:00
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__raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
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__io_address(REALVIEW_SYS_FLAGSSET));
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2005-11-08 05:05:42 +08:00
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}
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