2019-06-03 13:44:50 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2017-07-13 21:32:27 +08:00
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/*
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* This file is part of STM32 Crypto driver for Linux.
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*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Lionel DEBIEVE <lionel.debieve@st.com> for STMicroelectronics.
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*/
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#include <linux/clk.h>
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#include <linux/crypto.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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2018-06-26 20:52:45 +08:00
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#include <linux/pm_runtime.h>
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2017-07-13 21:32:27 +08:00
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#include <linux/reset.h>
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#include <crypto/engine.h>
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#include <crypto/hash.h>
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#include <crypto/md5.h>
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#include <crypto/scatterwalk.h>
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#include <crypto/sha.h>
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#include <crypto/internal/hash.h>
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#define HASH_CR 0x00
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#define HASH_DIN 0x04
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#define HASH_STR 0x08
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#define HASH_IMR 0x20
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#define HASH_SR 0x24
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#define HASH_CSR(x) (0x0F8 + ((x) * 0x04))
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#define HASH_HREG(x) (0x310 + ((x) * 0x04))
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#define HASH_HWCFGR 0x3F0
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#define HASH_VER 0x3F4
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#define HASH_ID 0x3F8
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/* Control Register */
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#define HASH_CR_INIT BIT(2)
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#define HASH_CR_DMAE BIT(3)
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#define HASH_CR_DATATYPE_POS 4
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#define HASH_CR_MODE BIT(6)
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#define HASH_CR_MDMAT BIT(13)
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#define HASH_CR_DMAA BIT(14)
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#define HASH_CR_LKEY BIT(16)
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#define HASH_CR_ALGO_SHA1 0x0
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#define HASH_CR_ALGO_MD5 0x80
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#define HASH_CR_ALGO_SHA224 0x40000
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#define HASH_CR_ALGO_SHA256 0x40080
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/* Interrupt */
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#define HASH_DINIE BIT(0)
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#define HASH_DCIE BIT(1)
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/* Interrupt Mask */
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#define HASH_MASK_CALC_COMPLETION BIT(0)
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#define HASH_MASK_DATA_INPUT BIT(1)
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/* Context swap register */
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#define HASH_CSR_REGISTER_NUMBER 53
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/* Status Flags */
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#define HASH_SR_DATA_INPUT_READY BIT(0)
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#define HASH_SR_OUTPUT_READY BIT(1)
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#define HASH_SR_DMA_ACTIVE BIT(2)
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#define HASH_SR_BUSY BIT(3)
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/* STR Register */
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#define HASH_STR_NBLW_MASK GENMASK(4, 0)
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#define HASH_STR_DCAL BIT(8)
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#define HASH_FLAGS_INIT BIT(0)
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#define HASH_FLAGS_OUTPUT_READY BIT(1)
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#define HASH_FLAGS_CPU BIT(2)
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#define HASH_FLAGS_DMA_READY BIT(3)
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#define HASH_FLAGS_DMA_ACTIVE BIT(4)
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#define HASH_FLAGS_HMAC_INIT BIT(5)
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#define HASH_FLAGS_HMAC_FINAL BIT(6)
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#define HASH_FLAGS_HMAC_KEY BIT(7)
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#define HASH_FLAGS_FINAL BIT(15)
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#define HASH_FLAGS_FINUP BIT(16)
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#define HASH_FLAGS_ALGO_MASK GENMASK(21, 18)
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#define HASH_FLAGS_MD5 BIT(18)
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#define HASH_FLAGS_SHA1 BIT(19)
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#define HASH_FLAGS_SHA224 BIT(20)
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#define HASH_FLAGS_SHA256 BIT(21)
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#define HASH_FLAGS_ERRORS BIT(22)
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#define HASH_FLAGS_HMAC BIT(23)
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#define HASH_OP_UPDATE 1
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#define HASH_OP_FINAL 2
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enum stm32_hash_data_format {
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HASH_DATA_32_BITS = 0x0,
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HASH_DATA_16_BITS = 0x1,
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HASH_DATA_8_BITS = 0x2,
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HASH_DATA_1_BIT = 0x3
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};
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#define HASH_BUFLEN 256
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#define HASH_LONG_KEY 64
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#define HASH_MAX_KEY_SIZE (SHA256_BLOCK_SIZE * 8)
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#define HASH_QUEUE_LENGTH 16
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#define HASH_DMA_THRESHOLD 50
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2018-06-26 20:52:45 +08:00
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#define HASH_AUTOSUSPEND_DELAY 50
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2017-07-13 21:32:27 +08:00
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struct stm32_hash_ctx {
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2018-01-27 03:15:33 +08:00
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struct crypto_engine_ctx enginectx;
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2017-07-13 21:32:27 +08:00
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struct stm32_hash_dev *hdev;
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unsigned long flags;
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u8 key[HASH_MAX_KEY_SIZE];
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int keylen;
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};
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struct stm32_hash_request_ctx {
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struct stm32_hash_dev *hdev;
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unsigned long flags;
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unsigned long op;
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u8 digest[SHA256_DIGEST_SIZE] __aligned(sizeof(u32));
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size_t digcnt;
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size_t bufcnt;
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size_t buflen;
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/* DMA */
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struct scatterlist *sg;
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unsigned int offset;
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unsigned int total;
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struct scatterlist sg_key;
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dma_addr_t dma_addr;
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size_t dma_ct;
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int nents;
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u8 data_type;
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u8 buffer[HASH_BUFLEN] __aligned(sizeof(u32));
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/* Export Context */
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u32 *hw_context;
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};
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struct stm32_hash_algs_info {
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struct ahash_alg *algs_list;
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size_t size;
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};
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struct stm32_hash_pdata {
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struct stm32_hash_algs_info *algs_info;
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size_t algs_info_size;
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};
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struct stm32_hash_dev {
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struct list_head list;
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struct device *dev;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *io_base;
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phys_addr_t phys_base;
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u32 dma_mode;
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u32 dma_maxburst;
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struct ahash_request *req;
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struct crypto_engine *engine;
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int err;
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unsigned long flags;
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struct dma_chan *dma_lch;
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struct completion dma_completion;
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const struct stm32_hash_pdata *pdata;
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};
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struct stm32_hash_drv {
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struct list_head dev_list;
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spinlock_t lock; /* List protection access */
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};
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static struct stm32_hash_drv stm32_hash = {
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.dev_list = LIST_HEAD_INIT(stm32_hash.dev_list),
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.lock = __SPIN_LOCK_UNLOCKED(stm32_hash.lock),
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};
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static void stm32_hash_dma_callback(void *param);
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static inline u32 stm32_hash_read(struct stm32_hash_dev *hdev, u32 offset)
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{
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return readl_relaxed(hdev->io_base + offset);
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}
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static inline void stm32_hash_write(struct stm32_hash_dev *hdev,
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u32 offset, u32 value)
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{
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writel_relaxed(value, hdev->io_base + offset);
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}
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static inline int stm32_hash_wait_busy(struct stm32_hash_dev *hdev)
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{
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u32 status;
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return readl_relaxed_poll_timeout(hdev->io_base + HASH_SR, status,
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!(status & HASH_SR_BUSY), 10, 10000);
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}
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static void stm32_hash_set_nblw(struct stm32_hash_dev *hdev, int length)
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{
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u32 reg;
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reg = stm32_hash_read(hdev, HASH_STR);
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reg &= ~(HASH_STR_NBLW_MASK);
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reg |= (8U * ((length) % 4U));
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stm32_hash_write(hdev, HASH_STR, reg);
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}
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static int stm32_hash_write_key(struct stm32_hash_dev *hdev)
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{
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
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struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
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u32 reg;
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int keylen = ctx->keylen;
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void *key = ctx->key;
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if (keylen) {
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stm32_hash_set_nblw(hdev, keylen);
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while (keylen > 0) {
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stm32_hash_write(hdev, HASH_DIN, *(u32 *)key);
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keylen -= 4;
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key += 4;
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}
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reg = stm32_hash_read(hdev, HASH_STR);
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reg |= HASH_STR_DCAL;
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stm32_hash_write(hdev, HASH_STR, reg);
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return -EINPROGRESS;
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}
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return 0;
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}
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static void stm32_hash_write_ctrl(struct stm32_hash_dev *hdev)
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{
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struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
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struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
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u32 reg = HASH_CR_INIT;
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if (!(hdev->flags & HASH_FLAGS_INIT)) {
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switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
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case HASH_FLAGS_MD5:
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reg |= HASH_CR_ALGO_MD5;
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break;
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case HASH_FLAGS_SHA1:
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reg |= HASH_CR_ALGO_SHA1;
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break;
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case HASH_FLAGS_SHA224:
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reg |= HASH_CR_ALGO_SHA224;
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break;
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case HASH_FLAGS_SHA256:
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reg |= HASH_CR_ALGO_SHA256;
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break;
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default:
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reg |= HASH_CR_ALGO_MD5;
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}
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reg |= (rctx->data_type << HASH_CR_DATATYPE_POS);
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if (rctx->flags & HASH_FLAGS_HMAC) {
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hdev->flags |= HASH_FLAGS_HMAC;
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reg |= HASH_CR_MODE;
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if (ctx->keylen > HASH_LONG_KEY)
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reg |= HASH_CR_LKEY;
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}
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stm32_hash_write(hdev, HASH_IMR, HASH_DCIE);
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stm32_hash_write(hdev, HASH_CR, reg);
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hdev->flags |= HASH_FLAGS_INIT;
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dev_dbg(hdev->dev, "Write Control %x\n", reg);
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}
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}
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static void stm32_hash_append_sg(struct stm32_hash_request_ctx *rctx)
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{
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size_t count;
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while ((rctx->bufcnt < rctx->buflen) && rctx->total) {
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count = min(rctx->sg->length - rctx->offset, rctx->total);
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count = min(count, rctx->buflen - rctx->bufcnt);
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if (count <= 0) {
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if ((rctx->sg->length == 0) && !sg_is_last(rctx->sg)) {
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rctx->sg = sg_next(rctx->sg);
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continue;
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} else {
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break;
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}
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}
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scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, rctx->sg,
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rctx->offset, count, 0);
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rctx->bufcnt += count;
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rctx->offset += count;
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rctx->total -= count;
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if (rctx->offset == rctx->sg->length) {
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rctx->sg = sg_next(rctx->sg);
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if (rctx->sg)
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rctx->offset = 0;
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else
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rctx->total = 0;
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}
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}
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}
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static int stm32_hash_xmit_cpu(struct stm32_hash_dev *hdev,
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const u8 *buf, size_t length, int final)
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{
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unsigned int count, len32;
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const u32 *buffer = (const u32 *)buf;
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u32 reg;
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if (final)
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hdev->flags |= HASH_FLAGS_FINAL;
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len32 = DIV_ROUND_UP(length, sizeof(u32));
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2019-07-03 22:26:53 +08:00
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dev_dbg(hdev->dev, "%s: length: %zd, final: %x len32 %i\n",
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2017-07-13 21:32:27 +08:00
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__func__, length, final, len32);
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hdev->flags |= HASH_FLAGS_CPU;
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stm32_hash_write_ctrl(hdev);
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if (stm32_hash_wait_busy(hdev))
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return -ETIMEDOUT;
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if ((hdev->flags & HASH_FLAGS_HMAC) &&
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2019-06-28 19:26:54 +08:00
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(!(hdev->flags & HASH_FLAGS_HMAC_KEY))) {
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2017-07-13 21:32:27 +08:00
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hdev->flags |= HASH_FLAGS_HMAC_KEY;
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stm32_hash_write_key(hdev);
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if (stm32_hash_wait_busy(hdev))
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return -ETIMEDOUT;
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}
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for (count = 0; count < len32; count++)
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stm32_hash_write(hdev, HASH_DIN, buffer[count]);
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|
|
if (final) {
|
|
|
|
stm32_hash_set_nblw(hdev, length);
|
|
|
|
reg = stm32_hash_read(hdev, HASH_STR);
|
|
|
|
reg |= HASH_STR_DCAL;
|
|
|
|
stm32_hash_write(hdev, HASH_STR, reg);
|
|
|
|
if (hdev->flags & HASH_FLAGS_HMAC) {
|
|
|
|
if (stm32_hash_wait_busy(hdev))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
stm32_hash_write_key(hdev);
|
|
|
|
}
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_update_cpu(struct stm32_hash_dev *hdev)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
|
|
|
|
int bufcnt, err = 0, final;
|
|
|
|
|
|
|
|
dev_dbg(hdev->dev, "%s flags %lx\n", __func__, rctx->flags);
|
|
|
|
|
|
|
|
final = (rctx->flags & HASH_FLAGS_FINUP);
|
|
|
|
|
|
|
|
while ((rctx->total >= rctx->buflen) ||
|
|
|
|
(rctx->bufcnt + rctx->total >= rctx->buflen)) {
|
|
|
|
stm32_hash_append_sg(rctx);
|
|
|
|
bufcnt = rctx->bufcnt;
|
|
|
|
rctx->bufcnt = 0;
|
|
|
|
err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
stm32_hash_append_sg(rctx);
|
|
|
|
|
|
|
|
if (final) {
|
|
|
|
bufcnt = rctx->bufcnt;
|
|
|
|
rctx->bufcnt = 0;
|
|
|
|
err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt,
|
|
|
|
(rctx->flags & HASH_FLAGS_FINUP));
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_xmit_dma(struct stm32_hash_dev *hdev,
|
|
|
|
struct scatterlist *sg, int length, int mdma)
|
|
|
|
{
|
|
|
|
struct dma_async_tx_descriptor *in_desc;
|
|
|
|
dma_cookie_t cookie;
|
|
|
|
u32 reg;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
in_desc = dmaengine_prep_slave_sg(hdev->dma_lch, sg, 1,
|
|
|
|
DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT |
|
|
|
|
DMA_CTRL_ACK);
|
|
|
|
if (!in_desc) {
|
|
|
|
dev_err(hdev->dev, "dmaengine_prep_slave error\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
reinit_completion(&hdev->dma_completion);
|
|
|
|
in_desc->callback = stm32_hash_dma_callback;
|
|
|
|
in_desc->callback_param = hdev;
|
|
|
|
|
|
|
|
hdev->flags |= HASH_FLAGS_FINAL;
|
|
|
|
hdev->flags |= HASH_FLAGS_DMA_ACTIVE;
|
|
|
|
|
|
|
|
reg = stm32_hash_read(hdev, HASH_CR);
|
|
|
|
|
|
|
|
if (mdma)
|
|
|
|
reg |= HASH_CR_MDMAT;
|
|
|
|
else
|
|
|
|
reg &= ~HASH_CR_MDMAT;
|
|
|
|
|
|
|
|
reg |= HASH_CR_DMAE;
|
|
|
|
|
|
|
|
stm32_hash_write(hdev, HASH_CR, reg);
|
|
|
|
|
|
|
|
stm32_hash_set_nblw(hdev, length);
|
|
|
|
|
|
|
|
cookie = dmaengine_submit(in_desc);
|
|
|
|
err = dma_submit_error(cookie);
|
|
|
|
if (err)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
dma_async_issue_pending(hdev->dma_lch);
|
|
|
|
|
2019-06-28 19:26:55 +08:00
|
|
|
if (!wait_for_completion_timeout(&hdev->dma_completion,
|
|
|
|
msecs_to_jiffies(100)))
|
2017-07-13 21:32:27 +08:00
|
|
|
err = -ETIMEDOUT;
|
|
|
|
|
|
|
|
if (dma_async_is_tx_complete(hdev->dma_lch, cookie,
|
|
|
|
NULL, NULL) != DMA_COMPLETE)
|
|
|
|
err = -ETIMEDOUT;
|
|
|
|
|
|
|
|
if (err) {
|
|
|
|
dev_err(hdev->dev, "DMA Error %i\n", err);
|
|
|
|
dmaengine_terminate_all(hdev->dma_lch);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stm32_hash_dma_callback(void *param)
|
|
|
|
{
|
|
|
|
struct stm32_hash_dev *hdev = param;
|
|
|
|
|
|
|
|
complete(&hdev->dma_completion);
|
|
|
|
|
|
|
|
hdev->flags |= HASH_FLAGS_DMA_READY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_hmac_dma_send(struct stm32_hash_dev *hdev)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (ctx->keylen < HASH_DMA_THRESHOLD || (hdev->dma_mode == 1)) {
|
|
|
|
err = stm32_hash_write_key(hdev);
|
|
|
|
if (stm32_hash_wait_busy(hdev))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
} else {
|
|
|
|
if (!(hdev->flags & HASH_FLAGS_HMAC_KEY))
|
|
|
|
sg_init_one(&rctx->sg_key, ctx->key,
|
|
|
|
ALIGN(ctx->keylen, sizeof(u32)));
|
|
|
|
|
|
|
|
rctx->dma_ct = dma_map_sg(hdev->dev, &rctx->sg_key, 1,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (rctx->dma_ct == 0) {
|
|
|
|
dev_err(hdev->dev, "dma_map_sg error\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = stm32_hash_xmit_dma(hdev, &rctx->sg_key, ctx->keylen, 0);
|
|
|
|
|
|
|
|
dma_unmap_sg(hdev->dev, &rctx->sg_key, 1, DMA_TO_DEVICE);
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_dma_init(struct stm32_hash_dev *hdev)
|
|
|
|
{
|
|
|
|
struct dma_slave_config dma_conf;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
memset(&dma_conf, 0, sizeof(dma_conf));
|
|
|
|
|
|
|
|
dma_conf.direction = DMA_MEM_TO_DEV;
|
|
|
|
dma_conf.dst_addr = hdev->phys_base + HASH_DIN;
|
|
|
|
dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
dma_conf.src_maxburst = hdev->dma_maxburst;
|
|
|
|
dma_conf.dst_maxburst = hdev->dma_maxburst;
|
|
|
|
dma_conf.device_fc = false;
|
|
|
|
|
|
|
|
hdev->dma_lch = dma_request_slave_channel(hdev->dev, "in");
|
|
|
|
if (!hdev->dma_lch) {
|
|
|
|
dev_err(hdev->dev, "Couldn't acquire a slave DMA channel.\n");
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = dmaengine_slave_config(hdev->dma_lch, &dma_conf);
|
|
|
|
if (err) {
|
|
|
|
dma_release_channel(hdev->dma_lch);
|
|
|
|
hdev->dma_lch = NULL;
|
|
|
|
dev_err(hdev->dev, "Couldn't configure DMA slave.\n");
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
init_completion(&hdev->dma_completion);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_dma_send(struct stm32_hash_dev *hdev)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
|
|
|
|
struct scatterlist sg[1], *tsg;
|
crypto: stm32 - Try to fix hash padding
gcc warns that the length for the extra unaligned data in the hash
function may be used unaligned. In theory this could happen if
we pass a zero-length sg_list, or if sg_is_last() was never true:
In file included from drivers/crypto/stm32/stm32-hash.c:23:
drivers/crypto/stm32/stm32-hash.c: In function 'stm32_hash_one_request':
include/uapi/linux/kernel.h:12:49: error: 'ncp' may be used uninitialized in this function [-Werror=maybe-uninitialized]
#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
Neither of these can happen in practice, so the warning is harmless.
However while trying to suppress the warning, I noticed multiple
problems with that code:
- On big-endian kernels, we byte-swap the data like we do for
register accesses, however this is a data stream and almost
certainly needs to use a single writesl() instead of series
of writel() to give the correct hash.
- If the length is not a multiple of four bytes, we skip the
last word entirely, since we write the truncated length
using stm32_hash_set_nblw().
- If we change the code to round the length up rather than
down, the last bytes contain stale data, so it needs some
form of padding.
This tries to address all four problems, by correctly
initializing the length to zero, using endian-safe copy
functions, adding zero-padding and passing the padded length.
I have done no testing on this patch, so please review
carefully and if possible test with an unaligned length
and big-endian kernel builds.
Fixes: 8a1012d3f2ab ("crypto: stm32 - Support for STM32 HASH module")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-12 17:35:39 +08:00
|
|
|
int err = 0, len = 0, reg, ncp = 0;
|
2017-07-13 21:32:27 +08:00
|
|
|
unsigned int i;
|
crypto: stm32 - Try to fix hash padding
gcc warns that the length for the extra unaligned data in the hash
function may be used unaligned. In theory this could happen if
we pass a zero-length sg_list, or if sg_is_last() was never true:
In file included from drivers/crypto/stm32/stm32-hash.c:23:
drivers/crypto/stm32/stm32-hash.c: In function 'stm32_hash_one_request':
include/uapi/linux/kernel.h:12:49: error: 'ncp' may be used uninitialized in this function [-Werror=maybe-uninitialized]
#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
Neither of these can happen in practice, so the warning is harmless.
However while trying to suppress the warning, I noticed multiple
problems with that code:
- On big-endian kernels, we byte-swap the data like we do for
register accesses, however this is a data stream and almost
certainly needs to use a single writesl() instead of series
of writel() to give the correct hash.
- If the length is not a multiple of four bytes, we skip the
last word entirely, since we write the truncated length
using stm32_hash_set_nblw().
- If we change the code to round the length up rather than
down, the last bytes contain stale data, so it needs some
form of padding.
This tries to address all four problems, by correctly
initializing the length to zero, using endian-safe copy
functions, adding zero-padding and passing the padded length.
I have done no testing on this patch, so please review
carefully and if possible test with an unaligned length
and big-endian kernel builds.
Fixes: 8a1012d3f2ab ("crypto: stm32 - Support for STM32 HASH module")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-12 17:35:39 +08:00
|
|
|
u32 *buffer = (void *)rctx->buffer;
|
2017-07-13 21:32:27 +08:00
|
|
|
|
|
|
|
rctx->sg = hdev->req->src;
|
|
|
|
rctx->total = hdev->req->nbytes;
|
|
|
|
|
|
|
|
rctx->nents = sg_nents(rctx->sg);
|
|
|
|
|
|
|
|
if (rctx->nents < 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
stm32_hash_write_ctrl(hdev);
|
|
|
|
|
|
|
|
if (hdev->flags & HASH_FLAGS_HMAC) {
|
|
|
|
err = stm32_hash_hmac_dma_send(hdev);
|
|
|
|
if (err != -EINPROGRESS)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_sg(rctx->sg, tsg, rctx->nents, i) {
|
|
|
|
len = sg->length;
|
|
|
|
|
|
|
|
sg[0] = *tsg;
|
|
|
|
if (sg_is_last(sg)) {
|
|
|
|
if (hdev->dma_mode == 1) {
|
|
|
|
len = (ALIGN(sg->length, 16) - 16);
|
|
|
|
|
|
|
|
ncp = sg_pcopy_to_buffer(
|
|
|
|
rctx->sg, rctx->nents,
|
|
|
|
rctx->buffer, sg->length - len,
|
|
|
|
rctx->total - sg->length + len);
|
|
|
|
|
|
|
|
sg->length = len;
|
|
|
|
} else {
|
|
|
|
if (!(IS_ALIGNED(sg->length, sizeof(u32)))) {
|
|
|
|
len = sg->length;
|
|
|
|
sg->length = ALIGN(sg->length,
|
|
|
|
sizeof(u32));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
rctx->dma_ct = dma_map_sg(hdev->dev, sg, 1,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (rctx->dma_ct == 0) {
|
|
|
|
dev_err(hdev->dev, "dma_map_sg error\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = stm32_hash_xmit_dma(hdev, sg, len,
|
|
|
|
!sg_is_last(sg));
|
|
|
|
|
|
|
|
dma_unmap_sg(hdev->dev, sg, 1, DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
if (err == -ENOMEM)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hdev->dma_mode == 1) {
|
|
|
|
if (stm32_hash_wait_busy(hdev))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
reg = stm32_hash_read(hdev, HASH_CR);
|
|
|
|
reg &= ~HASH_CR_DMAE;
|
|
|
|
reg |= HASH_CR_DMAA;
|
|
|
|
stm32_hash_write(hdev, HASH_CR, reg);
|
|
|
|
|
crypto: stm32 - Try to fix hash padding
gcc warns that the length for the extra unaligned data in the hash
function may be used unaligned. In theory this could happen if
we pass a zero-length sg_list, or if sg_is_last() was never true:
In file included from drivers/crypto/stm32/stm32-hash.c:23:
drivers/crypto/stm32/stm32-hash.c: In function 'stm32_hash_one_request':
include/uapi/linux/kernel.h:12:49: error: 'ncp' may be used uninitialized in this function [-Werror=maybe-uninitialized]
#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
Neither of these can happen in practice, so the warning is harmless.
However while trying to suppress the warning, I noticed multiple
problems with that code:
- On big-endian kernels, we byte-swap the data like we do for
register accesses, however this is a data stream and almost
certainly needs to use a single writesl() instead of series
of writel() to give the correct hash.
- If the length is not a multiple of four bytes, we skip the
last word entirely, since we write the truncated length
using stm32_hash_set_nblw().
- If we change the code to round the length up rather than
down, the last bytes contain stale data, so it needs some
form of padding.
This tries to address all four problems, by correctly
initializing the length to zero, using endian-safe copy
functions, adding zero-padding and passing the padded length.
I have done no testing on this patch, so please review
carefully and if possible test with an unaligned length
and big-endian kernel builds.
Fixes: 8a1012d3f2ab ("crypto: stm32 - Support for STM32 HASH module")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-12 17:35:39 +08:00
|
|
|
if (ncp) {
|
|
|
|
memset(buffer + ncp, 0,
|
|
|
|
DIV_ROUND_UP(ncp, sizeof(u32)) - ncp);
|
|
|
|
writesl(hdev->io_base + HASH_DIN, buffer,
|
|
|
|
DIV_ROUND_UP(ncp, sizeof(u32)));
|
|
|
|
}
|
2018-01-29 22:28:11 +08:00
|
|
|
stm32_hash_set_nblw(hdev, ncp);
|
2017-07-13 21:32:27 +08:00
|
|
|
reg = stm32_hash_read(hdev, HASH_STR);
|
|
|
|
reg |= HASH_STR_DCAL;
|
|
|
|
stm32_hash_write(hdev, HASH_STR, reg);
|
|
|
|
err = -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hdev->flags & HASH_FLAGS_HMAC) {
|
|
|
|
if (stm32_hash_wait_busy(hdev))
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
err = stm32_hash_hmac_dma_send(hdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct stm32_hash_dev *stm32_hash_find_dev(struct stm32_hash_ctx *ctx)
|
|
|
|
{
|
|
|
|
struct stm32_hash_dev *hdev = NULL, *tmp;
|
|
|
|
|
|
|
|
spin_lock_bh(&stm32_hash.lock);
|
|
|
|
if (!ctx->hdev) {
|
|
|
|
list_for_each_entry(tmp, &stm32_hash.dev_list, list) {
|
|
|
|
hdev = tmp;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
ctx->hdev = hdev;
|
|
|
|
} else {
|
|
|
|
hdev = ctx->hdev;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_bh(&stm32_hash.lock);
|
|
|
|
|
|
|
|
return hdev;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool stm32_hash_dma_aligned_data(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct scatterlist *sg;
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (req->nbytes <= HASH_DMA_THRESHOLD)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (sg_nents(req->src) > 1) {
|
|
|
|
if (hdev->dma_mode == 1)
|
|
|
|
return false;
|
|
|
|
for_each_sg(req->src, sg, sg_nents(req->src), i) {
|
|
|
|
if ((!IS_ALIGNED(sg->length, sizeof(u32))) &&
|
|
|
|
(!sg_is_last(sg)))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (req->src->offset % 4)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_init(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
|
|
|
|
|
|
rctx->hdev = hdev;
|
|
|
|
|
|
|
|
rctx->flags = HASH_FLAGS_CPU;
|
|
|
|
|
|
|
|
rctx->digcnt = crypto_ahash_digestsize(tfm);
|
|
|
|
switch (rctx->digcnt) {
|
|
|
|
case MD5_DIGEST_SIZE:
|
|
|
|
rctx->flags |= HASH_FLAGS_MD5;
|
|
|
|
break;
|
|
|
|
case SHA1_DIGEST_SIZE:
|
|
|
|
rctx->flags |= HASH_FLAGS_SHA1;
|
|
|
|
break;
|
|
|
|
case SHA224_DIGEST_SIZE:
|
|
|
|
rctx->flags |= HASH_FLAGS_SHA224;
|
|
|
|
break;
|
|
|
|
case SHA256_DIGEST_SIZE:
|
|
|
|
rctx->flags |= HASH_FLAGS_SHA256;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
rctx->bufcnt = 0;
|
|
|
|
rctx->buflen = HASH_BUFLEN;
|
|
|
|
rctx->total = 0;
|
|
|
|
rctx->offset = 0;
|
|
|
|
rctx->data_type = HASH_DATA_8_BITS;
|
|
|
|
|
|
|
|
memset(rctx->buffer, 0, HASH_BUFLEN);
|
|
|
|
|
|
|
|
if (ctx->flags & HASH_FLAGS_HMAC)
|
|
|
|
rctx->flags |= HASH_FLAGS_HMAC;
|
|
|
|
|
|
|
|
dev_dbg(hdev->dev, "%s Flags %lx\n", __func__, rctx->flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_update_req(struct stm32_hash_dev *hdev)
|
|
|
|
{
|
|
|
|
return stm32_hash_update_cpu(hdev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_final_req(struct stm32_hash_dev *hdev)
|
|
|
|
{
|
|
|
|
struct ahash_request *req = hdev->req;
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
int err;
|
2018-01-29 22:28:10 +08:00
|
|
|
int buflen = rctx->bufcnt;
|
|
|
|
|
|
|
|
rctx->bufcnt = 0;
|
2017-07-13 21:32:27 +08:00
|
|
|
|
|
|
|
if (!(rctx->flags & HASH_FLAGS_CPU))
|
|
|
|
err = stm32_hash_dma_send(hdev);
|
|
|
|
else
|
2018-01-29 22:28:10 +08:00
|
|
|
err = stm32_hash_xmit_cpu(hdev, rctx->buffer, buflen, 1);
|
2017-07-13 21:32:27 +08:00
|
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stm32_hash_copy_hash(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
u32 *hash = (u32 *)rctx->digest;
|
|
|
|
unsigned int i, hashsize;
|
|
|
|
|
|
|
|
switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
|
|
|
|
case HASH_FLAGS_MD5:
|
|
|
|
hashsize = MD5_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
case HASH_FLAGS_SHA1:
|
|
|
|
hashsize = SHA1_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
case HASH_FLAGS_SHA224:
|
|
|
|
hashsize = SHA224_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
case HASH_FLAGS_SHA256:
|
|
|
|
hashsize = SHA256_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < hashsize / sizeof(u32); i++)
|
|
|
|
hash[i] = be32_to_cpu(stm32_hash_read(rctx->hdev,
|
|
|
|
HASH_HREG(i)));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_finish(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
if (!req->result)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
memcpy(req->result, rctx->digest, rctx->digcnt);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void stm32_hash_finish_req(struct ahash_request *req, int err)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
struct stm32_hash_dev *hdev = rctx->hdev;
|
|
|
|
|
|
|
|
if (!err && (HASH_FLAGS_FINAL & hdev->flags)) {
|
|
|
|
stm32_hash_copy_hash(req);
|
|
|
|
err = stm32_hash_finish(req);
|
|
|
|
hdev->flags &= ~(HASH_FLAGS_FINAL | HASH_FLAGS_CPU |
|
|
|
|
HASH_FLAGS_INIT | HASH_FLAGS_DMA_READY |
|
|
|
|
HASH_FLAGS_OUTPUT_READY | HASH_FLAGS_HMAC |
|
|
|
|
HASH_FLAGS_HMAC_INIT | HASH_FLAGS_HMAC_FINAL |
|
|
|
|
HASH_FLAGS_HMAC_KEY);
|
|
|
|
} else {
|
|
|
|
rctx->flags |= HASH_FLAGS_ERRORS;
|
|
|
|
}
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_mark_last_busy(hdev->dev);
|
|
|
|
pm_runtime_put_autosuspend(hdev->dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
crypto_finalize_hash_request(hdev->engine, req, err);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_hw_init(struct stm32_hash_dev *hdev,
|
|
|
|
struct stm32_hash_request_ctx *rctx)
|
|
|
|
{
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_get_sync(hdev->dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
if (!(HASH_FLAGS_INIT & hdev->flags)) {
|
|
|
|
stm32_hash_write(hdev, HASH_CR, HASH_CR_INIT);
|
|
|
|
stm32_hash_write(hdev, HASH_STR, 0);
|
|
|
|
stm32_hash_write(hdev, HASH_DIN, 0);
|
|
|
|
stm32_hash_write(hdev, HASH_IMR, 0);
|
|
|
|
hdev->err = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-01-27 03:15:33 +08:00
|
|
|
static int stm32_hash_one_request(struct crypto_engine *engine, void *areq);
|
|
|
|
static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev,
|
|
|
|
struct ahash_request *req)
|
|
|
|
{
|
|
|
|
return crypto_transfer_hash_request_to_engine(hdev->engine, req);
|
|
|
|
}
|
|
|
|
|
2018-01-27 03:15:33 +08:00
|
|
|
static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq)
|
2017-07-13 21:32:27 +08:00
|
|
|
{
|
2018-01-27 03:15:33 +08:00
|
|
|
struct ahash_request *req = container_of(areq, struct ahash_request,
|
|
|
|
base);
|
2017-07-13 21:32:27 +08:00
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
|
|
struct stm32_hash_request_ctx *rctx;
|
|
|
|
|
|
|
|
if (!hdev)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
hdev->req = req;
|
|
|
|
|
|
|
|
rctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
dev_dbg(hdev->dev, "processing new req, op: %lu, nbytes %d\n",
|
|
|
|
rctx->op, req->nbytes);
|
|
|
|
|
|
|
|
return stm32_hash_hw_init(hdev, rctx);
|
|
|
|
}
|
|
|
|
|
2018-01-27 03:15:33 +08:00
|
|
|
static int stm32_hash_one_request(struct crypto_engine *engine, void *areq)
|
2017-07-13 21:32:27 +08:00
|
|
|
{
|
2018-01-27 03:15:33 +08:00
|
|
|
struct ahash_request *req = container_of(areq, struct ahash_request,
|
|
|
|
base);
|
2017-07-13 21:32:27 +08:00
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
|
|
struct stm32_hash_request_ctx *rctx;
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
if (!hdev)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
hdev->req = req;
|
|
|
|
|
|
|
|
rctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
if (rctx->op == HASH_OP_UPDATE)
|
|
|
|
err = stm32_hash_update_req(hdev);
|
|
|
|
else if (rctx->op == HASH_OP_FINAL)
|
|
|
|
err = stm32_hash_final_req(hdev);
|
|
|
|
|
|
|
|
if (err != -EINPROGRESS)
|
|
|
|
/* done task will not finish it, so do it here */
|
|
|
|
stm32_hash_finish_req(req, err);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_enqueue(struct ahash_request *req, unsigned int op)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
|
|
|
|
struct stm32_hash_dev *hdev = ctx->hdev;
|
|
|
|
|
|
|
|
rctx->op = op;
|
|
|
|
|
|
|
|
return stm32_hash_handle_queue(hdev, req);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_update(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
if (!req->nbytes || !(rctx->flags & HASH_FLAGS_CPU))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
rctx->total = req->nbytes;
|
|
|
|
rctx->sg = req->src;
|
|
|
|
rctx->offset = 0;
|
|
|
|
|
|
|
|
if ((rctx->bufcnt + rctx->total < rctx->buflen)) {
|
|
|
|
stm32_hash_append_sg(rctx);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-11-07 06:41:52 +08:00
|
|
|
return stm32_hash_enqueue(req, HASH_OP_UPDATE);
|
2017-07-13 21:32:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_final(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
rctx->flags |= HASH_FLAGS_FINUP;
|
|
|
|
|
|
|
|
return stm32_hash_enqueue(req, HASH_OP_FINAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_finup(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
|
|
int err1, err2;
|
|
|
|
|
|
|
|
rctx->flags |= HASH_FLAGS_FINUP;
|
|
|
|
|
|
|
|
if (hdev->dma_lch && stm32_hash_dma_aligned_data(req))
|
|
|
|
rctx->flags &= ~HASH_FLAGS_CPU;
|
|
|
|
|
|
|
|
err1 = stm32_hash_update(req);
|
|
|
|
|
|
|
|
if (err1 == -EINPROGRESS || err1 == -EBUSY)
|
|
|
|
return err1;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* final() has to be always called to cleanup resources
|
|
|
|
* even if update() failed, except EINPROGRESS
|
|
|
|
*/
|
|
|
|
err2 = stm32_hash_final(req);
|
|
|
|
|
|
|
|
return err1 ?: err2;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_digest(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
return stm32_hash_init(req) ?: stm32_hash_finup(req);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_export(struct ahash_request *req, void *out)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
|
|
u32 *preg;
|
|
|
|
unsigned int i;
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_get_sync(hdev->dev);
|
|
|
|
|
2019-04-08 15:41:58 +08:00
|
|
|
while ((stm32_hash_read(hdev, HASH_SR) & HASH_SR_BUSY))
|
2017-07-13 21:32:27 +08:00
|
|
|
cpu_relax();
|
|
|
|
|
treewide: kmalloc() -> kmalloc_array()
The kmalloc() function has a 2-factor argument form, kmalloc_array(). This
patch replaces cases of:
kmalloc(a * b, gfp)
with:
kmalloc_array(a * b, gfp)
as well as handling cases of:
kmalloc(a * b * c, gfp)
with:
kmalloc(array3_size(a, b, c), gfp)
as it's slightly less ugly than:
kmalloc_array(array_size(a, b), c, gfp)
This does, however, attempt to ignore constant size factors like:
kmalloc(4 * 1024, gfp)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
The tools/ directory was manually excluded, since it has its own
implementation of kmalloc().
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
type TYPE;
expression THING, E;
@@
(
kmalloc(
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
kmalloc(
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression COUNT;
typedef u8;
typedef __u8;
@@
(
kmalloc(
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
kmalloc(
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
kmalloc(
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
kmalloc(
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
kmalloc(
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
kmalloc(
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
kmalloc(
- sizeof(char) * COUNT
+ COUNT
, ...)
|
kmalloc(
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
- kmalloc
+ kmalloc_array
(
- sizeof(TYPE) * (COUNT_ID)
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(TYPE) * COUNT_ID
+ COUNT_ID, sizeof(TYPE)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(TYPE) * (COUNT_CONST)
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(TYPE) * COUNT_CONST
+ COUNT_CONST, sizeof(TYPE)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(THING) * (COUNT_ID)
+ COUNT_ID, sizeof(THING)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(THING) * COUNT_ID
+ COUNT_ID, sizeof(THING)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(THING) * (COUNT_CONST)
+ COUNT_CONST, sizeof(THING)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(THING) * COUNT_CONST
+ COUNT_CONST, sizeof(THING)
, ...)
)
// 2-factor product, only identifiers.
@@
identifier SIZE, COUNT;
@@
- kmalloc
+ kmalloc_array
(
- SIZE * COUNT
+ COUNT, SIZE
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
kmalloc(
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kmalloc(
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kmalloc(
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kmalloc(
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
kmalloc(
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kmalloc(
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kmalloc(
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
kmalloc(
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
kmalloc(
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
kmalloc(
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
kmalloc(
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
kmalloc(
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
kmalloc(
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
kmalloc(
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
identifier STRIDE, SIZE, COUNT;
@@
(
kmalloc(
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kmalloc(
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kmalloc(
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kmalloc(
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kmalloc(
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kmalloc(
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kmalloc(
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
kmalloc(
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products,
// when they're not all constants...
@@
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
kmalloc(C1 * C2 * C3, ...)
|
kmalloc(
- (E1) * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
|
kmalloc(
- (E1) * (E2) * E3
+ array3_size(E1, E2, E3)
, ...)
|
kmalloc(
- (E1) * (E2) * (E3)
+ array3_size(E1, E2, E3)
, ...)
|
kmalloc(
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants,
// keeping sizeof() as the second factor argument.
@@
expression THING, E1, E2;
type TYPE;
constant C1, C2, C3;
@@
(
kmalloc(sizeof(THING) * C2, ...)
|
kmalloc(sizeof(TYPE) * C2, ...)
|
kmalloc(C1 * C2 * C3, ...)
|
kmalloc(C1 * C2, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(TYPE) * (E2)
+ E2, sizeof(TYPE)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(TYPE) * E2
+ E2, sizeof(TYPE)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(THING) * (E2)
+ E2, sizeof(THING)
, ...)
|
- kmalloc
+ kmalloc_array
(
- sizeof(THING) * E2
+ E2, sizeof(THING)
, ...)
|
- kmalloc
+ kmalloc_array
(
- (E1) * E2
+ E1, E2
, ...)
|
- kmalloc
+ kmalloc_array
(
- (E1) * (E2)
+ E1, E2
, ...)
|
- kmalloc
+ kmalloc_array
(
- E1 * E2
+ E1, E2
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-13 04:55:00 +08:00
|
|
|
rctx->hw_context = kmalloc_array(3 + HASH_CSR_REGISTER_NUMBER,
|
|
|
|
sizeof(u32),
|
|
|
|
GFP_KERNEL);
|
2017-07-13 21:32:27 +08:00
|
|
|
|
|
|
|
preg = rctx->hw_context;
|
|
|
|
|
|
|
|
*preg++ = stm32_hash_read(hdev, HASH_IMR);
|
|
|
|
*preg++ = stm32_hash_read(hdev, HASH_STR);
|
|
|
|
*preg++ = stm32_hash_read(hdev, HASH_CR);
|
|
|
|
for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
|
|
|
|
*preg++ = stm32_hash_read(hdev, HASH_CSR(i));
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_mark_last_busy(hdev->dev);
|
|
|
|
pm_runtime_put_autosuspend(hdev->dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
memcpy(out, rctx, sizeof(*rctx));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_import(struct ahash_request *req, const void *in)
|
|
|
|
{
|
|
|
|
struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
|
|
|
|
struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
|
|
|
|
const u32 *preg = in;
|
|
|
|
u32 reg;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
memcpy(rctx, in, sizeof(*rctx));
|
|
|
|
|
|
|
|
preg = rctx->hw_context;
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_get_sync(hdev->dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
stm32_hash_write(hdev, HASH_IMR, *preg++);
|
|
|
|
stm32_hash_write(hdev, HASH_STR, *preg++);
|
|
|
|
stm32_hash_write(hdev, HASH_CR, *preg);
|
|
|
|
reg = *preg++ | HASH_CR_INIT;
|
|
|
|
stm32_hash_write(hdev, HASH_CR, reg);
|
|
|
|
|
|
|
|
for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
|
|
|
|
stm32_hash_write(hdev, HASH_CSR(i), *preg++);
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_mark_last_busy(hdev->dev);
|
|
|
|
pm_runtime_put_autosuspend(hdev->dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
kfree(rctx->hw_context);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_setkey(struct crypto_ahash *tfm,
|
|
|
|
const u8 *key, unsigned int keylen)
|
|
|
|
{
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
|
|
|
|
|
|
|
|
if (keylen <= HASH_MAX_KEY_SIZE) {
|
|
|
|
memcpy(ctx->key, key, keylen);
|
|
|
|
ctx->keylen = keylen;
|
|
|
|
} else {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_cra_init_algs(struct crypto_tfm *tfm,
|
|
|
|
const char *algs_hmac_name)
|
|
|
|
{
|
|
|
|
struct stm32_hash_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
|
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
|
|
sizeof(struct stm32_hash_request_ctx));
|
|
|
|
|
|
|
|
ctx->keylen = 0;
|
|
|
|
|
|
|
|
if (algs_hmac_name)
|
|
|
|
ctx->flags |= HASH_FLAGS_HMAC;
|
|
|
|
|
2018-01-27 03:15:33 +08:00
|
|
|
ctx->enginectx.op.do_one_request = stm32_hash_one_request;
|
|
|
|
ctx->enginectx.op.prepare_request = stm32_hash_prepare_req;
|
|
|
|
ctx->enginectx.op.unprepare_request = NULL;
|
2017-07-13 21:32:27 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_cra_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
return stm32_hash_cra_init_algs(tfm, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_cra_md5_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
return stm32_hash_cra_init_algs(tfm, "md5");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_cra_sha1_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
return stm32_hash_cra_init_algs(tfm, "sha1");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_cra_sha224_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
return stm32_hash_cra_init_algs(tfm, "sha224");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_cra_sha256_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
return stm32_hash_cra_init_algs(tfm, "sha256");
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct stm32_hash_dev *hdev = dev_id;
|
|
|
|
|
|
|
|
if (HASH_FLAGS_CPU & hdev->flags) {
|
|
|
|
if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
|
|
|
|
hdev->flags &= ~HASH_FLAGS_OUTPUT_READY;
|
|
|
|
goto finish;
|
|
|
|
}
|
|
|
|
} else if (HASH_FLAGS_DMA_READY & hdev->flags) {
|
|
|
|
if (HASH_FLAGS_DMA_ACTIVE & hdev->flags) {
|
|
|
|
hdev->flags &= ~HASH_FLAGS_DMA_ACTIVE;
|
|
|
|
goto finish;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
|
|
|
finish:
|
2017-08-18 21:54:01 +08:00
|
|
|
/* Finish current request */
|
|
|
|
stm32_hash_finish_req(hdev->req, 0);
|
2017-07-13 21:32:27 +08:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t stm32_hash_irq_handler(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct stm32_hash_dev *hdev = dev_id;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
reg = stm32_hash_read(hdev, HASH_SR);
|
|
|
|
if (reg & HASH_SR_OUTPUT_READY) {
|
|
|
|
reg &= ~HASH_SR_OUTPUT_READY;
|
|
|
|
stm32_hash_write(hdev, HASH_SR, reg);
|
|
|
|
hdev->flags |= HASH_FLAGS_OUTPUT_READY;
|
2018-01-29 22:28:10 +08:00
|
|
|
/* Disable IT*/
|
|
|
|
stm32_hash_write(hdev, HASH_IMR, 0);
|
2017-07-13 21:32:27 +08:00
|
|
|
return IRQ_WAKE_THREAD;
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ahash_alg algs_md5_sha1[] = {
|
|
|
|
{
|
|
|
|
.init = stm32_hash_init,
|
|
|
|
.update = stm32_hash_update,
|
|
|
|
.final = stm32_hash_final,
|
|
|
|
.finup = stm32_hash_finup,
|
|
|
|
.digest = stm32_hash_digest,
|
|
|
|
.export = stm32_hash_export,
|
|
|
|
.import = stm32_hash_import,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = MD5_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "md5",
|
|
|
|
.cra_driver_name = "stm32-md5",
|
|
|
|
.cra_priority = 200,
|
2018-07-01 06:16:12 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
2017-07-13 21:32:27 +08:00
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
|
|
.cra_alignmask = 3,
|
|
|
|
.cra_init = stm32_hash_cra_init,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = stm32_hash_init,
|
|
|
|
.update = stm32_hash_update,
|
|
|
|
.final = stm32_hash_final,
|
|
|
|
.finup = stm32_hash_finup,
|
|
|
|
.digest = stm32_hash_digest,
|
|
|
|
.export = stm32_hash_export,
|
|
|
|
.import = stm32_hash_import,
|
|
|
|
.setkey = stm32_hash_setkey,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = MD5_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "hmac(md5)",
|
|
|
|
.cra_driver_name = "stm32-hmac-md5",
|
|
|
|
.cra_priority = 200,
|
2018-07-01 06:16:12 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
2017-07-13 21:32:27 +08:00
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = MD5_HMAC_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
|
|
.cra_alignmask = 3,
|
|
|
|
.cra_init = stm32_hash_cra_md5_init,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = stm32_hash_init,
|
|
|
|
.update = stm32_hash_update,
|
|
|
|
.final = stm32_hash_final,
|
|
|
|
.finup = stm32_hash_finup,
|
|
|
|
.digest = stm32_hash_digest,
|
|
|
|
.export = stm32_hash_export,
|
|
|
|
.import = stm32_hash_import,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "sha1",
|
|
|
|
.cra_driver_name = "stm32-sha1",
|
|
|
|
.cra_priority = 200,
|
2018-07-01 06:16:12 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
2017-07-13 21:32:27 +08:00
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
|
|
.cra_alignmask = 3,
|
|
|
|
.cra_init = stm32_hash_cra_init,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = stm32_hash_init,
|
|
|
|
.update = stm32_hash_update,
|
|
|
|
.final = stm32_hash_final,
|
|
|
|
.finup = stm32_hash_finup,
|
|
|
|
.digest = stm32_hash_digest,
|
|
|
|
.export = stm32_hash_export,
|
|
|
|
.import = stm32_hash_import,
|
|
|
|
.setkey = stm32_hash_setkey,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "hmac(sha1)",
|
|
|
|
.cra_driver_name = "stm32-hmac-sha1",
|
|
|
|
.cra_priority = 200,
|
2018-07-01 06:16:12 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
2017-07-13 21:32:27 +08:00
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
|
|
.cra_alignmask = 3,
|
|
|
|
.cra_init = stm32_hash_cra_sha1_init,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct ahash_alg algs_sha224_sha256[] = {
|
|
|
|
{
|
|
|
|
.init = stm32_hash_init,
|
|
|
|
.update = stm32_hash_update,
|
|
|
|
.final = stm32_hash_final,
|
|
|
|
.finup = stm32_hash_finup,
|
|
|
|
.digest = stm32_hash_digest,
|
|
|
|
.export = stm32_hash_export,
|
|
|
|
.import = stm32_hash_import,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA224_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "sha224",
|
|
|
|
.cra_driver_name = "stm32-sha224",
|
|
|
|
.cra_priority = 200,
|
2018-07-01 06:16:12 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
2017-07-13 21:32:27 +08:00
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
|
|
.cra_alignmask = 3,
|
|
|
|
.cra_init = stm32_hash_cra_init,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = stm32_hash_init,
|
|
|
|
.update = stm32_hash_update,
|
|
|
|
.final = stm32_hash_final,
|
|
|
|
.finup = stm32_hash_finup,
|
|
|
|
.digest = stm32_hash_digest,
|
|
|
|
.setkey = stm32_hash_setkey,
|
|
|
|
.export = stm32_hash_export,
|
|
|
|
.import = stm32_hash_import,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA224_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "hmac(sha224)",
|
|
|
|
.cra_driver_name = "stm32-hmac-sha224",
|
|
|
|
.cra_priority = 200,
|
2018-07-01 06:16:12 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
2017-07-13 21:32:27 +08:00
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
|
|
.cra_alignmask = 3,
|
|
|
|
.cra_init = stm32_hash_cra_sha224_init,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = stm32_hash_init,
|
|
|
|
.update = stm32_hash_update,
|
|
|
|
.final = stm32_hash_final,
|
|
|
|
.finup = stm32_hash_finup,
|
|
|
|
.digest = stm32_hash_digest,
|
|
|
|
.export = stm32_hash_export,
|
|
|
|
.import = stm32_hash_import,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "sha256",
|
|
|
|
.cra_driver_name = "stm32-sha256",
|
|
|
|
.cra_priority = 200,
|
2018-07-01 06:16:12 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
2017-07-13 21:32:27 +08:00
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
|
|
.cra_alignmask = 3,
|
|
|
|
.cra_init = stm32_hash_cra_init,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.init = stm32_hash_init,
|
|
|
|
.update = stm32_hash_update,
|
|
|
|
.final = stm32_hash_final,
|
|
|
|
.finup = stm32_hash_finup,
|
|
|
|
.digest = stm32_hash_digest,
|
|
|
|
.export = stm32_hash_export,
|
|
|
|
.import = stm32_hash_import,
|
|
|
|
.setkey = stm32_hash_setkey,
|
|
|
|
.halg = {
|
|
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
|
|
|
.statesize = sizeof(struct stm32_hash_request_ctx),
|
|
|
|
.base = {
|
|
|
|
.cra_name = "hmac(sha256)",
|
|
|
|
.cra_driver_name = "stm32-hmac-sha256",
|
|
|
|
.cra_priority = 200,
|
2018-07-01 06:16:12 +08:00
|
|
|
.cra_flags = CRYPTO_ALG_ASYNC |
|
2017-07-13 21:32:27 +08:00
|
|
|
CRYPTO_ALG_KERN_DRIVER_ONLY,
|
|
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
|
|
.cra_ctxsize = sizeof(struct stm32_hash_ctx),
|
|
|
|
.cra_alignmask = 3,
|
|
|
|
.cra_init = stm32_hash_cra_sha256_init,
|
|
|
|
.cra_module = THIS_MODULE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static int stm32_hash_register_algs(struct stm32_hash_dev *hdev)
|
|
|
|
{
|
|
|
|
unsigned int i, j;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
for (i = 0; i < hdev->pdata->algs_info_size; i++) {
|
|
|
|
for (j = 0; j < hdev->pdata->algs_info[i].size; j++) {
|
|
|
|
err = crypto_register_ahash(
|
|
|
|
&hdev->pdata->algs_info[i].algs_list[j]);
|
|
|
|
if (err)
|
|
|
|
goto err_algs;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err_algs:
|
|
|
|
dev_err(hdev->dev, "Algo %d : %d failed\n", i, j);
|
|
|
|
for (; i--; ) {
|
|
|
|
for (; j--;)
|
|
|
|
crypto_unregister_ahash(
|
|
|
|
&hdev->pdata->algs_info[i].algs_list[j]);
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_unregister_algs(struct stm32_hash_dev *hdev)
|
|
|
|
{
|
|
|
|
unsigned int i, j;
|
|
|
|
|
|
|
|
for (i = 0; i < hdev->pdata->algs_info_size; i++) {
|
|
|
|
for (j = 0; j < hdev->pdata->algs_info[i].size; j++)
|
|
|
|
crypto_unregister_ahash(
|
|
|
|
&hdev->pdata->algs_info[i].algs_list[j]);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f4[] = {
|
|
|
|
{
|
|
|
|
.algs_list = algs_md5_sha1,
|
|
|
|
.size = ARRAY_SIZE(algs_md5_sha1),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct stm32_hash_pdata stm32_hash_pdata_stm32f4 = {
|
|
|
|
.algs_info = stm32_hash_algs_info_stm32f4,
|
|
|
|
.algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f4),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f7[] = {
|
|
|
|
{
|
|
|
|
.algs_list = algs_md5_sha1,
|
|
|
|
.size = ARRAY_SIZE(algs_md5_sha1),
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.algs_list = algs_sha224_sha256,
|
|
|
|
.size = ARRAY_SIZE(algs_sha224_sha256),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct stm32_hash_pdata stm32_hash_pdata_stm32f7 = {
|
|
|
|
.algs_info = stm32_hash_algs_info_stm32f7,
|
|
|
|
.algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f7),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id stm32_hash_of_match[] = {
|
|
|
|
{
|
|
|
|
.compatible = "st,stm32f456-hash",
|
|
|
|
.data = &stm32_hash_pdata_stm32f4,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "st,stm32f756-hash",
|
|
|
|
.data = &stm32_hash_pdata_stm32f7,
|
|
|
|
},
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(of, stm32_hash_of_match);
|
|
|
|
|
|
|
|
static int stm32_hash_get_of_match(struct stm32_hash_dev *hdev,
|
|
|
|
struct device *dev)
|
|
|
|
{
|
2017-09-21 02:31:40 +08:00
|
|
|
hdev->pdata = of_device_get_match_data(dev);
|
|
|
|
if (!hdev->pdata) {
|
2017-07-13 21:32:27 +08:00
|
|
|
dev_err(dev, "no compatible OF match\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2018-01-29 22:28:09 +08:00
|
|
|
if (of_property_read_u32(dev->of_node, "dma-maxburst",
|
|
|
|
&hdev->dma_maxburst)) {
|
|
|
|
dev_info(dev, "dma-maxburst not specified, using 0\n");
|
|
|
|
hdev->dma_maxburst = 0;
|
|
|
|
}
|
2017-07-13 21:32:27 +08:00
|
|
|
|
2018-01-29 22:28:09 +08:00
|
|
|
return 0;
|
2017-07-13 21:32:27 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct stm32_hash_dev *hdev;
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct resource *res;
|
|
|
|
int ret, irq;
|
|
|
|
|
|
|
|
hdev = devm_kzalloc(dev, sizeof(*hdev), GFP_KERNEL);
|
|
|
|
if (!hdev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
hdev->io_base = devm_ioremap_resource(dev, res);
|
|
|
|
if (IS_ERR(hdev->io_base))
|
|
|
|
return PTR_ERR(hdev->io_base);
|
|
|
|
|
|
|
|
hdev->phys_base = res->start;
|
|
|
|
|
|
|
|
ret = stm32_hash_get_of_match(hdev, dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
2019-07-31 02:15:05 +08:00
|
|
|
if (irq < 0)
|
2017-07-13 21:32:27 +08:00
|
|
|
return irq;
|
|
|
|
|
|
|
|
ret = devm_request_threaded_irq(dev, irq, stm32_hash_irq_handler,
|
|
|
|
stm32_hash_irq_thread, IRQF_ONESHOT,
|
|
|
|
dev_name(dev), hdev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Cannot grab IRQ\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
hdev->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(hdev->clk)) {
|
|
|
|
dev_err(dev, "failed to get clock for hash (%lu)\n",
|
|
|
|
PTR_ERR(hdev->clk));
|
|
|
|
return PTR_ERR(hdev->clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(hdev->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "failed to enable hash clock (%d)\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_set_autosuspend_delay(dev, HASH_AUTOSUSPEND_DELAY);
|
|
|
|
pm_runtime_use_autosuspend(dev);
|
|
|
|
|
|
|
|
pm_runtime_get_noresume(dev);
|
|
|
|
pm_runtime_set_active(dev);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
hdev->rst = devm_reset_control_get(&pdev->dev, NULL);
|
|
|
|
if (!IS_ERR(hdev->rst)) {
|
|
|
|
reset_control_assert(hdev->rst);
|
|
|
|
udelay(2);
|
|
|
|
reset_control_deassert(hdev->rst);
|
|
|
|
}
|
|
|
|
|
|
|
|
hdev->dev = dev;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, hdev);
|
|
|
|
|
|
|
|
ret = stm32_hash_dma_init(hdev);
|
|
|
|
if (ret)
|
|
|
|
dev_dbg(dev, "DMA mode not available\n");
|
|
|
|
|
|
|
|
spin_lock(&stm32_hash.lock);
|
|
|
|
list_add_tail(&hdev->list, &stm32_hash.dev_list);
|
|
|
|
spin_unlock(&stm32_hash.lock);
|
|
|
|
|
|
|
|
/* Initialize crypto engine */
|
|
|
|
hdev->engine = crypto_engine_alloc_init(dev, 1);
|
|
|
|
if (!hdev->engine) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_engine;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = crypto_engine_start(hdev->engine);
|
|
|
|
if (ret)
|
|
|
|
goto err_engine_start;
|
|
|
|
|
|
|
|
hdev->dma_mode = stm32_hash_read(hdev, HASH_HWCFGR);
|
|
|
|
|
|
|
|
/* Register algos */
|
|
|
|
ret = stm32_hash_register_algs(hdev);
|
|
|
|
if (ret)
|
|
|
|
goto err_algs;
|
|
|
|
|
|
|
|
dev_info(dev, "Init HASH done HW ver %x DMA mode %u\n",
|
|
|
|
stm32_hash_read(hdev, HASH_VER), hdev->dma_mode);
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_put_sync(dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_algs:
|
|
|
|
err_engine_start:
|
|
|
|
crypto_engine_exit(hdev->engine);
|
|
|
|
err_engine:
|
|
|
|
spin_lock(&stm32_hash.lock);
|
|
|
|
list_del(&hdev->list);
|
|
|
|
spin_unlock(&stm32_hash.lock);
|
|
|
|
|
|
|
|
if (hdev->dma_lch)
|
|
|
|
dma_release_channel(hdev->dma_lch);
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_disable(dev);
|
|
|
|
pm_runtime_put_noidle(dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
clk_disable_unprepare(hdev->clk);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_remove(struct platform_device *pdev)
|
|
|
|
{
|
2019-02-18 22:49:00 +08:00
|
|
|
struct stm32_hash_dev *hdev;
|
2018-06-26 20:52:45 +08:00
|
|
|
int ret;
|
2017-07-13 21:32:27 +08:00
|
|
|
|
|
|
|
hdev = platform_get_drvdata(pdev);
|
|
|
|
if (!hdev)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
ret = pm_runtime_get_sync(hdev->dev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
stm32_hash_unregister_algs(hdev);
|
|
|
|
|
|
|
|
crypto_engine_exit(hdev->engine);
|
|
|
|
|
|
|
|
spin_lock(&stm32_hash.lock);
|
|
|
|
list_del(&hdev->list);
|
|
|
|
spin_unlock(&stm32_hash.lock);
|
|
|
|
|
|
|
|
if (hdev->dma_lch)
|
|
|
|
dma_release_channel(hdev->dma_lch);
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
pm_runtime_disable(hdev->dev);
|
|
|
|
pm_runtime_put_noidle(hdev->dev);
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
clk_disable_unprepare(hdev->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-06-26 20:52:45 +08:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int stm32_hash_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct stm32_hash_dev *hdev = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
clk_disable_unprepare(hdev->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int stm32_hash_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct stm32_hash_dev *hdev = dev_get_drvdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(hdev->clk);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(hdev->dev, "Failed to prepare_enable clock\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct dev_pm_ops stm32_hash_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
|
|
pm_runtime_force_resume)
|
|
|
|
SET_RUNTIME_PM_OPS(stm32_hash_runtime_suspend,
|
|
|
|
stm32_hash_runtime_resume, NULL)
|
|
|
|
};
|
|
|
|
|
2017-07-13 21:32:27 +08:00
|
|
|
static struct platform_driver stm32_hash_driver = {
|
|
|
|
.probe = stm32_hash_probe,
|
|
|
|
.remove = stm32_hash_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "stm32-hash",
|
2018-06-26 20:52:45 +08:00
|
|
|
.pm = &stm32_hash_pm_ops,
|
2017-07-13 21:32:27 +08:00
|
|
|
.of_match_table = stm32_hash_of_match,
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(stm32_hash_driver);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("STM32 SHA1/224/256 & MD5 (HMAC) hw accelerator driver");
|
|
|
|
MODULE_AUTHOR("Lionel Debieve <lionel.debieve@st.com>");
|
|
|
|
MODULE_LICENSE("GPL v2");
|