2011-10-13 00:06:56 +08:00
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* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
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Required properties:
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2015-03-12 22:54:26 +08:00
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- compatible: Should be "atmel,<chip>-usart" or "atmel,<chip>-dbgu"
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2011-10-13 00:06:56 +08:00
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The compatible <chip> indicated will be the first SoC to support an
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additional mode or an USART new feature.
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2015-03-12 22:54:26 +08:00
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For the dbgu UART, use "atmel,<chip>-dbgu", "atmel,<chip>-usart"
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2011-10-13 00:06:56 +08:00
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- reg: Should contain registers location and length
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- interrupts: Should contain interrupt
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2013-12-18 00:22:20 +08:00
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- clock-names: tuple listing input clock names.
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Required elements: "usart"
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- clocks: phandles to input clocks.
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2011-10-13 00:06:56 +08:00
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Optional properties:
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- atmel,use-dma-rx: use of PDC or DMA for receiving data
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- atmel,use-dma-tx: use of PDC or DMA for transmitting data
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2014-05-14 02:20:44 +08:00
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- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively.
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It will use specified PIO instead of the peripheral function pin for the USART feature.
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If unsure, don't specify this property.
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2013-07-22 16:30:31 +08:00
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- add dma bindings for dma transfer:
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- dmas: DMA specifier, consisting of a phandle to DMA controller node,
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memory peripheral interface and USART DMA channel ID, FIFO configuration.
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Refer to dma.txt and atmel-dma.txt for details.
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- dma-names: "rx" for RX channel, "tx" for TX channel.
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ARM: at91/dt: add a new DT property to support FIFOs on Atmel USARTs
This patch adds a new DT property, "atmel,fifo-size", to enable and set
the maximum number of data the RX and TX FIFOs can store on FIFO capable
USARTs.
Please be aware that the VERSION register can not be used to guess the
size of FIFOs. Indeed, for a given hardware version, the USARTs can be
integrated on Atmel SoCs with different FIFO sizes. Also the
"atmel,fifo-size" property is optional as older USARTs don't embed FIFO at
all.
Besides, the FIFO size can not be read or guessed from other registers:
When designing the FIFO feature, no dedicated registers were added to
store this size. Unsed spaces in the I/O register range are limited and
better reserved for future usages. Instead, the FIFO size of each
peripheral is documented in the programmer datasheet.
Finally, on a given SoC, there can be several instances of USART with
different FIFO sizes. This explain why we'd rather use a dedicated DT
property than use the "compatible" property.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-02 21:18:09 +08:00
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- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
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capable USARTs.
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2017-09-20 20:29:36 +08:00
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- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt
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2011-10-13 00:06:56 +08:00
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<chip> compatible description:
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- at91rm9200: legacy USART support
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- at91sam9260: generic USART implementation for SAM9 SoCs
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Example:
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2013-07-22 16:30:31 +08:00
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- use PDC:
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2011-10-13 00:06:56 +08:00
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usart0: serial@fff8c000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xfff8c000 0x4000>;
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interrupts = <7>;
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2013-12-18 00:22:20 +08:00
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clocks = <&usart0_clk>;
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clock-names = "usart";
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2011-10-13 00:06:56 +08:00
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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2014-05-14 02:20:41 +08:00
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rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
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2014-05-14 02:20:44 +08:00
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cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
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dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>;
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dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
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dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>;
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rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>;
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2011-10-13 00:06:56 +08:00
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};
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2013-07-22 16:30:31 +08:00
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- use DMA:
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usart0: serial@f001c000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf001c000 0x100>;
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interrupts = <12 4 5>;
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2013-12-18 00:22:20 +08:00
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clocks = <&usart0_clk>;
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clock-names = "usart";
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2013-07-22 16:30:31 +08:00
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atmel,use-dma-rx;
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atmel,use-dma-tx;
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dmas = <&dma0 2 0x3>,
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<&dma0 2 0x204>;
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dma-names = "tx", "rx";
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ARM: at91/dt: add a new DT property to support FIFOs on Atmel USARTs
This patch adds a new DT property, "atmel,fifo-size", to enable and set
the maximum number of data the RX and TX FIFOs can store on FIFO capable
USARTs.
Please be aware that the VERSION register can not be used to guess the
size of FIFOs. Indeed, for a given hardware version, the USARTs can be
integrated on Atmel SoCs with different FIFO sizes. Also the
"atmel,fifo-size" property is optional as older USARTs don't embed FIFO at
all.
Besides, the FIFO size can not be read or guessed from other registers:
When designing the FIFO feature, no dedicated registers were added to
store this size. Unsed spaces in the I/O register range are limited and
better reserved for future usages. Instead, the FIFO size of each
peripheral is documented in the programmer datasheet.
Finally, on a given SoC, there can be several instances of USART with
different FIFO sizes. This explain why we'd rather use a dedicated DT
property than use the "compatible" property.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-07-02 21:18:09 +08:00
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atmel,fifo-size = <32>;
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2013-07-22 16:30:31 +08:00
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};
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