mirror of https://gitee.com/openkylin/linux.git
ARM: davinci: da8xx: add usb phy clocks
Up to this point, the USB phy clock configuration was handled manually in the board files and in the usb drivers. This adds proper clocks so that the usb drivers can use clk_get and clk_enable and not have to worry about the details. Also, the related code is removed from the board files and replaced with the new clock registration functions. This also removes the #if IS_ENABLED(CONFIG_USB_MUSB_HDRC) around the musb declaration and renames the musb platform device so that we can reference it from the usb20 clock even if the musb device is not used. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Axel Haslam <ahaslam@baylibre.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
David Lechner
Sekhar Nori
parent
3b996e5f8f
commit
0004b02a68
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@ -18,7 +18,6 @@
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#include <linux/i2c.h>
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#include <linux/i2c/pcf857x.h>
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#include <linux/platform_data/at24.h>
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#include <linux/mfd/da8xx-cfgchip.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/spi/spi.h>
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@ -108,30 +107,18 @@ static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id)
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static __init void da830_evm_usb_init(void)
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{
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u32 cfgchip2;
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int ret;
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/*
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* Set up USB clock in the CFGCHIP2 register.
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* FYI: CFGCHIP2 is 0x0000ef00 initially.
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*/
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cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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/* USB2.0 PHY reference clock is 24 MHz */
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cfgchip2 &= ~CFGCHIP2_REFFREQ_MASK;
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cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
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/*
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* Select internal reference clock for USB 2.0 PHY
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* and use it as a clock source for USB 1.1 PHY
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* (this is the default setting anyway).
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*/
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cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
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cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX;
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__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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/* USB_REFCLKIN is not used. */
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ret = da8xx_register_usb20_phy_clk(false);
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if (ret)
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pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
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__func__, ret);
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ret = da8xx_register_usb11_phy_clk(false);
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if (ret)
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pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
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__func__, ret);
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ret = da8xx_register_usb_phy();
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if (ret)
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@ -13,7 +13,6 @@
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/gpio.h>
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#include <linux/mfd/da8xx-cfgchip.h>
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#include <linux/platform_data/gpio-davinci.h>
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#include <linux/regulator/machine.h>
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@ -245,7 +244,6 @@ static irqreturn_t omapl138_hawk_usb_ocic_irq(int irq, void *dev_id)
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static __init void omapl138_hawk_usb_init(void)
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{
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int ret;
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u32 cfgchip2;
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ret = davinci_cfg_reg_list(da850_hawk_usb11_pins);
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if (ret) {
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@ -253,12 +251,15 @@ static __init void omapl138_hawk_usb_init(void)
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return;
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}
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/* Setup the Ref. clock frequency for the HAWK at 24 MHz. */
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ret = da8xx_register_usb20_phy_clk(false);
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if (ret)
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pr_warn("%s: USB 2.0 PHY CLK registration failed: %d\n",
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__func__, ret);
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cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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cfgchip2 &= ~CFGCHIP2_REFFREQ_MASK;
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cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
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__raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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ret = da8xx_register_usb11_phy_clk(false);
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if (ret)
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pr_warn("%s: USB 1.1 PHY CLK registration failed: %d\n",
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__func__, ret);
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ret = da8xx_register_usb_phy();
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if (ret)
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@ -92,6 +92,9 @@ int da8xx_register_watchdog(void);
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int da8xx_register_usb_phy(void);
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int da8xx_register_usb20(unsigned mA, unsigned potpgt);
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int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
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int da8xx_register_usb_refclkin(int rate);
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int da8xx_register_usb20_phy_clk(bool use_usb_refclkin);
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int da8xx_register_usb11_phy_clk(bool use_usb_refclkin);
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int da8xx_register_emac(void);
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int da8xx_register_uio_pruss(void);
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int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
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@ -1,24 +1,38 @@
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/*
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* DA8xx USB
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/mfd/da8xx-cfgchip.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_data/usb-davinci.h>
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#include <linux/platform_device.h>
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#include <linux/usb/musb.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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#include <mach/cputype.h>
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#include <mach/da8xx.h>
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#include <mach/irqs.h>
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#include "clock.h"
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#define DA8XX_USB0_BASE 0x01e00000
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#define DA8XX_USB1_BASE 0x01e25000
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static struct platform_device da8xx_usb_phy = {
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.name = "da8xx-usb-phy",
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.id = -1,
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.dev = {
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/*
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* Setting init_name so that clock lookup will work in
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* da8xx_register_usb11_phy_clk() even if this device is not
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* registered yet.
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*/
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.init_name = "da8xx-usb-phy",
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},
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};
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int __init da8xx_register_usb_phy(void)
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@ -26,8 +40,6 @@ int __init da8xx_register_usb_phy(void)
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return platform_device_register(&da8xx_usb_phy);
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}
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#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
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static struct musb_hdrc_config musb_config = {
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.multipoint = true,
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.num_eps = 5,
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@ -56,10 +68,15 @@ static struct resource da8xx_usb20_resources[] = {
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static u64 usb_dmamask = DMA_BIT_MASK(32);
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static struct platform_device usb_dev = {
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static struct platform_device da8xx_usb20_dev = {
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.name = "musb-da8xx",
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.id = -1,
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.dev = {
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/*
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* Setting init_name so that clock lookup will work in
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* usb20_phy_clk_enable() even if this device is not registered.
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*/
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.init_name = "musb-da8xx",
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.platform_data = &usb_data,
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.dma_mask = &usb_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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@ -73,18 +90,9 @@ int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt)
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usb_data.power = mA > 510 ? 255 : mA / 2;
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usb_data.potpgt = (potpgt + 1) / 2;
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return platform_device_register(&usb_dev);
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return platform_device_register(&da8xx_usb20_dev);
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}
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#else
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int __init da8xx_register_usb20(unsigned int mA, unsigned int potpgt)
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{
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return 0;
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}
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#endif /* CONFIG_USB_MUSB_HDRC */
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static struct resource da8xx_usb11_resources[] = {
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[0] = {
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.start = DA8XX_USB1_BASE,
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@ -116,3 +124,236 @@ int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata)
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da8xx_usb11_device.dev.platform_data = pdata;
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return platform_device_register(&da8xx_usb11_device);
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}
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static struct clk usb_refclkin = {
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.name = "usb_refclkin",
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.set_rate = davinci_simple_set_rate,
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};
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static struct clk_lookup usb_refclkin_lookup =
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CLK(NULL, "usb_refclkin", &usb_refclkin);
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/**
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* da8xx_register_usb_refclkin - register USB_REFCLKIN clock
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*
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* @rate: The clock rate in Hz
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*
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* This clock is only needed if the board provides an external USB_REFCLKIN
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* signal, in which case it will be used as the parent of usb20_phy_clk and/or
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* usb11_phy_clk.
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*/
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int __init da8xx_register_usb_refclkin(int rate)
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{
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int ret;
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usb_refclkin.rate = rate;
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ret = clk_register(&usb_refclkin);
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if (ret)
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return ret;
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clkdev_add(&usb_refclkin_lookup);
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return 0;
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}
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static void usb20_phy_clk_enable(struct clk *clk)
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{
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struct clk *usb20_clk;
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int err;
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u32 val;
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u32 timeout = 500000; /* 500 msec */
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val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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usb20_clk = clk_get(&da8xx_usb20_dev.dev, "usb20");
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if (IS_ERR(usb20_clk)) {
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pr_err("could not get usb20 clk: %ld\n", PTR_ERR(usb20_clk));
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return;
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}
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/* The USB 2.O PLL requires that the USB 2.O PSC is enabled as well. */
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err = clk_prepare_enable(usb20_clk);
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if (err) {
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pr_err("failed to enable usb20 clk: %d\n", err);
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clk_put(usb20_clk);
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return;
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}
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/*
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* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
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* host may use the PLL clock without USB 2.0 OTG being used.
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*/
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val &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN);
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val |= CFGCHIP2_PHY_PLLON;
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writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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while (--timeout) {
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val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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if (val & CFGCHIP2_PHYCLKGD)
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goto done;
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udelay(1);
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}
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pr_err("Timeout waiting for USB 2.0 PHY clock good\n");
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done:
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clk_disable_unprepare(usb20_clk);
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clk_put(usb20_clk);
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}
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static void usb20_phy_clk_disable(struct clk *clk)
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{
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u32 val;
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val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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val |= CFGCHIP2_PHYPWRDN;
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writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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}
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static int usb20_phy_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 val;
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val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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/* Set the mux depending on the parent clock. */
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if (parent == &usb_refclkin) {
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val &= ~CFGCHIP2_USB2PHYCLKMUX;
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} else if (strcmp(parent->name, "pll0_aux_clk") == 0) {
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val |= CFGCHIP2_USB2PHYCLKMUX;
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} else {
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pr_err("Bad parent on USB 2.0 PHY clock\n");
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return -EINVAL;
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}
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/* reference frequency also comes from parent clock */
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val &= ~CFGCHIP2_REFFREQ_MASK;
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switch (clk_get_rate(parent)) {
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case 12000000:
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val |= CFGCHIP2_REFFREQ_12MHZ;
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break;
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case 13000000:
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val |= CFGCHIP2_REFFREQ_13MHZ;
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break;
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case 19200000:
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val |= CFGCHIP2_REFFREQ_19_2MHZ;
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break;
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case 20000000:
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val |= CFGCHIP2_REFFREQ_20MHZ;
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break;
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case 24000000:
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val |= CFGCHIP2_REFFREQ_24MHZ;
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break;
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case 26000000:
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val |= CFGCHIP2_REFFREQ_26MHZ;
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break;
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case 38400000:
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val |= CFGCHIP2_REFFREQ_38_4MHZ;
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break;
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case 40000000:
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val |= CFGCHIP2_REFFREQ_40MHZ;
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break;
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case 48000000:
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val |= CFGCHIP2_REFFREQ_48MHZ;
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break;
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default:
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pr_err("Bad parent clock rate on USB 2.0 PHY clock\n");
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return -EINVAL;
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}
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writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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return 0;
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}
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static struct clk usb20_phy_clk = {
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.name = "usb20_phy",
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.clk_enable = usb20_phy_clk_enable,
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.clk_disable = usb20_phy_clk_disable,
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.set_parent = usb20_phy_clk_set_parent,
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};
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static struct clk_lookup usb20_phy_clk_lookup =
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CLK("da8xx-usb-phy", "usb20_phy", &usb20_phy_clk);
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/**
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* da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock
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*
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* @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
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* or "pll0_aux" if false.
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*/
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int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin)
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{
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struct clk *parent;
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int ret = 0;
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parent = clk_get(NULL, use_usb_refclkin ? "usb_refclkin" : "pll0_aux");
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if (IS_ERR(parent))
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return PTR_ERR(parent);
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usb20_phy_clk.parent = parent;
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ret = clk_register(&usb20_phy_clk);
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if (!ret)
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clkdev_add(&usb20_phy_clk_lookup);
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clk_put(parent);
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return ret;
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}
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static int usb11_phy_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 val;
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val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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/* Set the USB 1.1 PHY clock mux based on the parent clock. */
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if (parent == &usb20_phy_clk) {
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val &= ~CFGCHIP2_USB1PHYCLKMUX;
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} else if (parent == &usb_refclkin) {
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val |= CFGCHIP2_USB1PHYCLKMUX;
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} else {
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pr_err("Bad parent on USB 1.1 PHY clock\n");
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return -EINVAL;
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}
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writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
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return 0;
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}
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static struct clk usb11_phy_clk = {
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.name = "usb11_phy",
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.set_parent = usb11_phy_clk_set_parent,
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};
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static struct clk_lookup usb11_phy_clk_lookup =
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CLK("da8xx-usb-phy", "usb11_phy", &usb11_phy_clk);
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/**
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* da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock
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*
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* @use_usb_refclkin: Selects the parent clock - either "usb_refclkin" if true
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* or "usb20_phy" if false.
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*/
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int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
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{
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struct clk *parent;
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int ret = 0;
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if (use_usb_refclkin)
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parent = clk_get(NULL, "usb_refclkin");
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else
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parent = clk_get(&da8xx_usb_phy.dev, "usb20_phy");
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if (IS_ERR(parent))
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return PTR_ERR(parent);
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usb11_phy_clk.parent = parent;
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ret = clk_register(&usb11_phy_clk);
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if (!ret)
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clkdev_add(&usb11_phy_clk_lookup);
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clk_put(parent);
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return ret;
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}
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