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selftests: bpf: add zero extend checks for ALU32 and/or/xor
Add three tests to test_verifier/basic_instr that make sure that the high 32-bits of the destination register is cleared after an ALU32 and/or/xor. Signed-off-by: Björn Töpel <bjorn.topel@gmail.com> Acked-by: Yonghong Song <yhs@fb.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
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@ -132,3 +132,42 @@
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.result = ACCEPT,
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},
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},
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{
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"and32 reg zero extend check",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_0, -1),
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BPF_MOV64_IMM(BPF_REG_2, -2),
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BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2),
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BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 0,
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},
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{
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"or32 reg zero extend check",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_0, -1),
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BPF_MOV64_IMM(BPF_REG_2, -2),
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BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2),
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BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 0,
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},
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{
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"xor32 reg zero extend check",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_0, -1),
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BPF_MOV64_IMM(BPF_REG_2, 0),
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BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2),
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BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 0,
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},
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