mirror of https://gitee.com/openkylin/linux.git
drm/i915: Init some CHV workarounds via LRIs in ring->init_context()
Follow the BDW example and apply the workarounds touching registers which are saved in the context image through LRIs in the new ring->init_context() hook. This makes Mesa much happier and eg. glxgears doesn't hang after the first frame. Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Add missing wa table initialization to avoid a functional conflict with Arun's wa table debugfs support.] Reviewed-by: "Barbalho, Rafael" <rafael.barbalho@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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21386f86c9
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00e1e623e6
drivers/gpu/drm/i915
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@ -6011,14 +6011,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
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I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
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/* WaDisablePartialInstShootdown:chv */
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I915_WRITE(GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
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/* WaDisableThreadStallDopClockGating:chv */
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I915_WRITE(GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
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/* WaVSRefCountFullforceMissDisable:chv */
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/* WaDSRefCountFullforceMissDisable:chv */
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I915_WRITE(GEN7_FF_THREAD_MODE,
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@ -6037,10 +6029,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
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I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
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GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
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/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
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I915_WRITE(HALF_SLICE_CHICKEN3,
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_MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
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/* WaDisableGunitClockGating:chv (pre-production hw) */
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I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
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GINT_DIS);
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@ -6050,8 +6038,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
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_MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
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/* WaDisableDopClockGating:chv (pre-production hw) */
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I915_WRITE(GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
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GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
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}
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@ -681,7 +681,7 @@ static inline void intel_ring_emit_wa(struct intel_engine_cs *ring,
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return;
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}
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static int gen8_init_workarounds(struct intel_engine_cs *ring)
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static int bdw_init_workarounds(struct intel_engine_cs *ring)
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{
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int ret;
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struct drm_device *dev = ring->dev;
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@ -758,6 +758,45 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring)
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return 0;
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}
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static int chv_init_workarounds(struct intel_engine_cs *ring)
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{
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int ret;
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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/*
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* workarounds applied in this fn are part of register state context,
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* they need to be re-initialized followed by gpu reset, suspend/resume,
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* module reload.
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*/
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dev_priv->num_wa_regs = 0;
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memset(dev_priv->intel_wa_regs, 0, sizeof(dev_priv->intel_wa_regs));
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ret = intel_ring_begin(ring, 12);
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if (ret)
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return ret;
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/* WaDisablePartialInstShootdown:chv */
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intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
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/* WaDisableThreadStallDopClockGating:chv */
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intel_ring_emit_wa(ring, GEN8_ROW_CHICKEN,
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_MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
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/* WaDisableDopClockGating:chv (pre-production hw) */
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intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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/* WaDisableSamplerPowerBypass:chv (pre-production hw) */
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intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3,
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_MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
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intel_ring_advance(ring);
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return 0;
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}
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static int init_render_ring(struct intel_engine_cs *ring)
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{
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struct drm_device *dev = ring->dev;
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@ -2244,7 +2283,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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dev_priv->semaphore_obj = obj;
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}
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}
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ring->init_context = gen8_init_workarounds;
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if (IS_CHERRYVIEW(dev))
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ring->init_context = chv_init_workarounds;
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else
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ring->init_context = bdw_init_workarounds;
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ring->add_request = gen6_add_request;
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ring->flush = gen8_render_ring_flush;
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ring->irq_get = gen8_ring_get_irq;
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