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Merge branch 'x86/cleanups' into x86/urgent 

Pull in some merge window leftovers.

Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar 2016-03-17 09:44:57 +01:00
parent cbf8b5a2b6 d89abe2a1f
commit 00f5268501
44 changed files with 52 additions and 66 deletions
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2
arch/x86/entry/vdso/vclock_gettime.c
View File

@ -178,7 +178,7 @@ notrace static cycle_t vread_tsc(void)
/*
* GCC likes to generate cmov here, but this branch is extremely
* predictable (it's just a funciton of time and the likely is
* predictable (it's just a function of time and the likely is
* very likely) and there's a data dependence, so force GCC
* to generate a branch instead. I don't barrier() because
* we don't actually need a barrier, and if this function

2
arch/x86/events/intel/lbr.c
View File

@ -649,7 +649,7 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
/*
* return the type of control flow change at address "from"
* intruction is not necessarily a branch (in case of interrupt).
* instruction is not necessarily a branch (in case of interrupt).
*
* The branch type returned also includes the priv level of the
* target of the control flow change (X86_BR_USER, X86_BR_KERNEL).

2
arch/x86/events/perf_event.h
View File

@ -272,7 +272,7 @@ struct cpu_hw_events {
* events to select for counter rescheduling.
*
* Care must be taken as the rescheduling algorithm is O(n!) which
* will increase scheduling cycles for an over-commited system
* will increase scheduling cycles for an over-committed system
* dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
* and its counter masks must be kept at a minimum.
*/

2
arch/x86/include/asm/ftrace.h
View File

@ -52,7 +52,7 @@ int ftrace_int3_handler(struct pt_regs *regs);
* this screws up the trace output when tracing a ia32 task.
* Instead of reporting bogus syscalls, just do not trace them.
*
* If the user realy wants these, then they should use the
* If the user really wants these, then they should use the
* raw syscall tracepoints with filtering.
*/
#define ARCH_TRACE_IGNORE_COMPAT_SYSCALLS 1

14
arch/x86/include/asm/hw_irq.h
View File

@ -168,20 +168,6 @@ extern atomic_t irq_mis_count;
extern void elcr_set_level_irq(unsigned int irq);
/* SMP */
extern __visible void smp_apic_timer_interrupt(struct pt_regs *);
extern __visible void smp_spurious_interrupt(struct pt_regs *);
extern __visible void smp_x86_platform_ipi(struct pt_regs *);
extern __visible void smp_error_interrupt(struct pt_regs *);
#ifdef CONFIG_X86_IO_APIC
extern asmlinkage void smp_irq_move_cleanup_interrupt(void);
#endif
#ifdef CONFIG_SMP
extern __visible void smp_reschedule_interrupt(struct pt_regs *);
extern __visible void smp_call_function_interrupt(struct pt_regs *);
extern __visible void smp_call_function_single_interrupt(struct pt_regs *);
#endif
extern char irq_entries_start[];
#ifdef CONFIG_TRACING
#define trace_irq_entries_start irq_entries_start

2
arch/x86/include/asm/rwsem.h
View File

@ -25,7 +25,7 @@
* This should be totally fair - if anything is waiting, a process that wants a
* lock will go to the back of the queue. When the currently active lock is
* released, if there's a writer at the front of the queue, then that and only
* that will be woken up; if there's a bunch of consequtive readers at the
* that will be woken up; if there's a bunch of consecutive readers at the
* front, then they'll all be woken up, but no other readers will be.
*/

4
arch/x86/kernel/acpi/boot.c
View File

@ -956,7 +956,7 @@ static int __init early_acpi_parse_madt_lapic_addr_ovr(void)
/*
* Note that the LAPIC address is obtained from the MADT (32-bit value)
* and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
* and (optionally) overridden by a LAPIC_ADDR_OVR entry (64-bit value).
*/
count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE,
@ -984,7 +984,7 @@ static int __init acpi_parse_madt_lapic_entries(void)
/*
* Note that the LAPIC address is obtained from the MADT (32-bit value)
* and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
* and (optionally) overridden by a LAPIC_ADDR_OVR entry (64-bit value).
*/
count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE,

2
arch/x86/kernel/apic/apic.c
View File

@ -1611,7 +1611,7 @@ void __init enable_IR_x2apic(void)
legacy_pic->mask_all();
mask_ioapic_entries();
/* If irq_remapping_prepare() succeded, try to enable it */
/* If irq_remapping_prepare() succeeded, try to enable it */
if (ir_stat >= 0)
ir_stat = try_to_enable_IR();
/* ir_stat contains the remap mode or an error code */

2
arch/x86/kernel/apic/x2apic_uv_x.c
View File

@ -860,7 +860,7 @@ int uv_set_vga_state(struct pci_dev *pdev, bool decode,
*/
void uv_cpu_init(void)
{
/* CPU 0 initilization will be done via uv_system_init. */
/* CPU 0 initialization will be done via uv_system_init. */
if (!uv_blade_info)
return;

2
arch/x86/kernel/apm_32.c
View File

@ -1088,7 +1088,7 @@ static int apm_get_battery_status(u_short which, u_short *status,
* @device: identity of device
* @enable: on/off
*
* Activate or deactive power management on either a specific device
* Activate or deactivate power management on either a specific device
* or the entire system (%APM_DEVICE_ALL).
*/

2
arch/x86/kernel/cpu/amd.c
View File

@ -82,7 +82,7 @@ static void init_amd_k5(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_32
/*
* General Systems BIOSen alias the cpu frequency registers
* of the Elan at 0x000df000. Unfortuantly, one of the Linux
* of the Elan at 0x000df000. Unfortunately, one of the Linux
* drivers subsequently pokes it, and changes the CPU speed.
* Workaround : Remove the unneeded alias.
*/

4
arch/x86/kernel/cpu/common.c
View File

@ -925,7 +925,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
if (this_cpu->c_identify)
this_cpu->c_identify(c);
/* Clear/Set all flags overriden by options, after probe */
/* Clear/Set all flags overridden by options, after probe */
for (i = 0; i < NCAPINTS; i++) {
c->x86_capability[i] &= ~cpu_caps_cleared[i];
c->x86_capability[i] |= cpu_caps_set[i];
@ -984,7 +984,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
x86_init_cache_qos(c);
/*
* Clear/Set all flags overriden by options, need do it
* Clear/Set all flags overridden by options, need do it
* before following smp all cpus cap AND.
*/
for (i = 0; i < NCAPINTS; i++) {

2
arch/x86/kernel/cpu/mtrr/generic.c
View File

@ -42,7 +42,7 @@ EXPORT_SYMBOL_GPL(mtrr_state);
* "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
* Opteron Processors" (26094 Rev. 3.30 February 2006), section
* "13.2.1.2 SYSCFG Register": "The MtrrFixDramModEn bit should be set
* to 1 during BIOS initalization of the fixed MTRRs, then cleared to
* to 1 during BIOS initialization of the fixed MTRRs, then cleared to
* 0 for operation."
*/
static inline void k8_check_syscfg_dram_mod_en(void)

2
arch/x86/kernel/early_printk.c
View File

@ -287,7 +287,7 @@ static __init void early_pci_serial_init(char *s)
}
/*
* Lastly, initalize the hardware
* Lastly, initialize the hardware
*/
if (*s) {
if (strcmp(s, "nocfg") == 0)

2
arch/x86/kernel/fpu/regset.c
View File

@ -8,7 +8,7 @@
/*
* The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
* as the "regset->n" for the xstate regset will be updated based on the feature
* capabilites supported by the xsave.
* capabilities supported by the xsave.
*/
int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
{

2
arch/x86/kernel/kexec-bzimage64.c
View File

@ -271,7 +271,7 @@ static int bzImage64_probe(const char *buf, unsigned long len)
int ret = -ENOEXEC;
struct setup_header *header;
/* kernel should be atleast two sectors long */
/* kernel should be at least two sectors long */
if (len < 2 * 512) {
pr_err("File is too short to be a bzImage\n");
return ret;

4
arch/x86/kernel/kgdb.c
View File

@ -609,9 +609,9 @@ static struct notifier_block kgdb_notifier = {
};
/**
* kgdb_arch_init - Perform any architecture specific initalization.
* kgdb_arch_init - Perform any architecture specific initialization.
*
* This function will handle the initalization of any architecture
* This function will handle the initialization of any architecture
* specific callbacks.
*/
int kgdb_arch_init(void)

2
arch/x86/kernel/kvmclock.c
View File

@ -226,7 +226,7 @@ static void kvm_setup_secondary_clock(void)
* registered memory location. If the guest happens to shutdown, this memory
* won't be valid. In cases like kexec, in which you install a new kernel, this
* means a random memory location will be kept being written. So before any
* kind of shutdown from our side, we unregister the clock by writting anything
* kind of shutdown from our side, we unregister the clock by writing anything
* that does not have the 'enable' bit set in the msr
*/
#ifdef CONFIG_KEXEC_CORE

2
arch/x86/kernel/tsc.c
View File

@ -881,7 +881,7 @@ void tsc_restore_sched_clock_state(void)
local_irq_save(flags);
/*
* We're comming out of suspend, there's no concurrency yet; don't
* We're coming out of suspend, there's no concurrency yet; don't
* bother being nice about the RCU stuff, just write to both
* data fields.
*/

4
arch/x86/kvm/mmu.c
View File

@ -478,7 +478,7 @@ static bool spte_is_locklessly_modifiable(u64 spte)
static bool spte_has_volatile_bits(u64 spte)
{
/*
* Always atomicly update spte if it can be updated
* Always atomically update spte if it can be updated
* out of mmu-lock, it can ensure dirty bit is not lost,
* also, it can help us to get a stable is_writable_pte()
* to ensure tlb flush is not missed.
@ -549,7 +549,7 @@ static bool mmu_spte_update(u64 *sptep, u64 new_spte)
/*
* For the spte updated out of mmu-lock is safe, since
* we always atomicly update it, see the comments in
* we always atomically update it, see the comments in
* spte_has_volatile_bits().
*/
if (spte_is_locklessly_modifiable(old_spte) &&

4
arch/x86/kvm/vmx.c
View File

@ -5496,7 +5496,7 @@ static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
return kvm_set_cr4(vcpu, val);
}
/* called to set cr0 as approriate for clts instruction exit. */
/* called to set cr0 as appropriate for clts instruction exit. */
static void handle_clts(struct kvm_vcpu *vcpu)
{
if (is_guest_mode(vcpu)) {
@ -7244,7 +7244,7 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu)
/* The value to write might be 32 or 64 bits, depending on L1's long
* mode, and eventually we need to write that into a field of several
* possible lengths. The code below first zero-extends the value to 64
* bit (field_value), and then copies only the approriate number of
* bit (field_value), and then copies only the appropriate number of
* bits into the vmcs12 field.
*/
u64 field_value = 0;

2
arch/x86/kvm/x86.c
View File

@ -1562,7 +1562,7 @@ static cycle_t read_tsc(void)
/*
* GCC likes to generate cmov here, but this branch is extremely
* predictable (it's just a funciton of time and the likely is
* predictable (it's just a function of time and the likely is
* very likely) and there's a data dependence, so force GCC
* to generate a branch instead. I don't barrier() because
* we don't actually need a barrier, and if this function

2
arch/x86/lib/memset_64.S
View File

@ -9,7 +9,7 @@
/*
* ISO C memset - set a memory block to a byte value. This function uses fast
* string to get better performance than the original function. The code is
* simpler and shorter than the orignal function as well.
* simpler and shorter than the original function as well.
*
* rdi destination
* rsi value (char)

4
arch/x86/mm/mpx.c
View File

@ -728,14 +728,14 @@ static inline unsigned long bd_entry_virt_space(struct mm_struct *mm)
/*
* This covers 32-bit emulation as well as 32-bit kernels
* running on 64-bit harware.
* running on 64-bit hardware.
*/
if (!is_64bit_mm(mm))
return (4ULL * GB) / MPX_BD_NR_ENTRIES_32;
/*
* 'x86_virt_bits' returns what the hardware is capable
* of, and returns the full >32-bit adddress space when
* of, and returns the full >32-bit address space when
* running 32-bit kernels on 64-bit hardware.
*/
virt_space = (1ULL << boot_cpu_data.x86_virt_bits);

2
arch/x86/mm/pat.c
View File

@ -149,7 +149,7 @@ enum {
PAT_WT = 4, /* Write Through */
PAT_WP = 5, /* Write Protected */
PAT_WB = 6, /* Write Back (default) */
PAT_UC_MINUS = 7, /* UC, but can be overriden by MTRR */
PAT_UC_MINUS = 7, /* UC, but can be overridden by MTRR */
};
#define CM(c) (_PAGE_CACHE_MODE_ ## c)

2
arch/x86/platform/intel-mid/device_libs/platform_bma023.c
View File

@ -1,5 +1,5 @@
/*
* platform_bma023.c: bma023 platform data initilization file
* platform_bma023.c: bma023 platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
*

2
arch/x86/platform/intel-mid/device_libs/platform_emc1403.c
View File

@ -1,5 +1,5 @@
/*
* platform_emc1403.c: emc1403 platform data initilization file
* platform_emc1403.c: emc1403 platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_gpio_keys.c
View File

@ -1,5 +1,5 @@
/*
* platform_gpio_keys.c: gpio_keys platform data initilization file
* platform_gpio_keys.c: gpio_keys platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_lis331.c
View File

@ -1,5 +1,5 @@
/*
* platform_lis331.c: lis331 platform data initilization file
* platform_lis331.c: lis331 platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_max7315.c
View File

@ -1,5 +1,5 @@
/*
* platform_max7315.c: max7315 platform data initilization file
* platform_max7315.c: max7315 platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_mpu3050.c
View File

@ -1,5 +1,5 @@
/*
* platform_mpu3050.c: mpu3050 platform data initilization file
* platform_mpu3050.c: mpu3050 platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_msic.c
View File

@ -1,5 +1,5 @@
/*
* platform_msic.c: MSIC platform data initilization file
* platform_msic.c: MSIC platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_msic_audio.c
View File

@ -1,5 +1,5 @@
/*
* platform_msic_audio.c: MSIC audio platform data initilization file
* platform_msic_audio.c: MSIC audio platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_msic_battery.c
View File

@ -1,5 +1,5 @@
/*
* platform_msic_battery.c: MSIC battery platform data initilization file
* platform_msic_battery.c: MSIC battery platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_msic_gpio.c
View File

@ -1,5 +1,5 @@
/*
* platform_msic_gpio.c: MSIC GPIO platform data initilization file
* platform_msic_gpio.c: MSIC GPIO platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_msic_ocd.c
View File

@ -1,5 +1,5 @@
/*
* platform_msic_ocd.c: MSIC OCD platform data initilization file
* platform_msic_ocd.c: MSIC OCD platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_msic_power_btn.c
View File

@ -1,5 +1,5 @@
/*
* platform_msic_power_btn.c: MSIC power btn platform data initilization file
* platform_msic_power_btn.c: MSIC power btn platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_msic_thermal.c
View File

@ -1,5 +1,5 @@
/*
* platform_msic_thermal.c: msic_thermal platform data initilization file
* platform_msic_thermal.c: msic_thermal platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_pmic_gpio.c
View File

@ -1,5 +1,5 @@
/*
* platform_pmic_gpio.c: PMIC GPIO platform data initilization file
* platform_pmic_gpio.c: PMIC GPIO platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_tc35876x.c
View File

@ -1,5 +1,5 @@
/*
* platform_tc35876x.c: tc35876x platform data initilization file
* platform_tc35876x.c: tc35876x platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/platform/intel-mid/device_libs/platform_tca6416.c
View File

@ -1,5 +1,5 @@
/*
* platform_tca6416.c: tca6416 platform data initilization file
* platform_tca6416.c: tca6416 platform data initialization file
*
* (C) Copyright 2013 Intel Corporation
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>

2
arch/x86/purgatory/stack.S
View File

@ -8,7 +8,7 @@
*/
/* A stack for the loaded kernel.
* Seperate and in the data section so it can be prepopulated.
* Separate and in the data section so it can be prepopulated.
*/
.data
.balign 4096

8
arch/x86/xen/mmu.c
View File

@ -1256,7 +1256,7 @@ static void __init xen_pagetable_cleanhighmap(void)
xen_cleanhighmap(addr, addr + size);
xen_start_info->pt_base = (unsigned long)__va(__pa(xen_start_info->pt_base));
#ifdef DEBUG
/* This is superflous and is not neccessary, but you know what
/* This is superfluous and is not necessary, but you know what
* lets do it. The MODULES_VADDR -> MODULES_END should be clear of
* anything at this stage. */
xen_cleanhighmap(MODULES_VADDR, roundup(MODULES_VADDR, PUD_SIZE) - 1);
@ -1474,7 +1474,7 @@ static void xen_write_cr3(unsigned long cr3)
/*
* At the start of the day - when Xen launches a guest, it has already
* built pagetables for the guest. We diligently look over them
* in xen_setup_kernel_pagetable and graft as appropiate them in the
* in xen_setup_kernel_pagetable and graft as appropriate them in the
* init_level4_pgt and its friends. Then when we are happy we load
* the new init_level4_pgt - and continue on.
*
@ -2792,7 +2792,7 @@ static int remap_area_mfn_pte_fn(pte_t *ptep, pgtable_t token,
struct remap_data *rmd = data;
pte_t pte = pte_mkspecial(mfn_pte(*rmd->mfn, rmd->prot));
/* If we have a contigious range, just update the mfn itself,
/* If we have a contiguous range, just update the mfn itself,
else update pointer to be "next mfn". */
if (rmd->contiguous)
(*rmd->mfn)++;
@ -2833,7 +2833,7 @@ static int do_remap_gfn(struct vm_area_struct *vma,
rmd.mfn = gfn;
rmd.prot = prot;
/* We use the err_ptr to indicate if there we are doing a contigious
/* We use the err_ptr to indicate if there we are doing a contiguous
* mapping or a discontigious mapping. */
rmd.contiguous = !err_ptr;

2
arch/x86/xen/xen-head.S
View File

@ -26,7 +26,7 @@
(1 << XENFEAT_auto_translated_physmap) | \
(1 << XENFEAT_supervisor_mode_kernel) | \
(1 << XENFEAT_hvm_callback_vector))
/* The XENFEAT_writable_page_tables is not stricly neccessary as we set that
/* The XENFEAT_writable_page_tables is not stricly necessary as we set that
* up regardless whether this CONFIG option is enabled or not, but it
* clarifies what the right flags need to be.
*/