mirror of https://gitee.com/openkylin/linux.git
drm/i915: Make AGP support optional
We only depend on the intel-gtt module for GTT frobbign on older gens. The intel_agp module is optional, except for UMS and some old XvMC userland on gen3. So make AGP support optional. As before, we will fail the i915 init for UMS and gen3 KMS the same as before if intel_agp isn't around. intel-gtt.c is left with a somewhat ugly ifdef mess, but I'm going to save that for a later cleaning. At least my gen2 still works with the patch and CONFIG_AGP=n. v2: Make i915 depend on X86 and PCI, and intel-gtt depend on PCI Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä
Daniel Vetter
parent
ab3c759a04
commit
00fe639a56
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@ -50,7 +50,7 @@ obj-$(CONFIG_GPIO_TB0219) += tb0219.o
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obj-$(CONFIG_TELCLOCK) += tlclk.o
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obj-$(CONFIG_MWAVE) += mwave/
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obj-$(CONFIG_AGP) += agp/
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obj-y += agp/
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obj-$(CONFIG_PCMCIA) += pcmcia/
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obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o
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@ -68,6 +68,7 @@ config AGP_AMD64
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config AGP_INTEL
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tristate "Intel 440LX/BX/GX, I8xx and E7x05 chipset support"
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depends on AGP && X86
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select INTEL_GTT
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help
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This option gives you AGP support for the GLX component of X
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on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860, 875,
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@ -155,3 +156,7 @@ config AGP_SGI_TIOCA
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This option gives you AGP GART support for the SGI TIO chipset
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for IA64 processors.
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config INTEL_GTT
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tristate
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depends on X86 && PCI
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@ -13,7 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
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obj-$(CONFIG_AGP_PARISC) += parisc-agp.o
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obj-$(CONFIG_AGP_I460) += i460-agp.o
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obj-$(CONFIG_AGP_INTEL) += intel-agp.o
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obj-$(CONFIG_AGP_INTEL) += intel-gtt.o
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obj-$(CONFIG_INTEL_GTT) += intel-gtt.o
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obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o
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obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o
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obj-$(CONFIG_AGP_SIS) += sis-agp.o
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@ -94,6 +94,7 @@ static struct _intel_private {
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#define IS_IRONLAKE intel_private.driver->is_ironlake
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#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static int intel_gtt_map_memory(struct page **pages,
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unsigned int num_entries,
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struct sg_table *st)
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@ -168,6 +169,7 @@ static void i8xx_destroy_pages(struct page *page)
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__free_pages(page, 2);
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atomic_dec(&agp_bridge->current_memory_agp);
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}
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#endif
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#define I810_GTT_ORDER 4
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static int i810_setup(void)
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@ -209,6 +211,7 @@ static void i810_cleanup(void)
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free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
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}
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
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int type)
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{
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@ -289,6 +292,7 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
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}
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kfree(curr);
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}
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#endif
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static int intel_gtt_setup_scratch_page(void)
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{
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@ -647,7 +651,9 @@ static int intel_gtt_init(void)
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return -ENOMEM;
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}
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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global_cache_flush(); /* FIXME: ? */
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#endif
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intel_private.stolen_size = intel_gtt_stolen_size();
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@ -671,6 +677,7 @@ static int intel_gtt_init(void)
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return 0;
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}
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static int intel_fake_agp_fetch_size(void)
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{
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int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
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@ -689,6 +696,7 @@ static int intel_fake_agp_fetch_size(void)
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return 0;
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}
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#endif
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static void i830_cleanup(void)
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{
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@ -801,6 +809,7 @@ static int i830_setup(void)
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return 0;
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}
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
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{
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agp_bridge->gatt_table_real = NULL;
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@ -825,6 +834,7 @@ static int intel_fake_agp_configure(void)
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return 0;
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}
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#endif
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static bool i830_check_flags(unsigned int flags)
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{
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@ -863,6 +873,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
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}
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EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static void intel_gtt_insert_pages(unsigned int first_entry,
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unsigned int num_entries,
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struct page **pages,
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@ -928,6 +939,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem,
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mem->is_flushed = true;
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return ret;
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}
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#endif
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void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
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{
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@ -941,6 +953,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
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}
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EXPORT_SYMBOL(intel_gtt_clear_range);
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static int intel_fake_agp_remove_entries(struct agp_memory *mem,
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off_t pg_start, int type)
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{
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@ -982,6 +995,7 @@ static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
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/* always return NULL for other allocation types for now */
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return NULL;
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}
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#endif
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static int intel_alloc_chipset_flush_resource(void)
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{
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@ -1138,6 +1152,7 @@ static int i9xx_setup(void)
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return 0;
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}
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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static const struct agp_bridge_driver intel_fake_agp_driver = {
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.owner = THIS_MODULE,
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.size_type = FIXED_APER_SIZE,
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@ -1159,6 +1174,7 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_destroy_pages = agp_generic_destroy_pages,
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};
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#endif
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static const struct intel_gtt_driver i81x_gtt_driver = {
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.gen = 1,
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@ -1376,11 +1392,13 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
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intel_private.refcount++;
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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if (bridge) {
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bridge->driver = &intel_fake_agp_driver;
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bridge->dev_private_data = &intel_private;
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bridge->dev = bridge_pdev;
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}
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#endif
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intel_private.bridge_dev = pci_dev_get(bridge_pdev);
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@ -1,8 +1,10 @@
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config DRM_I915
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tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics"
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depends on DRM
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depends on AGP
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depends on AGP_INTEL
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depends on X86 && PCI
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depends on (AGP || AGP=n)
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select INTEL_GTT
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select AGP_INTEL if AGP
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# we need shmfs for the swappable backing store, and in particular
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# the shmem_readpage() which depends upon tmpfs
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select SHMEM
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@ -155,7 +155,11 @@ MODULE_PARM_DESC(prefault_disable,
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"Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
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static struct drm_driver driver;
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#if IS_ENABLED(CONFIG_AGP_INTEL)
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extern int intel_agp_enabled;
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#else
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static int intel_agp_enabled;
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#endif
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static const struct intel_device_info intel_i830_info = {
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.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
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