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staging: comedi: multiq3: document the encoder chip commands
Add some comments to document the commands that are sent to the encoder chips. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#define MULTIQ3_ENC_CTRL_REG 0x0e
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/*
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* flags for encoder control
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* Encoder chip commands (from the programming manual)
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*/
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#define MULTIQ3_CLOCK_DATA 0x00
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#define MULTIQ3_CLOCK_SETUP 0x18
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#define MULTIQ3_INPUT_SETUP 0x41
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#define MULTIQ3_QUAD_X4 0x38
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#define MULTIQ3_BP_RESET 0x01
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#define MULTIQ3_CNTR_RESET 0x02
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#define MULTIQ3_TRSFRPR_CTR 0x08
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#define MULTIQ3_TRSFRCNTR_OL 0x10
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#define MULTIQ3_EFLAG_RESET 0x06
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#define MULTIQ3_CLOCK_DATA 0x00 /* FCK frequency divider */
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#define MULTIQ3_CLOCK_SETUP 0x18 /* xfer PR0 to PSC */
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#define MULTIQ3_INPUT_SETUP 0x41 /* enable inputs A and B */
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#define MULTIQ3_QUAD_X4 0x38 /* quadrature */
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#define MULTIQ3_BP_RESET 0x01 /* reset byte pointer */
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#define MULTIQ3_CNTR_RESET 0x02 /* reset counter */
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#define MULTIQ3_TRSFRPR_CTR 0x08 /* xfre preset reg to counter */
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#define MULTIQ3_TRSFRCNTR_OL 0x10 /* xfer CNTR to OL (x and y) */
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#define MULTIQ3_EFLAG_RESET 0x06 /* reset E bit of flag reg */
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#define MULTIQ3_TIMEOUT 30
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