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ASoC: Fix WM9081 PowerPC compiler issues 

Ensure that we always set a new sysclk when using the FLL in master mode
and pick out the correct value for the sample rate in hw_params().

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Mark Brown 2009-05-23 00:01:05 +01:00
parent 86ed3669f0
commit 0154724d48
1 changed files with 4 additions and 2 deletions
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6
sound/soc/codecs/wm9081.c
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@ -702,9 +702,10 @@ static int configure_clock(struct snd_soc_codec *codec)
* performance. */ * performance. */
for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
target = wm9081->fs * clk_sys_rates[i].ratio; target = wm9081->fs * clk_sys_rates[i].ratio;
new_sysclk = target;
if (target >= wm9081->bclk && if (target >= wm9081->bclk &&
target > 3000000) target > 3000000)
new_sysclk = target; break;
} }
} else if (wm9081->fs) { } else if (wm9081->fs) {
for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) { for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
@ -1102,7 +1103,8 @@ static int wm9081_hw_params(struct snd_pcm_substream *substream,
} }
dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
sample_rates[best].rate); sample_rates[best].rate);
clk_ctrl2 |= (sample_rates[i].sample_rate << WM9081_SAMPLE_RATE_SHIFT); clk_ctrl2 |= (sample_rates[best].sample_rate
<< WM9081_SAMPLE_RATE_SHIFT);
/* BCLK_DIV */ /* BCLK_DIV */
best = 0; best = 0;