mirror of https://gitee.com/openkylin/linux.git
staging: comedi: adv_pci1723: tidy up register map
For aesthetics, rename the defines used for the register map offsets and remove the unnecessary comments. Add the bit defines for the registers. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
5f86288fc5
commit
01601aaf9f
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@ -48,60 +48,42 @@ configures all channels in the same group.
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#include "../comedidev.h"
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/* all the registers for the pci1723 board */
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#define PCI1723_DA(N) ((N)<<1) /* W: D/A register N (0 to 7) */
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#define PCI1723_SYN_SET 0x12 /* synchronized set register */
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#define PCI1723_ALL_CHNNELE_SYN_STROBE 0x12
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/* synchronized status register */
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#define PCI1723_RANGE_CALIBRATION_MODE 0x14
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/* range and calibration mode */
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#define PCI1723_RANGE_CALIBRATION_STATUS 0x14
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/* range and calibration status */
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#define PCI1723_CONTROL_CMD_CALIBRATION_FUN 0x16
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/*
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* SADC control command for
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* calibration function
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* PCI Bar 2 I/O Register map (dev->iobase)
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*/
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#define PCI1723_STATUS_CMD_CALIBRATION_FUN 0x16
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/*
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* SADC control status for
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* calibration function
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*/
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#define PCI1723_CALIBRATION_PARA_STROBE 0x18
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/* Calibration parameter strobe */
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#define PCI1723_DIGITAL_IO_PORT_SET 0x1A /* Digital I/O port setting */
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#define PCI1723_DIGITAL_IO_PORT_MODE 0x1A /* Digital I/O port mode */
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#define PCI1723_WRITE_DIGITAL_OUTPUT_CMD 0x1C
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/* Write digital output command */
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#define PCI1723_READ_DIGITAL_INPUT_DATA 0x1C /* Read digital input data */
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#define PCI1723_WRITE_CAL_CMD 0x1E /* Write calibration command */
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#define PCI1723_READ_CAL_STATUS 0x1E /* Read calibration status */
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#define PCI1723_SYN_STROBE 0x20 /* Synchronized strobe */
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#define PCI1723_RESET_ALL_CHN_STROBE 0x22
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/* Reset all D/A channels strobe */
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#define PCI1723_RESET_CAL_CONTROL_STROBE 0x24
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/*
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* Reset the calibration
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* controller strobe
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*/
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#define PCI1723_CHANGE_CHA_OUTPUT_TYPE_STROBE 0x26
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/*
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* Change D/A channels output
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* type strobe
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*/
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#define PCI1723_SELECT_CALIBRATION 0x28 /* Select the calibration Ref_V */
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#define PCI1723_AO_REG(x) (0x00 + ((x) * 2))
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#define PCI1723_BOARD_ID_REG 0x10
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#define PCI1723_BOARD_ID_MASK (0xf << 0)
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#define PCI1723_SYNC_CTRL_REG 0x12
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#define PCI1723_SYNC_CTRL_ASYNC (0 << 0)
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#define PCI1723_SYNC_CTRL_SYNC (1 << 0)
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#define PCI1723_CTRL_REG 0x14
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#define PCI1723_CTRL_BUSY (1 << 15)
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#define PCI1723_CTRL_INIT (1 << 14)
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#define PCI1723_CTRL_SELF (1 << 8)
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#define PCI1723_CTRL_IDX(x) (((x) & 0x3) << 6)
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#define PCI1723_CTRL_RANGE(x) (((x) & 0x3) << 4)
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#define PCI1723_CTRL_GAIN (0 << 3)
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#define PCI1723_CTRL_OFFSET (1 << 3)
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#define PCI1723_CTRL_CHAN(x) (((x) & 0x7) << 0)
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#define PCI1723_CALIB_CTRL_REG 0x16
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#define PCI1723_CALIB_CTRL_CS (1 << 2)
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#define PCI1723_CALIB_CTRL_DAT (1 << 1)
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#define PCI1723_CALIB_CTRL_CLK (1 << 0)
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#define PCI1723_CALIB_STROBE_REG 0x18
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#define PCI1723_DIO_CTRL_REG 0x1a
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#define PCI1723_DIO_CTRL_HDIO (1 << 1)
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#define PCI1723_DIO_CTRL_LDIO (1 << 0)
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#define PCI1723_DIO_DATA_REG 0x1c
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#define PCI1723_CALIB_DATA_REG 0x1e
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#define PCI1723_SYNC_STROBE_REG 0x20
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#define PCI1723_RESET_AO_STROBE_REG 0x22
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#define PCI1723_RESET_CALIB_STROBE_REG 0x24
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#define PCI1723_RANGE_STROBE_REG 0x26
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#define PCI1723_VREF_REG 0x28
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#define PCI1723_VREF_NEG10V (0 << 0)
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#define PCI1723_VREF_0V (1 << 0)
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#define PCI1723_VREF_POS10V (3 << 0)
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struct pci1723_private {
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unsigned char da_range[8]; /* D/A output range for each channel */
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@ -116,25 +98,22 @@ static int pci1723_reset(struct comedi_device *dev)
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struct pci1723_private *devpriv = dev->private;
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int i;
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outw(0x01, dev->iobase + PCI1723_SYN_SET);
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/* set synchronous output mode */
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outw(PCI1723_SYNC_CTRL_SYNC, dev->iobase + PCI1723_SYNC_CTRL_REG);
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for (i = 0; i < 8; i++) {
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/* set all outputs to 0V */
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devpriv->ao_data[i] = 0x8000;
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outw(devpriv->ao_data[i], dev->iobase + PCI1723_DA(i));
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outw(devpriv->ao_data[i], dev->iobase + PCI1723_AO_REG(i));
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/* set all ranges to +/- 10V */
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devpriv->da_range[i] = 0;
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outw(((devpriv->da_range[i] << 4) | i),
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PCI1723_RANGE_CALIBRATION_MODE);
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PCI1723_CTRL_REG);
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}
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outw(0, dev->iobase + PCI1723_CHANGE_CHA_OUTPUT_TYPE_STROBE);
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/* update ranges */
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outw(0, dev->iobase + PCI1723_SYN_STROBE); /* update outputs */
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outw(0, dev->iobase + PCI1723_RANGE_STROBE_REG);
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outw(0, dev->iobase + PCI1723_SYNC_STROBE_REG);
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/* set asynchronous output mode */
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outw(0, dev->iobase + PCI1723_SYN_SET);
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outw(PCI1723_SYNC_CTRL_ASYNC, dev->iobase + PCI1723_SYNC_CTRL_REG);
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return 0;
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}
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@ -166,7 +145,7 @@ static int pci1723_ao_write_winsn(struct comedi_device *dev,
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for (n = 0; n < insn->n; n++) {
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devpriv->ao_data[chan] = data[n];
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outw(data[n], dev->iobase + PCI1723_DA(chan));
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outw(data[n], dev->iobase + PCI1723_AO_REG(chan));
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}
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return n;
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@ -199,7 +178,7 @@ static int pci1723_dio_insn_config(struct comedi_device *dev,
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mode |= 0x0001; /* low byte input */
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if (!(s->io_bits & 0xff00))
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mode |= 0x0002; /* high byte input */
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outw(mode, dev->iobase + PCI1723_DIGITAL_IO_PORT_SET);
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outw(mode, dev->iobase + PCI1723_DIO_CTRL_REG);
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return insn->n;
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}
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@ -210,9 +189,9 @@ static int pci1723_dio_insn_bits(struct comedi_device *dev,
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unsigned int *data)
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{
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if (comedi_dio_update_state(s, data))
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outw(s->state, dev->iobase + PCI1723_WRITE_DIGITAL_OUTPUT_CMD);
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outw(s->state, dev->iobase + PCI1723_DIO_DATA_REG);
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data[1] = inw(dev->iobase + PCI1723_READ_DIGITAL_INPUT_DATA);
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data[1] = inw(dev->iobase + PCI1723_DIO_DATA_REG);
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return insn->n;
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}
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@ -260,7 +239,7 @@ static int pci1723_auto_attach(struct comedi_device *dev,
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s->insn_bits = pci1723_dio_insn_bits;
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/* read DIO config */
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switch (inw(dev->iobase + PCI1723_DIGITAL_IO_PORT_MODE) & 0x03) {
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switch (inw(dev->iobase + PCI1723_DIO_CTRL_REG) & 0x03) {
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case 0x00: /* low byte output, high byte output */
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s->io_bits = 0xFFFF;
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break;
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@ -275,7 +254,7 @@ static int pci1723_auto_attach(struct comedi_device *dev,
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break;
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}
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/* read DIO port state */
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s->state = inw(dev->iobase + PCI1723_READ_DIGITAL_INPUT_DATA);
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s->state = inw(dev->iobase + PCI1723_DIO_DATA_REG);
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pci1723_reset(dev);
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