mirror of https://gitee.com/openkylin/linux.git
net: hns3: Add enable and process hw errors of TM scheduler
This patch enables and process hw errors of TM scheduler and QCN(Quantized Congestion Control). Signed-off-by: Shiju Jose <shiju.jose@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shiju Jose
David S. Miller
parent
da2d072a9e
commit
01865a50d7
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@ -211,6 +211,12 @@ enum hclge_opcode_type {
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HCLGE_OPC_LED_STATUS_CFG = 0xB000,
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/* Error INT commands */
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HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
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HCLGE_TM_SCH_ECC_ERR_RINT_CMD = 0x082d,
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HCLGE_TM_SCH_ECC_ERR_RINT_CE = 0x082f,
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HCLGE_TM_SCH_ECC_ERR_RINT_NFE = 0x0830,
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HCLGE_TM_SCH_ECC_ERR_RINT_FE = 0x0831,
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HCLGE_TM_SCH_MBIT_ECC_INFO_CMD = 0x0833,
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HCLGE_COMMON_ECC_INT_CFG = 0x1505,
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HCLGE_IGU_EGU_TNL_INT_QUERY = 0x1802,
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HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
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@ -218,6 +224,8 @@ enum hclge_opcode_type {
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HCLGE_IGU_COMMON_INT_QUERY = 0x1805,
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HCLGE_IGU_COMMON_INT_EN = 0x1806,
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HCLGE_IGU_COMMON_INT_CLR = 0x1807,
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HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
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HCLGE_TM_QCN_MEM_INT_INFO_CMD = 0x1A17,
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HCLGE_PPP_CMD0_INT_CMD = 0x2100,
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HCLGE_PPP_CMD1_INT_CMD = 0x2101,
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HCLGE_NCSI_INT_QUERY = 0x2400,
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@ -213,6 +213,129 @@ static const struct hclge_hw_error hclge_ppp_mpf_int3[] = {
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{ /* sentinel */ }
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};
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struct hclge_tm_sch_ecc_info {
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const char *name;
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};
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static const struct hclge_tm_sch_ecc_info hclge_tm_sch_ecc_err[7][15] = {
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{
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{ .name = "QSET_QUEUE_CTRL:PRI_LEN TAB" },
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{ .name = "QSET_QUEUE_CTRL:SPA_LEN TAB" },
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{ .name = "QSET_QUEUE_CTRL:SPB_LEN TAB" },
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{ .name = "QSET_QUEUE_CTRL:WRRA_LEN TAB" },
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{ .name = "QSET_QUEUE_CTRL:WRRB_LEN TAB" },
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{ .name = "QSET_QUEUE_CTRL:SPA_HPTR TAB" },
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{ .name = "QSET_QUEUE_CTRL:SPB_HPTR TAB" },
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{ .name = "QSET_QUEUE_CTRL:WRRA_HPTR TAB" },
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{ .name = "QSET_QUEUE_CTRL:WRRB_HPTR TAB" },
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{ .name = "QSET_QUEUE_CTRL:QS_LINKLIST TAB" },
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{ .name = "QSET_QUEUE_CTRL:SPA_TPTR TAB" },
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{ .name = "QSET_QUEUE_CTRL:SPB_TPTR TAB" },
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{ .name = "QSET_QUEUE_CTRL:WRRA_TPTR TAB" },
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{ .name = "QSET_QUEUE_CTRL:WRRB_TPTR TAB" },
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{ .name = "QSET_QUEUE_CTRL:QS_DEFICITCNT TAB" },
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},
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{
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{ .name = "ROCE_QUEUE_CTRL:QS_LEN TAB" },
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{ .name = "ROCE_QUEUE_CTRL:QS_TPTR TAB" },
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{ .name = "ROCE_QUEUE_CTRL:QS_HPTR TAB" },
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{ .name = "ROCE_QUEUE_CTRL:QLINKLIST TAB" },
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{ .name = "ROCE_QUEUE_CTRL:QCLEN TAB" },
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},
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{
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{ .name = "NIC_QUEUE_CTRL:QS_LEN TAB" },
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{ .name = "NIC_QUEUE_CTRL:QS_TPTR TAB" },
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{ .name = "NIC_QUEUE_CTRL:QS_HPTR TAB" },
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{ .name = "NIC_QUEUE_CTRL:QLINKLIST TAB" },
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{ .name = "NIC_QUEUE_CTRL:QCLEN TAB" },
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},
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{
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{ .name = "RAM_CFG_CTRL:CSHAP TAB" },
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{ .name = "RAM_CFG_CTRL:PSHAP TAB" },
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},
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{
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{ .name = "SHAPER_CTRL:PSHAP TAB" },
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},
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{
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{ .name = "MSCH_CTRL" },
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},
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{
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{ .name = "TOP_CTRL" },
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},
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};
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static const struct hclge_hw_error hclge_tm_sch_err_int[] = {
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{ .int_msk = BIT(0), .msg = "tm_sch_ecc_1bit_err" },
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{ .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err" },
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{ .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_full_err" },
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{ .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_empty_err" },
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{ .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_full_err" },
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{ .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_empty_err" },
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{ .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_full_err" },
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{ .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_empty_err" },
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{ .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_full_err" },
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{ .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_empty_err" },
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{ .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_full_err" },
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{ .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_empty_err" },
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{ .int_msk = BIT(12),
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.msg = "tm_sch_port_shap_offset_fifo_wr_full_err" },
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{ .int_msk = BIT(13),
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.msg = "tm_sch_port_shap_offset_fifo_rd_empty_err" },
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{ .int_msk = BIT(14),
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.msg = "tm_sch_pg_pshap_offset_fifo_wr_full_err" },
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{ .int_msk = BIT(15),
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.msg = "tm_sch_pg_pshap_offset_fifo_rd_empty_err" },
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{ .int_msk = BIT(16),
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.msg = "tm_sch_pg_cshap_offset_fifo_wr_full_err" },
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{ .int_msk = BIT(17),
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.msg = "tm_sch_pg_cshap_offset_fifo_rd_empty_err" },
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{ .int_msk = BIT(18),
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.msg = "tm_sch_pri_pshap_offset_fifo_wr_full_err" },
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{ .int_msk = BIT(19),
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.msg = "tm_sch_pri_pshap_offset_fifo_rd_empty_err" },
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{ .int_msk = BIT(20),
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.msg = "tm_sch_pri_cshap_offset_fifo_wr_full_err" },
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{ .int_msk = BIT(21),
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.msg = "tm_sch_pri_cshap_offset_fifo_rd_empty_err" },
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{ .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_full_err" },
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{ .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_empty_err" },
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{ .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_full_err" },
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{ .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_empty_err" },
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{ .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_full_err" },
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{ .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_empty_err" },
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{ .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_full_err" },
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{ .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_empty_err" },
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{ .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_full_err" },
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{ .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_empty_err" },
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{ /* sentinel */ }
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};
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static const struct hclge_hw_error hclge_qcn_ecc_err_int[] = {
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{ .int_msk = BIT(0), .msg = "qcn_byte_mem_ecc_1bit_err" },
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{ .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err" },
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{ .int_msk = BIT(2), .msg = "qcn_time_mem_ecc_1bit_err" },
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{ .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err" },
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{ .int_msk = BIT(4), .msg = "qcn_fb_mem_ecc_1bit_err" },
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{ .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err" },
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{ .int_msk = BIT(6), .msg = "qcn_link_mem_ecc_1bit_err" },
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{ .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err" },
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{ .int_msk = BIT(8), .msg = "qcn_rate_mem_ecc_1bit_err" },
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{ .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err" },
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{ .int_msk = BIT(10), .msg = "qcn_tmplt_mem_ecc_1bit_err" },
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{ .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err" },
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{ .int_msk = BIT(12), .msg = "qcn_shap_cfg_mem_ecc_1bit_err" },
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{ .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err" },
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{ .int_msk = BIT(14), .msg = "qcn_gp0_barrel_mem_ecc_1bit_err" },
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{ .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err" },
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{ .int_msk = BIT(16), .msg = "qcn_gp1_barrel_mem_ecc_1bit_err" },
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{ .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err" },
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{ .int_msk = BIT(18), .msg = "qcn_gp2_barrel_mem_ecc_1bit_err" },
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{ .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err" },
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{ .int_msk = BIT(20), .msg = "qcn_gp3_barral_mem_ecc_1bit_err" },
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{ .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err" },
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{ /* sentinel */ }
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};
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static void hclge_log_error(struct device *dev,
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const struct hclge_hw_error *err_list,
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u32 err_sts)
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@ -501,6 +624,47 @@ static int hclge_enable_ppp_error(struct hclge_dev *hdev, bool en)
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return ret;
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}
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int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en)
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{
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struct device *dev = &hdev->pdev->dev;
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struct hclge_desc desc;
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int ret;
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/* enable TM SCH hw errors */
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hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_SCH_ECC_INT_EN, false);
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if (en)
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desc.data[0] = cpu_to_le32(HCLGE_TM_SCH_ECC_ERR_INT_EN);
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else
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desc.data[0] = 0;
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ret = hclge_cmd_send(&hdev->hw, &desc, 1);
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if (ret) {
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dev_err(dev, "failed(%d) to configure TM SCH errors\n", ret);
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return ret;
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}
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/* enable TM QCN hw errors */
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ret = hclge_cmd_query_error(hdev, &desc, HCLGE_TM_QCN_MEM_INT_CFG,
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0, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to read TM QCN CFG status\n", ret);
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return ret;
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}
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hclge_cmd_reuse_desc(&desc, false);
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if (en)
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desc.data[1] = cpu_to_le32(HCLGE_TM_QCN_MEM_ERR_INT_EN);
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else
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desc.data[1] = 0;
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ret = hclge_cmd_send(&hdev->hw, &desc, 1);
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if (ret)
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dev_err(dev,
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"failed(%d) to configure TM QCN mem errors\n", ret);
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return ret;
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}
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static void hclge_process_common_error(struct hclge_dev *hdev,
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enum hclge_err_int_type type)
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{
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@ -736,6 +900,125 @@ static void hclge_process_ppp_error(struct hclge_dev *hdev,
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ret);
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}
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static void hclge_process_tm_sch_error(struct hclge_dev *hdev)
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{
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struct device *dev = &hdev->pdev->dev;
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const struct hclge_tm_sch_ecc_info *tm_sch_ecc_info;
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struct hclge_desc desc;
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u32 ecc_info;
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u8 module_no;
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u8 ram_no;
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int ret;
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/* read TM scheduler errors */
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ret = hclge_cmd_query_error(hdev, &desc,
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HCLGE_TM_SCH_MBIT_ECC_INFO_CMD, 0, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to read SCH mbit ECC err info\n", ret);
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return;
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}
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ecc_info = le32_to_cpu(desc.data[0]);
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ret = hclge_cmd_query_error(hdev, &desc,
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HCLGE_TM_SCH_ECC_ERR_RINT_CMD, 0, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to read SCH ECC err status\n", ret);
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return;
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}
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/* log TM scheduler errors */
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if (le32_to_cpu(desc.data[0])) {
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hclge_log_error(dev, &hclge_tm_sch_err_int[0],
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le32_to_cpu(desc.data[0]));
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if (le32_to_cpu(desc.data[0]) & 0x2) {
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module_no = (ecc_info >> 20) & 0xF;
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ram_no = (ecc_info >> 16) & 0xF;
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tm_sch_ecc_info =
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&hclge_tm_sch_ecc_err[module_no][ram_no];
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dev_warn(dev, "ecc err module:ram=%s\n",
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tm_sch_ecc_info->name);
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dev_warn(dev, "ecc memory address = 0x%x\n",
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ecc_info & 0xFFFF);
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}
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}
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/* clear TM scheduler errors */
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ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to clear TM SCH error status\n", ret);
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return;
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}
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ret = hclge_cmd_query_error(hdev, &desc,
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HCLGE_TM_SCH_ECC_ERR_RINT_CE, 0, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to read SCH CE status\n", ret);
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return;
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}
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ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to clear TM SCH CE status\n", ret);
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return;
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}
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ret = hclge_cmd_query_error(hdev, &desc,
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HCLGE_TM_SCH_ECC_ERR_RINT_NFE, 0, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to read SCH NFE status\n", ret);
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return;
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}
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ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to clear TM SCH NFE status\n", ret);
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return;
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}
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ret = hclge_cmd_query_error(hdev, &desc,
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HCLGE_TM_SCH_ECC_ERR_RINT_FE, 0, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to read SCH FE status\n", ret);
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return;
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}
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ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
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if (ret)
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dev_err(dev, "failed(%d) to clear TM SCH FE status\n", ret);
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}
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static void hclge_process_tm_qcn_error(struct hclge_dev *hdev)
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{
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struct device *dev = &hdev->pdev->dev;
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struct hclge_desc desc;
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int ret;
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/* read QCN errors */
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ret = hclge_cmd_query_error(hdev, &desc,
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HCLGE_TM_QCN_MEM_INT_INFO_CMD, 0, 0, 0);
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if (ret) {
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dev_err(dev, "failed(%d) to read QCN ECC err status\n", ret);
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return;
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}
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/* log QCN errors */
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if (le32_to_cpu(desc.data[0]))
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hclge_log_error(dev, &hclge_qcn_ecc_err_int[0],
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le32_to_cpu(desc.data[0]));
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/* clear QCN errors */
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ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
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if (ret)
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dev_err(dev, "failed(%d) to clear QCN error status\n", ret);
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}
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static void hclge_process_tm_error(struct hclge_dev *hdev,
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enum hclge_err_int_type type)
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{
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hclge_process_tm_sch_error(hdev);
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hclge_process_tm_qcn_error(hdev);
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}
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static const struct hclge_hw_blk hw_blk[] = {
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{ .msk = BIT(0), .name = "IGU_EGU",
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.enable_error = hclge_enable_igu_egu_error,
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@ -743,6 +1026,9 @@ static const struct hclge_hw_blk hw_blk[] = {
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{ .msk = BIT(5), .name = "COMMON",
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.enable_error = hclge_enable_common_error,
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.process_error = hclge_process_common_error, },
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{ .msk = BIT(4), .name = "TM",
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.enable_error = hclge_enable_tm_hw_error,
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.process_error = hclge_process_tm_error, },
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{ .msk = BIT(1), .name = "PPP",
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.enable_error = hclge_enable_ppp_error,
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.process_error = hclge_process_ppp_error, },
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@ -37,6 +37,8 @@
|
|||
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
|
||||
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
|
||||
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
|
||||
#define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3
|
||||
#define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
|
||||
#define HCLGE_NCSI_ERR_INT_EN 0x3
|
||||
#define HCLGE_NCSI_ERR_INT_TYPE 0x9
|
||||
|
||||
|
|
@ -76,5 +78,6 @@ struct hclge_hw_error {
|
|||
};
|
||||
|
||||
int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
|
||||
int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en);
|
||||
pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -6881,6 +6881,12 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Re-enable the TM hw error interrupts because
|
||||
* they get disabled on core/global reset.
|
||||
*/
|
||||
if (hclge_enable_tm_hw_error(hdev, true))
|
||||
dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
|
||||
|
||||
dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
|
||||
HCLGE_DRIVER_NAME);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue