mirror of https://gitee.com/openkylin/linux.git
mmc: tmio: move tmio_mmc_set_clock() to platform hook
tmio_mmc_set_clock() is full of quirks because different SoC vendors extended this in different ways. The original IP defines the divisor range 1/2 ... 1/512. bit 7 is set: 1/512 bit 6 is set: 1/256 ... bit 0 is set: 1/4 all bits clear: 1/2 It is platform-dependent how to achieve the 1/1 clock. I guess the TMIO-MFD variant uses the clock selector outside of this IP, as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c I guess bit[7:0]=0xff is Renesas-specific extension. Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer versions of UniPhier SoC variants use bit 16 for 1/1024. host->clk_update() is only used by the Renesas variants, whereas host->set_clk_div() is only used by the TMIO-MFD variants. To cope with this mess, promote tmio_mmc_set_clock() to a new platform hook ->set_clock(), and melt the old two hooks into it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Masahiro Yamada
Ulf Hansson
parent
74005a01f1
commit
0196c8db83
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@ -152,6 +152,66 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
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return ret == 0 ? best_freq : clk_get_rate(priv->clk);
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}
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static void renesas_sdhi_clk_start(struct tmio_mmc_host *host)
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{
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* HW engineers overrode docs: no sleep needed on R-Car2+ */
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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usleep_range(10000, 11000);
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}
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static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host)
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{
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* HW engineers overrode docs: no sleep needed on R-Car2+ */
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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usleep_range(10000, 11000);
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}
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static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
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unsigned int new_clock)
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{
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u32 clk = 0, clock;
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if (new_clock == 0) {
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renesas_sdhi_clk_stop(host);
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return;
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}
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/*
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* Both HS400 and HS200/SD104 set 200MHz, but some devices need to
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* set 400MHz to distinguish the CPG settings in HS400.
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*/
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if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
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host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
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new_clock == 200000000)
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new_clock = 400000000;
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clock = renesas_sdhi_clk_update(host, new_clock) / 512;
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for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
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clock <<= 1;
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/* 1/1 clock is option */
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if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
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if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
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clk |= 0xff;
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else
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clk &= ~0xff;
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}
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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usleep_range(10000, 11000);
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renesas_sdhi_clk_start(host);
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}
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static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
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{
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struct renesas_sdhi *priv = host_to_priv(host);
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@ -617,8 +677,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
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host->write16_hook = renesas_sdhi_write16_hook;
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host->clk_enable = renesas_sdhi_clk_enable;
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host->clk_update = renesas_sdhi_clk_update;
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host->clk_disable = renesas_sdhi_clk_disable;
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host->set_clock = renesas_sdhi_set_clock;
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host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
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host->dma_ops = dma_ops;
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@ -10,6 +10,7 @@
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* Copyright (C) 2004 Ian Molton
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/tmio.h>
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@ -20,6 +21,52 @@
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#include "tmio_mmc.h"
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static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
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{
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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usleep_range(10000, 11000);
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sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
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usleep_range(10000, 11000);
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}
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static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
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{
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sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
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usleep_range(10000, 11000);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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usleep_range(10000, 11000);
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}
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static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
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unsigned int new_clock)
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{
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u32 clk = 0, clock;
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if (new_clock == 0) {
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tmio_mmc_clk_stop(host);
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return;
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}
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clock = host->mmc->f_min;
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for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
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clock <<= 1;
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host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
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usleep_range(10000, 11000);
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tmio_mmc_clk_start(host);
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}
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#ifdef CONFIG_PM_SLEEP
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static int tmio_mmc_suspend(struct device *dev)
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{
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@ -97,6 +144,7 @@ static int tmio_mmc_probe(struct platform_device *pdev)
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/* SD control register space size is 0x200, 0x400 for bus_shift=1 */
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host->bus_shift = resource_size(res) >> 10;
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host->set_clock = tmio_mmc_set_clock;
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host->mmc->f_max = pdata->hclk;
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host->mmc->f_min = pdata->hclk / 512;
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@ -129,7 +129,6 @@ struct tmio_mmc_host {
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/* Callbacks for clock / power control */
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void (*set_pwr)(struct platform_device *host, int state);
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void (*set_clk_div)(struct platform_device *host, int state);
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/* pio related stuff */
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struct scatterlist *sg_ptr;
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@ -166,10 +165,9 @@ struct tmio_mmc_host {
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/* Mandatory callback */
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int (*clk_enable)(struct tmio_mmc_host *host);
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void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
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/* Optional callbacks */
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unsigned int (*clk_update)(struct tmio_mmc_host *host,
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unsigned int new_clock);
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void (*clk_disable)(struct tmio_mmc_host *host);
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int (*multi_io_quirk)(struct mmc_card *card,
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unsigned int direction, int blk_size);
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@ -157,83 +157,6 @@ static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
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}
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}
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static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
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{
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* HW engineers overrode docs: no sleep needed on R-Car2+ */
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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usleep_range(10000, 11000);
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if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
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sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
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usleep_range(10000, 11000);
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}
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}
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static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
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{
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if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
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sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
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usleep_range(10000, 11000);
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}
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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/* HW engineers overrode docs: no sleep needed on R-Car2+ */
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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usleep_range(10000, 11000);
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}
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static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
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unsigned int new_clock)
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{
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u32 clk = 0, clock;
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if (new_clock == 0) {
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tmio_mmc_clk_stop(host);
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return;
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}
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/*
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* Both HS400 and HS200/SD104 set 200MHz, but some devices need to
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* set 400MHz to distinguish the CPG settings in HS400.
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*/
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if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
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host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
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new_clock == 200000000)
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new_clock = 400000000;
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if (host->clk_update)
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clock = host->clk_update(host, new_clock) / 512;
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else
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clock = host->mmc->f_min;
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for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
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clock <<= 1;
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/* 1/1 clock is option */
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if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) &&
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((clk >> 22) & 0x1)) {
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if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
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clk |= 0xff;
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else
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clk &= ~0xff;
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}
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if (host->set_clk_div)
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host->set_clk_div(host->pdev, (clk >> 22) & 1);
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
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sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
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sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
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if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
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usleep_range(10000, 11000);
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tmio_mmc_clk_start(host);
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}
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static void tmio_mmc_reset(struct tmio_mmc_host *host)
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{
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/* FIXME - should we set stop clock reg here */
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@ -1040,15 +963,15 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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switch (ios->power_mode) {
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case MMC_POWER_OFF:
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tmio_mmc_power_off(host);
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tmio_mmc_set_clock(host, 0);
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host->set_clock(host, 0);
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break;
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case MMC_POWER_UP:
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tmio_mmc_power_on(host, ios->vdd);
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tmio_mmc_set_clock(host, ios->clock);
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host->set_clock(host, ios->clock);
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tmio_mmc_set_bus_width(host, ios->bus_width);
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break;
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case MMC_POWER_ON:
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tmio_mmc_set_clock(host, ios->clock);
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host->set_clock(host, ios->clock);
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tmio_mmc_set_bus_width(host, ios->bus_width);
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break;
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}
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@ -1234,7 +1157,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
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int ret;
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/*
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* Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
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* Check the sanity of mmc->f_min to prevent host->set_clock() from
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* looping forever...
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*/
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if (mmc->f_min == 0)
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@ -1244,7 +1167,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
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_host->write16_hook = NULL;
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_host->set_pwr = pdata->set_pwr;
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_host->set_clk_div = pdata->set_clk_div;
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ret = tmio_mmc_init_ocr(_host);
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if (ret < 0)
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@ -1307,7 +1229,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
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if (pdata->flags & TMIO_MMC_SDIO_IRQ)
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_host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
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tmio_mmc_set_clock(_host, 0);
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_host->set_clock(_host, 0);
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tmio_mmc_reset(_host);
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_host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
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@ -1391,7 +1313,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev)
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tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
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if (host->clk_cache)
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tmio_mmc_set_clock(host, 0);
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host->set_clock(host, 0);
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tmio_mmc_clk_disable(host);
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@ -1412,7 +1334,7 @@ int tmio_mmc_host_runtime_resume(struct device *dev)
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tmio_mmc_clk_enable(host);
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if (host->clk_cache)
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tmio_mmc_set_clock(host, host->clk_cache);
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host->set_clock(host, host->clk_cache);
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if (host->native_hotplug)
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tmio_mmc_enable_mmc_irqs(host,
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