mirror of https://gitee.com/openkylin/linux.git
mmc: sdhci-pci: add support of O2Micro/BayHubTech SD hosts
Add O2Micro/BayHubTech SD Host DeviceId 8520 support. Add O2Micro/BayHubTech SD Host DeviceId 8420 & 8421 support. Add O2Micro/BayHubTech SD Host DeviceId 8620 & 8621 support. These card readers are used in laptops like Lenovo ThinkPad W540, Dell Latitude E5440, Dell Latitude E6540. Signed-off-by: Peter Guo <peter.guo@bayhubtech.com> Signed-off-by: Adam Lee <adam.lee@canonical.com> Signed-off-by: Chris Ball <chris@printf.net>
This commit is contained in:
Adam Lee
Chris Ball
parent
522624f97e
commit
01acf6917a
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@ -9,6 +9,7 @@ obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
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obj-$(CONFIG_MMC_SDHCI) += sdhci.o
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obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
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obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-data.o
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obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += sdhci-pci-o2micro.o
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obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
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obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
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obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
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@ -0,0 +1,321 @@
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/*
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* Copyright (C) 2013 BayHub Technology Ltd.
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*
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* Authors: Peter Guo <peter.guo@bayhubtech.com>
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* Adam Lee <adam.lee@canonical.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/pci.h>
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#include "sdhci.h"
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#include "sdhci-pci.h"
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#include "sdhci-pci-o2micro.h"
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void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
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{
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u32 scratch_32;
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int ret;
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/* Improve write performance for SD3.0 */
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ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
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pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
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/* Enable Link abnormal reset generating Reset */
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ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 19) | (1 << 11));
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scratch_32 |= (1 << 10);
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pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
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/* set card power over current protection */
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ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
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if (ret)
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return;
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scratch_32 |= (1 << 4);
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pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
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/* adjust the output delay for SD mode */
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pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
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/* Set the output voltage setting of Aux 1.2v LDO */
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ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(3 << 12);
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pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
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/* Set Max power supply capability of SD host */
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ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x01FE);
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scratch_32 |= 0x00CC;
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pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
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/* Set DLL Tuning Window */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_TUNING_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000000FF);
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scratch_32 |= 0x00000066;
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pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
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/* Set UHS2 T_EIDLE */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_UHS2_L1_CTRL, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000000FC);
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scratch_32 |= 0x00000084;
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pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
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/* Set UHS2 Termination */
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ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~((1 << 21) | (1 << 30));
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/* Set RTD3 function disabled */
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scratch_32 |= ((1 << 29) | (1 << 28));
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pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
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/* Set L1 Entrance Timer */
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ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0xf0000000);
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scratch_32 |= 0x30000000;
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pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_MISC_CTRL4, &scratch_32);
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if (ret)
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return;
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scratch_32 &= ~(0x000f0000);
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scratch_32 |= 0x00080000;
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pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
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}
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EXPORT_SYMBOL_GPL(sdhci_pci_o2_fujin2_pci_init);
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int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
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{
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struct sdhci_pci_chip *chip;
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struct sdhci_host *host;
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u32 reg;
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chip = slot->chip;
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host = slot->host;
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switch (chip->pdev->device) {
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case PCI_DEVICE_ID_O2_SDS0:
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case PCI_DEVICE_ID_O2_SEABIRD0:
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case PCI_DEVICE_ID_O2_SEABIRD1:
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case PCI_DEVICE_ID_O2_SDS1:
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case PCI_DEVICE_ID_O2_FUJIN2:
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reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
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if (reg & 0x1)
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host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
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if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
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break;
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/* set dll watch dog timer */
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reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
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reg |= (1 << 12);
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sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
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break;
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default:
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe_slot);
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int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
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{
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int ret;
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u8 scratch;
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u32 scratch_32;
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switch (chip->pdev->device) {
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case PCI_DEVICE_ID_O2_8220:
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case PCI_DEVICE_ID_O2_8221:
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case PCI_DEVICE_ID_O2_8320:
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case PCI_DEVICE_ID_O2_8321:
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/* This extra setup is required due to broken ADMA. */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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/* Set Multi 3 to VCC3V# */
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pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
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/* Disable CLK_REQ# support after media DET */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_CLKREQ, &scratch);
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if (ret)
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return ret;
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scratch |= 0x20;
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pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
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/* Choose capabilities, enable SDMA. We have to write 0x01
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* to the capabilities register first to unlock it.
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*/
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ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
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if (ret)
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return ret;
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scratch |= 0x01;
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pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
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pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
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/* Disable ADMA1/2 */
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pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
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pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
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/* Disable the infinite transfer mode */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_INF_MOD, &scratch);
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if (ret)
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return ret;
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scratch |= 0x08;
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pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
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/* Lock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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break;
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case PCI_DEVICE_ID_O2_SDS0:
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case PCI_DEVICE_ID_O2_SDS1:
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case PCI_DEVICE_ID_O2_FUJIN2:
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/* UnLock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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/* Set timeout CLK */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CLK_SETTING, &scratch_32);
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if (ret)
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return ret;
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scratch_32 &= ~(0xFF00);
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scratch_32 |= 0x07E0C800;
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pci_write_config_dword(chip->pdev,
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O2_SD_CLK_SETTING, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CLKREQ, &scratch_32);
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if (ret)
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return ret;
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scratch_32 |= 0x3;
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pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, &scratch_32);
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if (ret)
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return ret;
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scratch_32 &= ~(0x1F3F070E);
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scratch_32 |= 0x18270106;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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/* Disable UHS1 funciton */
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_CAP_REG2, &scratch_32);
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if (ret)
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return ret;
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scratch_32 &= ~(0xE0);
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pci_write_config_dword(chip->pdev,
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O2_SD_CAP_REG2, scratch_32);
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if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
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sdhci_pci_o2_fujin2_pci_init(chip);
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/* Lock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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break;
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case PCI_DEVICE_ID_O2_SEABIRD0:
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case PCI_DEVICE_ID_O2_SEABIRD1:
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/* UnLock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch &= 0x7f;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG0, &scratch_32);
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if ((scratch_32 & 0xff000000) == 0x01000000) {
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scratch_32 &= 0x0000FFFF;
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scratch_32 |= 0x1F340000;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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} else {
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scratch_32 &= 0x0000FFFF;
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scratch_32 |= 0x2c280000;
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pci_write_config_dword(chip->pdev,
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O2_SD_PLL_SETTING, scratch_32);
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ret = pci_read_config_dword(chip->pdev,
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O2_SD_FUNC_REG4,
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&scratch_32);
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scratch_32 |= (1 << 22);
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pci_write_config_dword(chip->pdev,
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O2_SD_FUNC_REG4, scratch_32);
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}
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/* Lock WP */
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ret = pci_read_config_byte(chip->pdev,
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O2_SD_LOCK_WP, &scratch);
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if (ret)
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return ret;
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scratch |= 0x80;
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pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(sdhci_pci_o2_probe);
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int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
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{
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sdhci_pci_o2_probe(chip);
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return 0;
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}
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EXPORT_SYMBOL_GPL(sdhci_pci_o2_resume);
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@ -0,0 +1,72 @@
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/*
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* Copyright (C) 2013 BayHub Technology Ltd.
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*
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* Authors: Peter Guo <peter.guo@bayhubtech.com>
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* Adam Lee <adam.lee@canonical.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SDHCI_PCI_O2MICRO_H
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#define __SDHCI_PCI_O2MICRO_H
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#include "sdhci-pci.h"
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/*
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* O2Micro device IDs
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*/
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#define PCI_DEVICE_ID_O2_SDS0 0x8420
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#define PCI_DEVICE_ID_O2_SDS1 0x8421
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#define PCI_DEVICE_ID_O2_FUJIN2 0x8520
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#define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
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#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
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/*
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* O2Micro device registers
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*/
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#define O2_SD_MISC_REG5 0x64
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#define O2_SD_LD0_CTRL 0x68
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#define O2_SD_DEV_CTRL 0x88
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#define O2_SD_LOCK_WP 0xD3
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#define O2_SD_TEST_REG 0xD4
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#define O2_SD_FUNC_REG0 0xDC
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#define O2_SD_MULTI_VCC3V 0xEE
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#define O2_SD_CLKREQ 0xEC
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#define O2_SD_CAPS 0xE0
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#define O2_SD_ADMA1 0xE2
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#define O2_SD_ADMA2 0xE7
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#define O2_SD_INF_MOD 0xF1
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#define O2_SD_MISC_CTRL4 0xFC
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#define O2_SD_TUNING_CTRL 0x300
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#define O2_SD_PLL_SETTING 0x304
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#define O2_SD_CLK_SETTING 0x328
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#define O2_SD_CAP_REG2 0x330
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#define O2_SD_CAP_REG0 0x334
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#define O2_SD_UHS1_CAP_SETTING 0x33C
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#define O2_SD_DELAY_CTRL 0x350
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#define O2_SD_UHS2_L1_CTRL 0x35C
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#define O2_SD_FUNC_REG3 0x3E0
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#define O2_SD_FUNC_REG4 0x3E4
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#define O2_SD_VENDOR_SETTING 0x110
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#define O2_SD_VENDOR_SETTING2 0x1C8
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extern void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip);
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extern int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot);
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extern int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip);
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extern int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip);
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#endif /* __SDHCI_PCI_O2MICRO_H */
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@ -28,6 +28,7 @@
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#include "sdhci.h"
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#include "sdhci-pci.h"
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#include "sdhci-pci-o2micro.h"
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/*****************************************************************************\
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* *
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@ -321,65 +322,6 @@ static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
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#define O2_SD_ADMA2 0xE7
|
||||
#define O2_SD_INF_MOD 0xF1
|
||||
|
||||
static int o2_probe(struct sdhci_pci_chip *chip)
|
||||
{
|
||||
int ret;
|
||||
u8 scratch;
|
||||
|
||||
switch (chip->pdev->device) {
|
||||
case PCI_DEVICE_ID_O2_8220:
|
||||
case PCI_DEVICE_ID_O2_8221:
|
||||
case PCI_DEVICE_ID_O2_8320:
|
||||
case PCI_DEVICE_ID_O2_8321:
|
||||
/* This extra setup is required due to broken ADMA. */
|
||||
ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
|
||||
if (ret)
|
||||
return ret;
|
||||
scratch &= 0x7f;
|
||||
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
||||
|
||||
/* Set Multi 3 to VCC3V# */
|
||||
pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
|
||||
|
||||
/* Disable CLK_REQ# support after media DET */
|
||||
ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
|
||||
if (ret)
|
||||
return ret;
|
||||
scratch |= 0x20;
|
||||
pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
|
||||
|
||||
/* Choose capabilities, enable SDMA. We have to write 0x01
|
||||
* to the capabilities register first to unlock it.
|
||||
*/
|
||||
ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
|
||||
if (ret)
|
||||
return ret;
|
||||
scratch |= 0x01;
|
||||
pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
|
||||
pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
|
||||
|
||||
/* Disable ADMA1/2 */
|
||||
pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
|
||||
pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
|
||||
|
||||
/* Disable the infinite transfer mode */
|
||||
ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
|
||||
if (ret)
|
||||
return ret;
|
||||
scratch |= 0x08;
|
||||
pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
|
||||
|
||||
/* Lock WP */
|
||||
ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
|
||||
if (ret)
|
||||
return ret;
|
||||
scratch |= 0x80;
|
||||
pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
|
||||
{
|
||||
u8 scratch;
|
||||
|
|
@ -570,7 +512,10 @@ static int jmicron_resume(struct sdhci_pci_chip *chip)
|
|||
}
|
||||
|
||||
static const struct sdhci_pci_fixes sdhci_o2 = {
|
||||
.probe = o2_probe,
|
||||
.probe = sdhci_pci_o2_probe,
|
||||
.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
|
||||
.probe_slot = sdhci_pci_o2_probe_slot,
|
||||
.resume = sdhci_pci_o2_resume,
|
||||
};
|
||||
|
||||
static const struct sdhci_pci_fixes sdhci_jmicron = {
|
||||
|
|
@ -983,6 +928,46 @@ static const struct pci_device_id pci_ids[] = {
|
|||
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
||||
},
|
||||
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_O2,
|
||||
.device = PCI_DEVICE_ID_O2_FUJIN2,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
||||
},
|
||||
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_O2,
|
||||
.device = PCI_DEVICE_ID_O2_SDS0,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
||||
},
|
||||
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_O2,
|
||||
.device = PCI_DEVICE_ID_O2_SDS1,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
||||
},
|
||||
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_O2,
|
||||
.device = PCI_DEVICE_ID_O2_SEABIRD0,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
||||
},
|
||||
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_O2,
|
||||
.device = PCI_DEVICE_ID_O2_SEABIRD1,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.driver_data = (kernel_ulong_t)&sdhci_o2,
|
||||
},
|
||||
|
||||
{ /* Generic SD host controller */
|
||||
PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue