mirror of https://gitee.com/openkylin/linux.git
spi: sh-msiof: Add more register documentation
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Geert Uytterhoeven
Mark Brown
parent
6a85fc5af1
commit
01cfef57ef
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@ -42,32 +42,80 @@ struct sh_msiof_spi_priv {
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int rx_fifo_size;
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};
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#define TMDR1 0x00
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#define TMDR2 0x04
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#define TMDR3 0x08
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#define RMDR1 0x10
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#define RMDR2 0x14
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#define RMDR3 0x18
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#define TSCR 0x20
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#define RSCR 0x22
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#define CTR 0x28
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#define FCTR 0x30
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#define STR 0x40
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#define IER 0x44
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#define TDR1 0x48
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#define TDR2 0x4c
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#define TFDR 0x50
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#define RDR1 0x58
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#define RDR2 0x5c
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#define RFDR 0x60
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#define TMDR1 0x00 /* Transmit Mode Register 1 */
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#define TMDR2 0x04 /* Transmit Mode Register 2 */
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#define TMDR3 0x08 /* Transmit Mode Register 3 */
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#define RMDR1 0x10 /* Receive Mode Register 1 */
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#define RMDR2 0x14 /* Receive Mode Register 2 */
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#define RMDR3 0x18 /* Receive Mode Register 3 */
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#define TSCR 0x20 /* Transmit Clock Select Register */
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#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
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#define CTR 0x28 /* Control Register */
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#define FCTR 0x30 /* FIFO Control Register */
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#define STR 0x40 /* Status Register */
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#define IER 0x44 /* Interrupt Enable Register */
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#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
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#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
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#define TFDR 0x50 /* Transmit FIFO Data Register */
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#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
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#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
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#define RFDR 0x60 /* Receive FIFO Data Register */
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#define CTR_TSCKE (1 << 15)
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#define CTR_TFSE (1 << 14)
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#define CTR_TXE (1 << 9)
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#define CTR_RXE (1 << 8)
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/* TMDR1 and RMDR1 */
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#define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
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#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
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#define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
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#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
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#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
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#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
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#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */
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#define MDR1_FLD_SHIFT 2
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#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
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/* TMDR1 */
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#define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
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/* TMDR2 and RMDR2 */
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#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
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#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
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#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
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/* TSCR and RSCR */
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#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
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#define SCR_BRPS(i) (((i) - 1) << 8)
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#define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
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#define SCR_BRDV_DIV_2 0x0000
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#define SCR_BRDV_DIV_4 0x0001
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#define SCR_BRDV_DIV_8 0x0002
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#define SCR_BRDV_DIV_16 0x0003
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#define SCR_BRDV_DIV_32 0x0004
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#define SCR_BRDV_DIV_1 0x0007
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/* CTR */
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#define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
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#define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
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#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
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#define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
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#define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
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#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
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#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
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#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
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#define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
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#define CTR_TXDIZ_LOW 0x00000000 /* 0 */
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#define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
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#define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
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#define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
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#define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
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#define CTR_TXE 0x00000200 /* Transmit Enable */
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#define CTR_RXE 0x00000100 /* Receive Enable */
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/* STR and IER */
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#define STR_TEOF 0x00800000 /* Frame Transmission End */
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#define STR_REOF 0x00000080 /* Frame Reception End */
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#define DEFAULT_TX_FIFO_SIZE 64
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#define DEFAULT_RX_FIFO_SIZE 64
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#define STR_TEOF (1 << 23)
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#define STR_REOF (1 << 7)
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static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
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{
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@ -131,17 +179,17 @@ static struct {
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unsigned short div;
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unsigned short scr;
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} const sh_msiof_spi_clk_table[] = {
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{ 1, 0x0007 },
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{ 2, 0x0000 },
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{ 4, 0x0001 },
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{ 8, 0x0002 },
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{ 16, 0x0003 },
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{ 32, 0x0004 },
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{ 64, 0x1f00 },
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{ 128, 0x1f01 },
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{ 256, 0x1f02 },
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{ 512, 0x1f03 },
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{ 1024, 0x1f04 },
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{ 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 },
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{ 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 },
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{ 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 },
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{ 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 },
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{ 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 },
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{ 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 },
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{ 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 },
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{ 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 },
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{ 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 },
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{ 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 },
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{ 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 },
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};
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static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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@ -182,21 +230,21 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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*/
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sh_msiof_write(p, FCTR, 0);
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tmp = 0;
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tmp |= !cs_high << 25;
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tmp |= lsb_first << 24;
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sh_msiof_write(p, TMDR1, 0xe0000005 | tmp);
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sh_msiof_write(p, RMDR1, 0x20000005 | tmp);
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tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
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tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
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tmp |= lsb_first << MDR1_BITLSB_SHIFT;
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sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
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sh_msiof_write(p, RMDR1, tmp);
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tmp = 0xa0000000;
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tmp |= cpol << 30; /* TSCKIZ */
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tmp |= cpol << 28; /* RSCKIZ */
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tmp = 0;
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tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
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tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
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edge = cpol ^ !cpha;
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tmp |= edge << 27; /* TEDG */
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tmp |= edge << 26; /* REDG */
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tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
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tmp |= edge << CTR_TEDG_SHIFT;
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tmp |= edge << CTR_REDG_SHIFT;
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tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
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sh_msiof_write(p, CTR, tmp);
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}
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@ -204,12 +252,12 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
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const void *tx_buf, void *rx_buf,
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u32 bits, u32 words)
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{
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u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16);
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u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
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if (tx_buf)
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sh_msiof_write(p, TMDR2, dr2);
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else
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sh_msiof_write(p, TMDR2, dr2 | 1);
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sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
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if (rx_buf)
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sh_msiof_write(p, RMDR2, dr2);
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@ -695,8 +743,8 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
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pm_runtime_enable(&pdev->dev);
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/* The standard version of MSIOF use 64 word FIFOs */
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p->tx_fifo_size = 64;
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p->rx_fifo_size = 64;
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p->tx_fifo_size = DEFAULT_TX_FIFO_SIZE;
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p->rx_fifo_size = DEFAULT_RX_FIFO_SIZE;
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/* Platform data may override FIFO sizes */
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if (p->info->tx_fifo_override)
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