mirror of https://gitee.com/openkylin/linux.git
ASoC: SOF: Intel: CNL: add support for sending compact IPC
For compact IPCs, we will send the IPC header/command via the HIPCIDR register and the first 32bit payload via the HIPCIDD register, no mailbox will be used. Signed-off-by: Keyon Jie <yang.jie@linux.intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Link: https://lore.kernel.org/r/20191025224122.7718-19-pierre-louis.bossart@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -17,6 +17,7 @@
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#include "../ops.h"
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#include "hda.h"
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#include "hda-ipc.h"
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static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
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{"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
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@ -150,14 +151,45 @@ static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
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CNL_DSP_REG_HIPCCTL_DONE);
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}
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static bool cnl_compact_ipc_compress(struct snd_sof_ipc_msg *msg,
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u32 *dr, u32 *dd)
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{
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struct sof_ipc_pm_gate *pm_gate;
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if (msg->header == (SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE)) {
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pm_gate = msg->msg_data;
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/* send the compact message via the primary register */
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*dr = HDA_IPC_MSG_COMPACT | HDA_IPC_PM_GATE;
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/* send payload via the extended data register */
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*dd = pm_gate->flags;
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return true;
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}
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return false;
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}
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static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
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struct snd_sof_ipc_msg *msg)
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{
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/* send the message */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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CNL_DSP_REG_HIPCIDR_BUSY);
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u32 dr = 0;
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u32 dd = 0;
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if (cnl_compact_ipc_compress(msg, &dr, &dd)) {
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/* send the message via IPC registers */
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDD,
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dd);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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CNL_DSP_REG_HIPCIDR_BUSY | dr);
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} else {
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/* send the message via mailbox */
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sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
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msg->msg_size);
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snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
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CNL_DSP_REG_HIPCIDR_BUSY);
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}
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return 0;
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}
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@ -312,6 +312,7 @@
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#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
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#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
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#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
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#define CNL_DSP_REG_HIPCIDD (CNL_DSP_IPC_BASE + 0x18)
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#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
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/* HIPCI */
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