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MIPS: Octeon: Remove vestiges of CONFIG_CAVIUM_DECODE_RSL
This config option doesn't exist any more, remove the leftover code for it too. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5302/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -40,12 +40,6 @@
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#include <asm/octeon/pci-octeon.h>
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#include <asm/octeon/cvmx-mio-defs.h>
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#ifdef CONFIG_CAVIUM_DECODE_RSL
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extern void cvmx_interrupt_rsl_decode(void);
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extern int __cvmx_interrupt_ecc_report_single_bit_errors;
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extern void cvmx_interrupt_rsl_enable(void);
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#endif
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extern struct plat_smp_ops octeon_smp_ops;
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#ifdef CONFIG_PCI
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@ -462,18 +456,6 @@ static void octeon_halt(void)
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octeon_kill_core(NULL);
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}
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/**
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* Handle all the error condition interrupts that might occur.
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*
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*/
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#ifdef CONFIG_CAVIUM_DECODE_RSL
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static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
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{
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cvmx_interrupt_rsl_decode();
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return IRQ_HANDLED;
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}
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#endif
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/**
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* Return a string representing the system type
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*
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@ -1064,15 +1046,6 @@ void prom_free_prom_memory(void)
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panic("Core-14449 WAR not in place (%04x).\n"
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"Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
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}
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#ifdef CONFIG_CAVIUM_DECODE_RSL
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cvmx_interrupt_rsl_enable();
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/* Add an interrupt handler for general failures. */
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if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
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"RML/RSL", octeon_rlm_interrupt)) {
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panic("Unable to request_irq(OCTEON_IRQ_RML)");
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}
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#endif
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}
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int octeon_prune_device_tree(void);
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