mirror of https://gitee.com/openkylin/linux.git
cxl: Remove function write_timebase_ctrl_psl9() for PSL9
For PSL9 the contents of PSL_TB_CTLSTAT register have changed in PSL9 and all of the register is now readonly. Hence we don't need an sl_ops implementation for 'write_timebase_ctrl' for to populate this register for PSL9. Hence this patch removes function write_timebase_ctrl_psl9() and its references from the code. Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -572,12 +572,6 @@ static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_
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/* For the PSL this is a multiple for 0 < n <= 7: */
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#define PSL_2048_250MHZ_CYCLES 1
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static void write_timebase_ctrl_psl9(struct cxl *adapter)
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{
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cxl_p1_write(adapter, CXL_PSL9_TB_CTLSTAT,
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TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
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}
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static void write_timebase_ctrl_psl8(struct cxl *adapter)
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{
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cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
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@ -639,7 +633,8 @@ static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
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* Setup PSL Timebase Control and Status register
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* with the recommended Timebase Sync Count value
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*/
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adapter->native->sl_ops->write_timebase_ctrl(adapter);
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if (adapter->native->sl_ops->write_timebase_ctrl)
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adapter->native->sl_ops->write_timebase_ctrl(adapter);
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/* Enable PSL Timebase */
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cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
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@ -1805,7 +1800,6 @@ static const struct cxl_service_layer_ops psl9_ops = {
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.psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
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.err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
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.debugfs_stop_trace = cxl_stop_trace_psl9,
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.write_timebase_ctrl = write_timebase_ctrl_psl9,
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.timebase_read = timebase_read_psl9,
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.capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
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.needs_reset_before_disable = true,
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