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drm/radeon: Restrict offset for legacy display engine. 

The hardware only takes 27 bits for the offset, so larger offsets are
truncated, and the display shows random bits other than the intended ones.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Michel Dänzer 2012-03-14 17:12:42 +01:00 committed by Dave Airlie
parent c4353016da
commit 0349af70da
3 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/radeon/radeon_display.c
View File

@ -402,7 +402,9 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
DRM_ERROR("failed to reserve new rbo buffer before flip\n");
goto pflip_cleanup;
}
r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
/* Only 27 bit offset for legacy CRTC */
r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
if (unlikely(r != 0)) {
radeon_bo_unreserve(rbo);
r = -EINVAL;

5
drivers/gpu/drm/radeon/radeon_fb.c
View File

@ -164,7 +164,10 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
ret = radeon_bo_reserve(rbo, false);
if (unlikely(ret != 0))
goto out_unref;
ret = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, NULL);
/* Only 27 bit offset for legacy CRTC */
ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
NULL);
if (ret) {
radeon_bo_unreserve(rbo);
goto out_unref;

4
drivers/gpu/drm/radeon/radeon_legacy_crtc.c
View File

@ -419,7 +419,9 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
r = radeon_bo_reserve(rbo, false);
if (unlikely(r != 0))
return r;
r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
/* Only 27 bit offset for legacy CRTC */
r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
&base);
if (unlikely(r != 0)) {
radeon_bo_unreserve(rbo);
return -EINVAL;