mirror of https://gitee.com/openkylin/linux.git
drm/nv50/fifo: use hardware channel kickoff functionality
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
71af5e62db
commit
03bd6efa14
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@ -190,7 +190,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
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chan->user_get_hi = 0x60;
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/* disable the fifo caches */
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if (dev_priv->card_type < NV_C0)
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if (dev_priv->card_type < NV_50)
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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/* Construct initial RAMFC for new channel */
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@ -200,7 +200,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
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return ret;
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}
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if (dev_priv->card_type < NV_C0)
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if (dev_priv->card_type < NV_50)
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nv_wr32(dev, NV03_PFIFO_CACHES, 1);
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/* Insert NOPs for NOUVEAU_DMA_SKIPS */
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@ -306,7 +306,7 @@ nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
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nouveau_channel_idle(chan);
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/* boot it off the hardware */
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if (dev_priv->card_type < NV_C0)
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if (dev_priv->card_type < NV_50)
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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/* destroy the engine specific contexts */
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@ -318,7 +318,7 @@ nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
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pfifo->destroy_context(chan);
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}
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if (dev_priv->card_type < NV_C0)
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if (dev_priv->card_type < NV_50)
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nv_wr32(dev, NV03_PFIFO_CACHES, 1);
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/* aside from its resources, the channel should now be dead,
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@ -221,7 +221,7 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
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nouveau_channel_idle(chan);
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}
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if (dev_priv->card_type < NV_C0) {
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if (dev_priv->card_type < NV_50) {
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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nv_mask(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
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@ -269,7 +269,7 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
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if (dev_priv->eng[e])
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dev_priv->eng[e]->init(dev, e);
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}
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if (dev_priv->card_type < NV_C0) {
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if (dev_priv->card_type < NV_50) {
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
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nv_wr32(dev, NV03_PFIFO_CACHES, 1);
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@ -292,44 +292,46 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
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return 0;
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}
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static bool
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nv50_fifo_wait_kickoff(void *data)
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{
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struct drm_nouveau_private *dev_priv = data;
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struct drm_device *dev = dev_priv->dev;
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if (dev_priv->chipset == 0x50) {
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u32 me_enable = nv_mask(dev, 0x00b860, 0x00000001, 0x00000001);
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nv_wr32(dev, 0x00b860, me_enable);
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}
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return nv_rd32(dev, 0x0032fc) != 0xffffffff;
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}
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void
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nv50_fifo_destroy_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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unsigned long flags;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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/* remove channel from playlist, will context switch if active */
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_wr32(dev, NV03_PFIFO_CACHES, 0);
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/* Unload the context if it's the currently active one */
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if ((nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x7f) == chan->id) {
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nv_mask(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 0);
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nv_mask(dev, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
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pfifo->unload_context(dev);
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1);
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nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
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}
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nv50_fifo_channel_disable(dev, chan->id);
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/* Dummy channel, also used on ch 127 */
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if (chan->id == 0)
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nv50_fifo_channel_disable(dev, 127);
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nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000);
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nv50_fifo_playlist_update(dev);
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nv_wr32(dev, NV03_PFIFO_CACHES, 1);
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/* tell any engines on this channel to unload their contexts */
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nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
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if (!nv_wait_cb(dev, nv50_fifo_wait_kickoff, dev_priv))
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NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
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nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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/* Free the channel resources */
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/* clean up */
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if (chan->user) {
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iounmap(chan->user);
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chan->user = NULL;
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}
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nouveau_gpuobj_ref(NULL, &chan->ramfc);
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nouveau_gpuobj_ref(NULL, &chan->cache);
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}
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@ -337,68 +339,6 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
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int
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nv50_fifo_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramfc = chan->ramfc;
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struct nouveau_gpuobj *cache = chan->cache;
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int ptr, cnt;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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nv_wr32(dev, 0x3330, nv_ro32(ramfc, 0x00));
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nv_wr32(dev, 0x3334, nv_ro32(ramfc, 0x04));
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nv_wr32(dev, 0x3240, nv_ro32(ramfc, 0x08));
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nv_wr32(dev, 0x3320, nv_ro32(ramfc, 0x0c));
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nv_wr32(dev, 0x3244, nv_ro32(ramfc, 0x10));
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nv_wr32(dev, 0x3328, nv_ro32(ramfc, 0x14));
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nv_wr32(dev, 0x3368, nv_ro32(ramfc, 0x18));
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nv_wr32(dev, 0x336c, nv_ro32(ramfc, 0x1c));
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nv_wr32(dev, 0x3370, nv_ro32(ramfc, 0x20));
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nv_wr32(dev, 0x3374, nv_ro32(ramfc, 0x24));
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nv_wr32(dev, 0x3378, nv_ro32(ramfc, 0x28));
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nv_wr32(dev, 0x337c, nv_ro32(ramfc, 0x2c));
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nv_wr32(dev, 0x3228, nv_ro32(ramfc, 0x30));
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nv_wr32(dev, 0x3364, nv_ro32(ramfc, 0x34));
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nv_wr32(dev, 0x32a0, nv_ro32(ramfc, 0x38));
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nv_wr32(dev, 0x3224, nv_ro32(ramfc, 0x3c));
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nv_wr32(dev, 0x324c, nv_ro32(ramfc, 0x40));
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nv_wr32(dev, 0x2044, nv_ro32(ramfc, 0x44));
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nv_wr32(dev, 0x322c, nv_ro32(ramfc, 0x48));
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nv_wr32(dev, 0x3234, nv_ro32(ramfc, 0x4c));
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nv_wr32(dev, 0x3340, nv_ro32(ramfc, 0x50));
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nv_wr32(dev, 0x3344, nv_ro32(ramfc, 0x54));
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nv_wr32(dev, 0x3280, nv_ro32(ramfc, 0x58));
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nv_wr32(dev, 0x3254, nv_ro32(ramfc, 0x5c));
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nv_wr32(dev, 0x3260, nv_ro32(ramfc, 0x60));
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nv_wr32(dev, 0x3264, nv_ro32(ramfc, 0x64));
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nv_wr32(dev, 0x3268, nv_ro32(ramfc, 0x68));
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nv_wr32(dev, 0x326c, nv_ro32(ramfc, 0x6c));
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nv_wr32(dev, 0x32e4, nv_ro32(ramfc, 0x70));
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nv_wr32(dev, 0x3248, nv_ro32(ramfc, 0x74));
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nv_wr32(dev, 0x2088, nv_ro32(ramfc, 0x78));
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nv_wr32(dev, 0x2058, nv_ro32(ramfc, 0x7c));
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nv_wr32(dev, 0x2210, nv_ro32(ramfc, 0x80));
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cnt = nv_ro32(ramfc, 0x84);
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for (ptr = 0; ptr < cnt; ptr++) {
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nv_wr32(dev, NV40_PFIFO_CACHE1_METHOD(ptr),
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nv_ro32(cache, (ptr * 8) + 0));
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nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
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nv_ro32(cache, (ptr * 8) + 4));
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}
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
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/* guessing that all the 0x34xx regs aren't on NV50 */
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if (dev_priv->chipset != 0x50) {
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nv_wr32(dev, 0x340c, nv_ro32(ramfc, 0x88));
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nv_wr32(dev, 0x3400, nv_ro32(ramfc, 0x8c));
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nv_wr32(dev, 0x3404, nv_ro32(ramfc, 0x90));
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nv_wr32(dev, 0x3408, nv_ro32(ramfc, 0x94));
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nv_wr32(dev, 0x3410, nv_ro32(ramfc, 0x98));
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}
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
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return 0;
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}
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@ -406,85 +346,22 @@ int
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nv50_fifo_unload_context(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramfc, *cache;
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struct nouveau_channel *chan = NULL;
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int chid, get, put, ptr;
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int i;
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NV_DEBUG(dev, "\n");
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/* set playlist length to zero, fifo will unload context */
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nv_wr32(dev, 0x0032ec, 0);
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chid = nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) & 0x7f;
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if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
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return 0;
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chan = dev_priv->channels.ptr[chid];
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if (!chan) {
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NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
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return -EINVAL;
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}
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NV_DEBUG(dev, "ch%d\n", chan->id);
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ramfc = chan->ramfc;
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cache = chan->cache;
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nv_wo32(ramfc, 0x00, nv_rd32(dev, 0x3330));
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nv_wo32(ramfc, 0x04, nv_rd32(dev, 0x3334));
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nv_wo32(ramfc, 0x08, nv_rd32(dev, 0x3240));
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nv_wo32(ramfc, 0x0c, nv_rd32(dev, 0x3320));
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nv_wo32(ramfc, 0x10, nv_rd32(dev, 0x3244));
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nv_wo32(ramfc, 0x14, nv_rd32(dev, 0x3328));
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nv_wo32(ramfc, 0x18, nv_rd32(dev, 0x3368));
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nv_wo32(ramfc, 0x1c, nv_rd32(dev, 0x336c));
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nv_wo32(ramfc, 0x20, nv_rd32(dev, 0x3370));
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nv_wo32(ramfc, 0x24, nv_rd32(dev, 0x3374));
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nv_wo32(ramfc, 0x28, nv_rd32(dev, 0x3378));
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nv_wo32(ramfc, 0x2c, nv_rd32(dev, 0x337c));
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nv_wo32(ramfc, 0x30, nv_rd32(dev, 0x3228));
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nv_wo32(ramfc, 0x34, nv_rd32(dev, 0x3364));
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nv_wo32(ramfc, 0x38, nv_rd32(dev, 0x32a0));
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nv_wo32(ramfc, 0x3c, nv_rd32(dev, 0x3224));
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nv_wo32(ramfc, 0x40, nv_rd32(dev, 0x324c));
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nv_wo32(ramfc, 0x44, nv_rd32(dev, 0x2044));
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nv_wo32(ramfc, 0x48, nv_rd32(dev, 0x322c));
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nv_wo32(ramfc, 0x4c, nv_rd32(dev, 0x3234));
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nv_wo32(ramfc, 0x50, nv_rd32(dev, 0x3340));
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nv_wo32(ramfc, 0x54, nv_rd32(dev, 0x3344));
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nv_wo32(ramfc, 0x58, nv_rd32(dev, 0x3280));
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nv_wo32(ramfc, 0x5c, nv_rd32(dev, 0x3254));
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nv_wo32(ramfc, 0x60, nv_rd32(dev, 0x3260));
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nv_wo32(ramfc, 0x64, nv_rd32(dev, 0x3264));
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nv_wo32(ramfc, 0x68, nv_rd32(dev, 0x3268));
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nv_wo32(ramfc, 0x6c, nv_rd32(dev, 0x326c));
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nv_wo32(ramfc, 0x70, nv_rd32(dev, 0x32e4));
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nv_wo32(ramfc, 0x74, nv_rd32(dev, 0x3248));
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nv_wo32(ramfc, 0x78, nv_rd32(dev, 0x2088));
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nv_wo32(ramfc, 0x7c, nv_rd32(dev, 0x2058));
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nv_wo32(ramfc, 0x80, nv_rd32(dev, 0x2210));
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put = (nv_rd32(dev, NV03_PFIFO_CACHE1_PUT) & 0x7ff) >> 2;
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get = (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) & 0x7ff) >> 2;
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ptr = 0;
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while (put != get) {
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nv_wo32(cache, ptr + 0,
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nv_rd32(dev, NV40_PFIFO_CACHE1_METHOD(get)));
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nv_wo32(cache, ptr + 4,
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nv_rd32(dev, NV40_PFIFO_CACHE1_DATA(get)));
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get = (get + 1) & 0x1ff;
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ptr += 8;
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/* tell all connected engines to unload their contexts */
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for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
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struct nouveau_channel *chan = dev_priv->channels.ptr[i];
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if (chan)
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nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
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if (!nv_wait_cb(dev, nv50_fifo_wait_kickoff, dev_priv)) {
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NV_INFO(dev, "PFIFO: channel %d unload timeout\n", i);
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return -EBUSY;
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}
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}
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/* guessing that all the 0x34xx regs aren't on NV50 */
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if (dev_priv->chipset != 0x50) {
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nv_wo32(ramfc, 0x84, ptr >> 3);
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nv_wo32(ramfc, 0x88, nv_rd32(dev, 0x340c));
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nv_wo32(ramfc, 0x8c, nv_rd32(dev, 0x3400));
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nv_wo32(ramfc, 0x90, nv_rd32(dev, 0x3404));
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nv_wo32(ramfc, 0x94, nv_rd32(dev, 0x3408));
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nv_wo32(ramfc, 0x98, nv_rd32(dev, 0x3410));
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}
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dev_priv->engine.instmem.flush(dev);
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/*XXX: probably reload ch127 (NULL) state back too */
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 127);
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return 0;
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}
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