openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

ACPI: SPCR: work around clock issue on xgene UART 

xgene v1/v2 8250 UARTs don't run at the standard clock rate expected by
the driver and there is no information on clocking available from the
SPCR table. As there has been no progress on relevant vendors updating
DBG2/SPCR specifications to fix this work around this using the previous
xgene quirk handling to avoid setting a baud rate and therefore using
the UART as configured by firmware.

Signed-off-by: Graeme Gregory <graeme.gregory@linaro.org>
Tested-by: Mark Salter <msalter@redhat.com>
Reviewed-by: Mark Salter <msalter@redhat.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
Graeme Gregory 2017-08-04 22:49:44 +01:00 committed by Rafael J. Wysocki
parent dee82bc1e6
commit 03c3876f2e
1 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/acpi/spcr.c
View File

@ -188,11 +188,19 @@ int __init parse_spcr(bool earlycon)
uart = "qdf2400_e44"; uart = "qdf2400_e44";
} }
if (xgene_8250_erratum_present(table)) if (xgene_8250_erratum_present(table)) {
iotype = "mmio32"; iotype = "mmio32";
snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, /* for xgene v1 and v2 we don't know the clock rate of the
table->serial_port.address, baud_rate); * UART so don't attempt to change to the baud rate state
* in the table because driver cannot calculate the dividers
*/
snprintf(opts, sizeof(opts), "%s,%s,0x%llx", uart, iotype,
table->serial_port.address);
} else {
snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype,
table->serial_port.address, baud_rate);
}
pr_info("console: %s\n", opts); pr_info("console: %s\n", opts);