openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

SoCFPGA DTS updates for v4.2 

- Add accelerometer to sockit
 - Update and clean up support for the Arria10 platform
 - Add sdmmc_clk/4 clock node SoCFPGA Cyclone5/Arria5
 - Update ethernet nodes with multicast/unicast/fifo-depth properties
 - Add clocks for Arria10 platform
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJVUPgLAAoJEBmUBAuBoyj0tKMP/Av4Ls7Wm8kNatdA64oaefBa
 OJ8b2XIINiXCtYUexmw1auNiYglFfIMQkh/NHe83tl9USk7Tg0TgR7Hpe4TfkO57
 woSrz6GgIhwv3tHJiYZeczuZhlTwEl1sie/w3i+HYQRP8+nXyT5dw270tpMRTG5g
 +npltqCrqwa3vhHo5Nsz29l260unq/fXr5l59XqtBMp80Z3S4NStNA+gPqg5P1yI
 34RZkJvDrf8ePemRd4Et7ZLg7+Wv4SswomCEhg//WaO11EbwTLCOXc0D8MQ5ZThE
 I8S3jplpgn85fauOm8d++7jt7T5tIPmPUowxtkI9byLgaWYb7XtMkF/qAuqEWG5f
 FTfgh1GTJU8NCrlQLTXsehNuUENq+NBIEI75TlRSArTUUkUkrXua+PQAEe3Ae9B1
 Afniu3yIiPzgQgo+aXzbePuVyBNbf5VETB7AMsVf4PeVov8esHklAMt0sqXyepwy
 N6kvb6kAFI3U6yWhGMhljCT+oXconCnVUSfWm16/ss17TFWg1nJwGfDhphvEvyKu
 05ILLIYTUW6NRTbIE4Cy2peaDKXV/ZgN348JGtq27+4RKLV2sPtEbIDCEhzedKxS
 IeO+ACTzzMGnlhp9j6T0afQ0mpWPfExDBTvfqItFc7YATUdYv8Ja5VDeGFmpDc81
 LF+lhVo0blxtRdY3QpDf
 =fVwi
 -----END PGP SIGNATURE-----

Merge tag 'socfpga_dts_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

Pull "SoCFPGA DTS updates for v4.2" from Dinh Nguyen:

- Add accelerometer to sockit
- Update and clean up support for the Arria10 platform
- Add sdmmc_clk/4 clock node SoCFPGA Cyclone5/Arria5
- Update ethernet nodes with multicast/unicast/fifo-depth properties
- Add clocks for Arria10 platform

* tag 'socfpga_dts_for_v4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: dts: add clocks to the Arria10 platform
  ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth properties
  ARM: socfpga: dts: Add multicast bins and unicast filter entries
  ARM: socfpga: dts: Add a clock node for sdmmc CIU
  ARM: socfpga: dts: rename socdk board file to socdk_sdmmc
  ARM: socfpga: dts: enable UART1 for the debug uart
  ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10
  ARM: socfpga: dts: add cpu1-start-addr for Arria 10
  ARM: socfpga: dts: Add adxl34x
This commit is contained in:
Arnd Bergmann 2015-05-12 17:22:11 +02:00
parent 9ef1375d00 da29d824a6
commit 03d6d706a2
6 changed files with 380 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/Makefile
View File

@ -498,7 +498,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \

14
arch/arm/boot/dts/socfpga.dtsi
View File

@ -451,6 +451,14 @@ sdmmc_clk: sdmmc_clk {
clk-phase = <0 135>;
};
sdmmc_clk_divided: sdmmc_clk_divided {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&sdmmc_clk>;
clk-gate = <0xa0 8>;
fixed-divider = <4>;
};
nand_x_clk: nand_x_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
@ -488,6 +496,8 @@ gmac0: ethernet@ff700000 {
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
status = "disabled";
};
@ -504,6 +514,8 @@ gmac1: ethernet@ff702000 {
reset-names = "stmmaceth";
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
status = "disabled";
};
@ -635,7 +647,7 @@ mmc: dwmmc0@ff704000 {
fifo-depth = <0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
};

335
arch/arm/boot/dts/socfpga_arria10.dtsi
View File

@ -21,18 +21,6 @@ / {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
serial0 = &uart0;
serial1 = &uart1;
timer0 = &timer0;
timer1 = &timer1;
timer2 = &timer2;
timer3 = &timer3;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -98,6 +86,21 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
cb_intosc_ls_clk: cb_intosc_ls_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
f2s_free_clk: f2s_free_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -107,16 +110,286 @@ main_pll: main_pll {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
compatible = "altr,socfpga-pll-clock";
clocks = <&osc1>;
compatible = "altr,socfpga-a10-pll-clock";
clocks = <&osc1>, <&cb_intosc_ls_clk>,
<&f2s_free_clk>;
reg = <0x40>;
main_mpu_base_clk: main_mpu_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
div-reg = <0x140 0 11>;
};
main_noc_base_clk: main_noc_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
div-reg = <0x144 0 11>;
};
main_emaca_clk: main_emaca_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x68>;
};
main_emacb_clk: main_emacb_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x6C>;
};
main_emac_ptp_clk: main_emac_ptp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x70>;
};
main_gpio_db_clk: main_gpio_db_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x74>;
};
main_sdmmc_clk: main_sdmmc_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk"
;
clocks = <&main_pll>;
reg = <0x78>;
};
main_s2f_usr0_clk: main_s2f_usr0_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x7C>;
};
main_s2f_usr1_clk: main_s2f_usr1_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x80>;
};
main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x84>;
};
main_periph_ref_clk: main_periph_ref_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x9C>;
};
};
periph_pll: periph_pll {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
compatible = "altr,socfpga-pll-clock";
clocks = <&osc1>;
compatible = "altr,socfpga-a10-pll-clock";
clocks = <&osc1>, <&cb_intosc_ls_clk>,
<&f2s_free_clk>, <&main_periph_ref_clk>;
reg = <0xC0>;
peri_mpu_base_clk: peri_mpu_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
div-reg = <0x140 16 11>;
};
peri_noc_base_clk: peri_noc_base_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
div-reg = <0x144 16 11>;
};
peri_emaca_clk: peri_emaca_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xE8>;
};
peri_emacb_clk: peri_emacb_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xEC>;
};
peri_emac_ptp_clk: peri_emac_ptp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF0>;
};
peri_gpio_db_clk: peri_gpio_db_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF4>;
};
peri_sdmmc_clk: peri_sdmmc_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF8>;
};
peri_s2f_usr0_clk: peri_s2f_usr0_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xFC>;
};
peri_s2f_usr1_clk: peri_s2f_usr1_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0x100>;
};
peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0x104>;
};
};
mpu_free_clk: mpu_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
reg = <0x60>;
};
noc_free_clk: noc_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
reg = <0x64>;
};
s2f_user1_free_clk: s2f_user1_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
reg = <0x104>;
};
sdmmc_free_clk: sdmmc_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
fixed-divider = <4>;
reg = <0xF8>;
};
l4_sys_free_clk: l4_sys_free_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&noc_free_clk>;
fixed-divider = <4>;
};
l4_main_clk: l4_main_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
div-reg = <0xA8 0 2>;
clk-gate = <0x48 1>;
};
l4_mp_clk: l4_mp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
div-reg = <0xA8 8 2>;
clk-gate = <0x48 2>;
};
l4_sp_clk: l4_sp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
div-reg = <0xA8 16 2>;
clk-gate = <0x48 3>;
};
mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&mpu_free_clk>;
fixed-divider = <4>;
clk-gate = <0x48 0>;
};
sdmmc_clk: sdmmc_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&sdmmc_free_clk>;
clk-gate = <0xC8 5>;
};
qspi_clk: qspi_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_main_clk>;
clk-gate = <0xC8 11>;
};
nand_clk: nand_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_mp_clk>;
clk-gate = <0xC8 10>;
};
spi_m_clk: spi_m_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_main_clk>;
clk-gate = <0xC8 9>;
};
usb_clk: usb_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_mp_clk>;
clk-gate = <0xC8 8>;
};
s2f_usr1_clk: s2f_usr1_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&peri_s2f_usr1_clk>;
clk-gate = <0xC8 6>;
};
};
};
@ -128,6 +401,8 @@ gmac0: ethernet@ff800000 {
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
status = "disabled";
};
@ -138,6 +413,10 @@ gmac1: ethernet@ff802000 {
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
status = "disabled";
};
@ -148,6 +427,10 @@ gmac2: ethernet@ff804000 {
interrupt-names = "macirq";
/* Filled in by bootloader */
mac-address = [00 00 00 00 00 00];
snps,multicast-filter-bins = <256>;
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <16384>;
status = "disabled";
};
@ -268,6 +551,9 @@ mmc: dwmmc0@ff808000 {
reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>;
clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
clock-names = "biu", "ciu";
status = "disabled";
};
ocram: sram@ffe00000 {
@ -284,6 +570,7 @@ rst: rstmgr@ffd05000 {
sysmgr: sysmgr@ffd06000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd06000 0x300>;
cpu1-start-addr = <0xffd06230>;
};
/* Local timer */
@ -291,30 +578,39 @@ timer@ffffc600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xffffc600 0x100>;
interrupts = <1 13 0xf04>;
clocks = <&mpu_periph_clk>;
};
timer0: timer0@ffc02700 {
compatible = "snps,dw-apb-timer";
interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffc02700 0x100>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
};
timer1: timer1@ffc02800 {
compatible = "snps,dw-apb-timer";
interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffc02800 0x100>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
};
timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer";
interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd00000 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
};
timer3: timer3@ffd00100 {
compatible = "snps,dw-apb-timer";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xffd01000 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
};
uart0: serial0@ffc02000 {
@ -323,6 +619,7 @@ uart0: serial0@ffc02000 {
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial1@ffc02100 {
@ -331,6 +628,8 @@ uart1: serial1@ffc02100 {
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
status = "disabled";
};
usbphy0: usbphy@0 {
@ -343,6 +642,8 @@ usb0: usb@ffb00000 {
compatible = "snps,dwc2";
reg = <0xffb00000 0xffff>;
interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_clk>;
clock-names = "otg";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@ -361,6 +662,7 @@ watchdog0: watchdog@ffd00200 {
compatible = "snps,dw-wdt";
reg = <0xffd00200 0x100>;
interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sys_free_clk>;
status = "disabled";
};
@ -368,6 +670,7 @@ watchdog1: watchdog@ffd00300 {
compatible = "snps,dw-wdt";
reg = <0xffd00300 0x100>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sys_free_clk>;
status = "disabled";
};
};

12
arch/arm/boot/dts/socfpga_arria10_socdk.dts → arch/arm/boot/dts/socfpga_arria10_socdk.dtsi Executable file → Normal file
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2014 Altera Corporation <www.altera.com>
* Copyright (C) 2015 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -14,8 +14,6 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
#include "socfpga_arria10.dtsi"
/ {
@ -40,9 +38,9 @@ osc1 {
};
};
};
serial0@ffc02000 {
status = "okay";
};
};
};
&uart1 {
status = "okay";
};

26
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts Normal file
View File

@ -0,0 +1,26 @@
/*
* Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
&mmc {
status = "okay";
num-slots = <1>;
broken-cd;
bus-width = <4>;
};

16
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
View File

@ -68,3 +68,19 @@ &mmc0 {
&usb1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&i2c1{
status = "okay";
accel1: accel1@53{
compatible = "adxl34x";
reg = <0x53>;
interrupt-parent = < &portc >;
interrupts = <3 2>;
};
};