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ARM: dts: r8a7743: Add OPP table for frequency scaling
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - clock-latency = 300 us Approximate worst-case latency to do clock transition for every OPPs. Using an arbitrary safe value similar to r8a7791(R-Car M2) Soc. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since DVS is not supported in RZ/G1 Soc. Note:This also fixes the below errors seen on kernel logs [ 0.876877] cpu cpu0: dev_pm_opp_get_opp_count: OPP table not found (-19) [ 0.883727] cpu cpu1: cpufreq_init: failed to get clk: -2 Signed-off-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -38,8 +38,17 @@ cpu0: cpu@0 {
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reg = <0>;
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clock-frequency = <1500000000>;
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clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
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clock-latency = <300000>; /* 300 us */
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power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
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next-level-cache = <&L2_CA15>;
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1500000 1000000>,
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<1312500 1000000>,
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<1125000 1000000>,
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< 937500 1000000>,
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< 750000 1000000>,
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< 375000 1000000>;
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};
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cpu1: cpu@1 {
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